Adaptive minimum duty cycle design for extending dc-dc converter operating voltage range

Abstract

This application relates to an adaptive minimum duty cycle design for extending the operating voltage range of a DCDC converter. A method for a switched mode power supply (SMPS) includes providing an error voltage signal based on a difference between a sampled output voltage of the SMPS and a target voltage, and generating a clock signal characterized by an oscillation frequency. A switching control signal is generated based on the error voltage signal and the clock signal using pulse width modulation (PWM). The method further includes varying the oscillation frequency of the clock signal in a current generation circuit as a function of the error voltage signal, and applying the switching control signal to control a power switch of the SMPS.

Description

Technical Field

[0001] This disclosure generally relates to an adaptive minimum duty cycle design for extending the operating voltage range of a DC-DC converter. Background Technology

[0002] Switching mode power supplies (SMPS) (such as DC-DC converters) are widely used in personal, automotive, and industrial electronic equipment, such as DC-DC power supplies, LED drivers, battery chargers, and many other applications. To support a wide range of applications, DC-DC converters are required to cover a broad range of input voltages (VIN) and output voltages (VOUT). DC-DC converters have the ability to handle a wide range of VIN and VOUT voltages, eliminating the need for multiple designs to cover only a portion of the required operating voltage range, thus saving cost and time-to-market.

[0003] In switching-mode power supplies, the minimum duty cycle (D_min) or minimum on-time (Ton_min) is limited by logic delays and the charging / discharging times associated with its output FETs. These include the propagation delay of the controller logic, the blanking time of the high-side sense amplifier, the dead time required to avoid breakdown current, and the rise and fall times of the driver. All these necessary delays are required to ensure stable converter operation. Failure to meet these timing requirements can easily lead to converter failure, instability, and, in the worst case, irreversible damage. Therefore, the physical requirements for D_min limit the VIN (or VOUT) operating range of the switching-mode power supply.

[0004] The inventors have observed numerous drawbacks to these conventional solutions. For example, some conventional designs reduce the minimum duty cycle (D_min) or minimum on-time (Ton_min) of the buck converter by, for instance, a) using process techniques with lower supply voltages to shorten logic delays, b) using new topologies for high-side sense amplifiers with shorter blanking times, c) increasing driver strength to accelerate rise and fall times, or d) using complex circuitry similar to that of constant on-time (COT) converters, which requires valley and peak current sensing and additional circuitry. All of these solutions increase cost, increase trade-offs in converter performance, or result in added circuitry complexity. For example, cost can increase due to the additional mask layers and process steps required to accelerate digital logic with lower supply voltages. Increasing driver strength can lead to more severe electromagnetic emission (EMI) problems, hindering application in some systems. Therefore, in conventional solutions, trade-offs are made between operating voltage range, cost, and performance.

[0005] Another conventional design uses a clock to reduce the duty cycle of the buck converter. This clock reduces its oscillation frequency by varying the current directly with the input voltage of the buck converter to reduce the current required for operation at higher input voltages. However, its open-loop design primarily considers variations in the input voltage. In embodiments of the present invention, both input and output voltage variations are considered together with the error voltage signal in the closed-loop feedback system to provide precise control for a wider range of applications.

[0006] Therefore, an improved solution for the minimum on-time limit in converters is highly needed. Summary of the Invention

[0007] Embodiments of this invention provide a cost-effective solution to extend the minimum duty cycle of a power converter to increase the operating voltage range. A closed-loop adaptive minimum duty cycle circuit uses an error voltage derived from the output to change the converter's switching frequency, thereby extending the minimum duty cycle while maintaining minimum system on-time requirements. This design extends the operating input voltage range and provides stable waveforms in the output voltage, switching nodes, and inductor current without pulse skipping and subharmonic oscillations. This adaptive solution can also be applied to all types of DC-DC converters, not just buck converters, such as controllers for boost and buck-boost converters.

[0008] As an example, embodiments of the present invention demonstrate a Switching Mode Power Supply (SMPS) comprising: an input node for coupling to an input voltage; an output node for providing an output voltage; a first switch coupled between the input node and the switching node; a second switch coupled between the switching node and a ground node; and an inductor coupled between the switching node and the output node for providing an inductor current to the output node in response to a switching control signal controlled by the switches. The SMPS further comprises: an error amplifier configured to compare a sampled output voltage with a first reference voltage to provide an error voltage signal; an oscillator circuit for providing a clock signal; an adaptive minimum duty cycle circuit configured to receive the error voltage signal and generate a current signal in response to the error voltage signal to change the oscillation frequency of the clock signal; and a pulse width modulation (PWM) circuit configured to receive the error voltage signal and the clock signal and provide the switching control signal to control the switches.

[0009] In another example, embodiments of the present invention describe a controller for a Switching Mode Power Supply (SMPS), the controller comprising: an error amplifier configured to compare a sampled output voltage of the SMPS with a first reference voltage to generate an error voltage signal; and an oscillator circuit configured to provide a clock signal. The SMPS also includes an adaptive minimum duty cycle circuit configured to receive the error voltage signal and, in response to the error voltage signal, generate a current signal to change the oscillation frequency of the clock signal. The SMPS further includes a PWM switching control circuit configured to receive the error voltage signal and the clock signal, and to provide a PWM switching control signal for controlling the power switching of the SMPS.

[0010] In another example, a further embodiment of the invention demonstrates a method for a Switching Mode Power Supply (SMPS), the method comprising: providing an error voltage signal based on the difference between a sampled output voltage of the SMPS and a target voltage; generating a clock signal characterized by an oscillation frequency; and generating a switching control signal based on the error voltage signal and the clock signal using pulse width modulation (PWM). The method further comprises changing the oscillation frequency of the clock signal according to the error voltage signal, and applying the switching control signal to control the power switching of the SMPS.

[0011] definition

[0012] The terms used in this disclosure generally have their common meanings in the art within the context of this invention. Certain terms are discussed below to provide additional guidance to those skilled in the art regarding the description of the invention. It should be understood that the same thing can be expressed in more than one way. Therefore, alternative languages ​​and synonyms may be used.

[0013] The half-bridge circuit used in this article refers to a switching circuit with high-side transistors and low-side transistors that are vertically stacked and connected at the midpoint.

[0014] The power switch used in this article refers to a semiconductor switch, such as a transistor, designed to handle high power levels.

[0015] A power MOSFET is a special type of metal-oxide-semiconductor field-effect transistor (MOSFET) designed to handle significant power levels. An example of a power MOSFET used for switching operations is called a laterally diffused MOS, or LDMOS for short.

[0016] A power converter is an electrical or electromechanical device used to convert electrical energy, such as converting or changing voltage, current, or frequency between AC and DC, or some combination of these conversions. Power converters typically include voltage regulation.

[0017] Switching regulators, or switching mode power supplies (SMPS), use active devices that switch on and off to maintain an average output voltage. In contrast, linear regulators are designed to function as variable resistors, continuously adjusting the voltage divider network to maintain a constant output voltage and continuously dissipate power.

[0018] As used in this article, duty cycle is the fraction of a period during which a signal or system is active.

[0019] The pulse width modulation (PWM) used in this article is a control mechanism that uses rectangular pulse waves to modulate the pulse width or duty cycle of the rectangular pulse wave, resulting in a change in the average value of the waveform.

[0020] The DC-DC or DC-to-DC converter used in this article is an electronic circuit that converts a direct current (DC) source from one voltage level to another.

[0021] The buck converter used in this article is a DC-to-DC power converter that gradually reduces the voltage of its input (power supply) while drawing less average current.

[0022] The boost converter used in this article is a DC-to-DC power converter that gradually increases the voltage (while gradually decreasing the current) from its input (power supply) to its output.

[0023] The buck-boost converter used in this article is a DC-to-DC converter with an output voltage value that is greater than or less than the input voltage.

[0024] The error amplifier used in this paper is an electronic circuit that amplifies the error signal based on the difference between the reference signal and the input signal. Error amplifiers are most commonly found in feedback voltage control circuits, where the sampled output voltage of the controlled circuit is fed back and compared with a stable reference voltage. Any difference between the two will generate a compensation error voltage.

[0025] A voltage reference is an electronic device that ideally generates a fixed (constant) voltage without taking into account the load, power supply variations, temperature variations, and the passage of time.

[0026] The reference voltage is the voltage value used as the target for the comparison operation.

[0027] When the term "identical" is used to describe two quantities, it means that the values ​​of the two quantities are determined to be identical within measurement constraints. Attached Figure Description

[0028] Figure 1 This is a simplified schematic / block diagram illustrating a switching mode power supply (SMPS) that embodies certain aspects of the present invention;

[0029] Figure 2This is a simplified schematic diagram illustrating a switching mode power supply (SMPS) that embodies certain aspects of the present invention;

[0030] Figure 3 The illustrations demonstrate certain aspects of the invention. Figure 1 and 2 Analog timing signal graphs of the operation of the SMPS 100;

[0031] Figure 4 This is a simplified flowchart illustrating a method of switching mode power supply (SMPS) that embodies certain aspects of the present invention;

[0032] Figure 5 The demonstration includes simulated waveforms illustrating the operation of a buck converter with adaptive minimum duty cycle.

[0033] Figure 6 Demonstrating certain aspects of the invention Figure 5 A magnified view of a portion of the waveform;

[0034] Figure 7 The diagram illustrates simulated waveforms demonstrating the operation of a buck converter without the aforementioned adaptive minimum duty cycle, illustrating certain aspects of the invention; and

[0035] Figure 8 Demonstrating certain aspects of the invention Figure 7 A magnified view of a portion of the waveform. Detailed Implementation

[0036] For a buck converter operating in continuous conduction mode, its duty cycle can be expressed as shown by the following equation (1):

[0037] Duty cycle (D) = Ton / T = VOUT / VIN (1)

[0038] Where Ton is the on-time of the high-side FET, and VOUT and VIN are the output and input voltages, respectively. When Ton reaches its physical minimum on-time value, the minimum duty cycle D_min becomes:

[0039] D_min=Ton_min / T=VOUT_given / VIN_max (2)

[0040] For a given fixed output voltage VOUT_given, the corresponding VIN_max can only be pulled up to a specific voltage level without violating the VOUT-VIN relationship defined in equation (2). Applying any VIN voltage higher than the VIN_max value will cause instability or abnormal behavior of the buck converter.

[0041] To extend the range of VIN operations defined in equation (2), one approach is to increase the switching period (T) or decrease the switching frequency. As the switching period increases, the corresponding VIN_max can be extended accordingly.

[0042] Similarly, for a given fixed input voltage VIN_given, the lower limit of VOUT_min can be redefined in the following D_min equation (3):

[0043] D_min=Ton_min / T=VOUT_min / VIN_given (3)

[0044] If the switching period (T) can be lengthened, then VOUT_min can be further reduced. Therefore, as shown in equations (2) and (3), by lengthening the switching period (T) of the buck converter, D_min can be reduced, and the operating voltage range of VIN (or VOUT) can be extended.

[0045] In some embodiments, an "adaptive minimum duty cycle circuit" is used in the controller of the DC-DC converter to smoothly extend its minimum duty cycle for a wider operating voltage range. For existing products without an "adaptive minimum duty cycle design," the buck converter will exhibit instability when the switching node voltage, inductor current, or output voltage waveform is pushed beyond their D_min condition.

[0046] When the buck converter reaches its minimum on-time (Ton_min) condition, the "adaptive minimum duty cycle design" can smoothly and adaptively extend the switching period (T_adaptive), so that it can adaptively reduce its effective duty cycle (Ton_min / T_adaptive) until VIN (or VOUT) reaches its final target value.

[0047] The extended minimum duty cycle satisfies the operating requirements specified in equations (1) to (3) listed above. Therefore, no instability is observed in the inductor current or output voltage waveform. The novel adaptive controller design successfully extends the operating voltage range of VIN (or VOUT) without significantly increasing cost, complex high-voltage or valley current sensing, trade-offs in system EMI performance, or the risk of irreversible damage.

[0048] Figure 1 This is a simplified schematic / block diagram illustrating a switching mode power supply (SMPS) that embodies certain aspects of the present invention. For example... Figure 1 As shown, the power converter 100 is an example of an SMPS configured as a buck converter. However, it should be understood that the embodiments described herein are applicable to other types of SMPSs, such as boost converters and buck-boost converters. Figure 1In this example, the SMPS 100 includes an input node 111 for coupling to an input voltage VIN, an output node 112 for providing an output voltage VOUT, a first switch 114 coupled between the input node 111 and a switching node 113, and a second switch 115 coupled between the switching node 113 and a ground node GND. The SMPS 100 also includes an inductor 116 coupled between the switching node 113 and the output node 112 to provide an inductor current I_IND to the output node 112 in response to a first switching control signal 127 and a second switching control signal 128, under the control of the first switch 114 and the second switch 115. Figure 1 The output capacitor Co and resistor RL of the load device representing the SMPS 100 are also shown.

[0049] exist Figure 1 In this configuration, the SMPS is in a half-bridge configuration. The first switch 114 is also referred to as a high-side transistor (HSFET), which is coupled to a second switch 115, which is also referred to as a low-side transistor (LSFET). The first switching control signal 127 is also referred to as an upper gate drive signal (UGD), and the second switching control signal 128 is also referred to as a lower gate drive signal (LGD).

[0050] SMPS 100 also includes: voltage sensing circuit 102, which includes a voltage divider and provides a sampled output voltage signal 122; and current sensing circuit 106, which is coupled to a first switch 114 via a sensing transistor and provides a sensed current voltage signal VLD.

[0051] SMPS 100 further includes a controller comprising an error amplifier 121, a PWM circuit 124, an oscillator circuit 130, a slope compensation circuit 140, and an adaptive minimum duty cycle circuit 150. The error amplifier 121 is configured to compare a sampled output voltage 122 with a first reference voltage VR1 to provide an error voltage signal VCT at the output node 123 of the error amplifier 121. The oscillator circuit 130 is configured to provide a clock signal VSET. The slope compensation circuit 140 is configured to perform slope compensation and provide a sawtooth signal VSUM to the PWM circuit 124. The adaptive minimum duty cycle circuit 150 is configured to receive the error voltage signal VCT and, in response to the error voltage signal VCT, generate a current signal to change the oscillation frequency of the clock signal VSET.

[0052] The pulse width modulation (PWM) circuit 124 includes a comparator PWM CMP configured to compare an error voltage signal VCT and a sawtooth signal VSUM and provide an output signal 125. The PWM circuit 124 also includes a latch 126 configured to receive the output signal 125 from the comparator PWM CMP and a clock signal VSET from the oscillator circuit 130, and to provide first and second switching control signals 127 and 128 to control the first switch 114 and the second switch 115 using PWM control.

[0053] Figure 2 This is a simplified schematic diagram illustrating a switching mode power supply (SMPS) that embodies certain aspects of the present invention. Similar to... Figure 1 , Figure 2 The power converter 100 is described, having an exemplary embodiment of an oscillator circuit 130, a slope compensation circuit 140, an adaptive minimum duty cycle circuit 150, and a current sensing circuit 106.

[0054] like Figure 2 As shown, the oscillator circuit 130 includes: a capacitor 131; a first constant current source 133; a current mirror 134 coupled at node 136 to the first constant current source 133 to provide a first current I1 for charging the capacitor 131; a comparator OSC CMP for comparing the capacitor voltage (VC) on the capacitor 131 with a second reference voltage VR2 for discharging the capacitor 131; and an inverter 137 coupled to the output of the comparator to provide a clock signal (VSET).

[0055] like Figure 2 As shown, the slope compensation circuit 140 includes an amplifier SLPCMP AMP having a positive input node coupled to the capacitor voltage (VC) in the oscillator circuit 130, and a negative input node coupled to a feedback circuit including transistor 144 and resistor 145. The slope compensation circuit 140 also includes a current mirror 146 having a first branch coupled to the amplifier SLPCMP AMP via transistor 144 and a second branch coupled to the voltage signal (VLD) from the current sensing circuit 106 via resistor 147. The slope compensation circuit 140 generates a sawtooth signal VSUM to the PWM circuit 124.

[0056] Still referencing Figure 2The adaptive minimum duty cycle circuit 150 includes a first PMOS transistor (P-type metal-oxide-semiconductor transistor) PM1 with a gate node coupled to an error voltage signal VCT, a first NMOS transistor (N-type metal-oxide-semiconductor transistor) NM1 with a gate node coupled to a third reference voltage VR3, and a first resistor R1. The adaptive minimum duty cycle circuit 150 also includes a current mirror 151, which has a first branch 151-1 coupled to the first NMOS transistor NM1, the first resistor R1, and the first PMOS transistor PM1 connected in series, and a second branch 151-2 providing a second current I2 to the oscillator circuit 130.

[0057] The adaptive minimum duty cycle circuit 150 further includes an adaptive minimum duty cycle enable circuit 153 configured to determine whether a minimum on-time condition has been met, and if so, to provide an adaptive minimum duty cycle enable signal EN_DMIN, which couples a second current I2 to the oscillator circuit 130 at node 136. In some embodiments, the adaptive minimum duty cycle enable circuit 153 is further configured to determine, before providing the adaptive minimum duty cycle enable signal, that the following conditions are met: soft-start complete, output voltage power good, and continuous conduction mode (CCM) or forced PWM mode. Detailed enable sequences will be described in later sections. As used herein, forced PWM mode refers to control that eliminates discontinuous modes by allowing reverse current from the inductor under light loads. In some embodiments, the adaptive minimum duty cycle circuit 150 also includes a second current source 155 (IPTAT). The adaptive minimum duty cycle enable signal EN_DMIN further couples the second current source 155 (IPTAT) to the oscillator circuit 130 and decouples the first constant current source 133 (ICONST) from the oscillator circuit. The IPTAT current is used to compensate for temperature changes caused by the resistance of R1 and the turn-on threshold voltages of NM1 and PM1.

[0058] Figure 3 The illustrations demonstrate certain aspects of the invention. Figure 1 and 2 Analog timing signal graphs of the operation of the SMPS 100. Figure 3 In the middle, the horizontal axis displays time, and the vertical axis displays the following signals:

[0059] The input voltage of VIN–SMPS 100;

[0060] VOUT – Output voltage of SMPS 100;

[0061] EN_DMIN – Adaptive minimum duty cycle enable signal;

[0062] VCT – Error Voltage;

[0063] VSUM – Sawtooth signal;

[0064] The switching frequency of fsw–SMPS; and

[0065] VSW – Switch node voltage.

[0066] The following text is for reference only. Figure 1 , 2 And 3 describes the operation of SMPS 100.

[0067] exist Figure 1 and 2 In this embodiment, the SMPS 100 is configured as a DC-DC buck converter with an adaptive minimum duty cycle (D_min) for extending the operating voltage range. Figure 1 and 2 The current-controlled oscillator 130, the slope compensation block 140, and the adaptive minimum duty cycle control circuit 150 are shown.

[0068] like Figure 2 As shown, the buck converter features a peak current mode controller with a current sensing and voltage regulation loop. The current sensing loop provides inductor current information with slope compensation to eliminate complex conjugate poles associated with the inductor and capacitor at the output, making the inductor a current source for loop compensation and better stability. The oscillator period is based on the time for charging and discharging capacitor 131 using a control current source. As the current value decreases, the charging time of the capacitor to a preset threshold voltage VR2 increases, thus extending the switching clock period or reducing the switching frequency. In the adaptive minimum duty cycle enable circuit 153, the start of the clock period extension is controlled by a sensing circuit (D_DET) for minimum duty cycle detection. Once the clock period is adaptively adjusted, the slope compensation period also changes accordingly to update the compensation within the adjusted clock period.

[0069] The adaptive minimum duty cycle circuit 150 includes circuitry for detecting the minimum duty cycle condition of the buck converter. For example... Figure 2 As shown, it includes: 1) a PMOSFET, PM1, which is used for VCT voltage sensing (VCT is the output of the error amplifier); 2) an NMOSFET, NM1, where a reference voltage VR3 is connected to its gate for controlling the current through resistor R1; and 3) a current mirror 151 for guiding current into the current source of the oscillator and then adaptively adjusting the period of the switching clock.

[0070] In some embodiments, current conduction is only permitted after soft-start, good VOUT power, and the converter operating in either Continuous Conductive Mode (CCM) or Forced PWM Mode. The CLK_EN signal is asserted high when the buck converter is in either operating mode. If the DC-DC buck converter is in Pulse Frequency Modulation (PFM) mode, the oscillator is off, and the CLK_EN signal is pulled low, thus turning off the adaptive minimum duty cycle circuit. In PFM mode, the VOUT voltage is regulated via a hysteresis mechanism by monitoring the VOUT voltage and then replenishing charge to the output when the VOUT voltage drops below a preset threshold voltage. Furthermore, the adaptive minimum duty cycle circuit will not be activated until a preset duty cycle (D) is reached; for example, for a switching frequency of 1 MHz, D = 8%, corresponding to 80 ns of Ton. Before the adaptive minimum duty cycle circuit is activated, the buck converter operates at a fixed switching frequency. Once the adaptive circuit is activated, the buck converter operates at an adaptive switching frequency, extending the energy of the baseband and thus potentially reducing EMI issues.

[0071] like Figure 1 and 2 As shown, the oscillator provides a switching clock signal (VSET) and an additional slope-compensated ramp voltage to form the summation ramp (VSUM) for the PWM loop. The PWM loop begins on the rising edge of the clock by turning on the high-side FET (HSFET), and the HSFET remains on until the VSUM waveform intersects with the output voltage (VCT) of the error amplifier, as shown. Figure 3 The VCT and VSUM curves are illustrated in the diagram. The high-side FET (HSFET) then turns off, and the low-side FET (LSFET) turns on until the next PWM cycle. For a given fixed VOUT voltage, the on-time of the high-side FET decreases as the VIN voltage increases. The voltage control loop responds to demand by reducing the output voltage (VCT) of the error amplifier. When the VCT voltage drops, it intersects the ramp waveform VSUM earlier, resulting in a smaller duty cycle. The minimum on-time (Ton_min) of the HSFET is set by the required logic delay, driver timing, and others discussed earlier, thus limiting the minimum duty cycle and operating voltage range.

[0072] like Figure 2 As shown, the adaptive minimum duty cycle circuit 150 continuously monitors the VCT until it meets the condition specified in the following equation.

[0073] V_RTOP=VR3-Vthn (4)

[0074] V_RBOT=VCT+Vthp (5)

[0075] In order to turn on the sensing circuit and allow current to flow

[0076] V_RTOP>V_RBOT (6)

[0077] Where V_RTOP and V_RBOT are the top and bottom voltages of R1, Vthn and Vthp are the turn-on threshold voltages of NM1 and PM1 respectively, and VCT is the output voltage of the error amplifier.

[0078] When V_RTOP>V_RBOT, current begins to flow in R1, and the current mirror will reflect the current ( Figure 2 The current I2 in the adaptive minimum duty cycle circuit 150 is directed to the control current source 133 or 155 of the oscillator circuit 130, effectively reducing the amount of current (I1) used to charge the capacitor in the oscillator, which extends the period of the PWM clock signal. Therefore, the minimum duty cycle can be reduced to a smaller amount than the fixed Ton_min. Consequently, the operating voltage range will be extended accordingly. Since the period of the PWM clock signal increases linearly with the amount of current flowing through R1, the clock period will also be smoothly and adaptively changed by the error voltage VCT.

[0079] To enable more efficient and robust operation of the buck converter using an adaptive minimum duty cycle circuit, several supplementary blocks exist to ensure successful operation across various process and temperature ranges. For example... Figure 2 As demonstrated, to conserve quiescent current in low-power saving mode, the adaptive circuit remains off until CCM operation is required. As mentioned above, it is gated by the CLK_EN signal and shuts down during PFM operation. The adaptive circuit does not interfere with the soft-start process; therefore, it remains off until the VOUT voltage reaches a power-good state. Furthermore, the adaptive minimum duty cycle circuit only activates after the buck converter reaches a preset duty cycle. The circuitry for duty cycle detection compares 1) the average value of the VSW node voltage with 2) a reference voltage set by a predetermined percentage of the supply voltage to obtain duty cycle information. Since the average value of the VSW node voltage is also proportional to the supply voltage (i.e., the average value of the VSW node voltage equals D x VIN, where D is the duty cycle and VIN is the supply voltage), the obtained duty cycle information will remain the same despite variations in process, supply voltage, and temperature (PVT). In other words, the adaptive minimum duty cycle circuit will remain on at a preset duty cycle at the PVT corner.

[0080] Once the minimum duty cycle adaptation begins, the clock cycle deviation is determined by the amount of pilot current (i.e., the control current source drawn into the oscillator). Figure 2 The I_STEERING in the equation is determined as shown in equation (7):

[0081]

[0082] Where M is a fixed current mirror ratio, but the values ​​of V_RTOP, V_RNOT, and R1 vary at the PVT corner due to changes in transistor threshold voltage and resistor resistance. Therefore, VR3 is trimmed at the process corner. The current mirror has good output impedance to obtain a constant output current under varying supply voltage, and uses an IPTAT current source to minimize the temperature coefficient of the pilot current. IPTAT current is a current proportional to absolute temperature. As temperature increases, IPTAT current increases. Since the threshold voltages of transistors NM1 and PM1, as well as the resistance of R1, all change with temperature, the I2 current will also change with temperature. When the adaptive minimum duty cycle circuit is enabled, the IPTAT current is used to compensate for temperature variations.

[0083] refer to Figure 3 For a fixed VOUT voltage, as VIN increases, starting from time T1, the output voltage VCT of the error amplifier decreases; therefore, the duty cycle decreases. When the input voltage VIN increases to the threshold voltage VIN_C_H, at time T2, the DC-DC converter will reach the Ton = Ton_min condition. The adaptive DMIN circuit is then enabled, and the EN_DMIN signal switches high at time T2. The switching frequency (fsw) begins to decrease, and its period (T) increases. Therefore, its duty cycle will continue to decrease adaptively until VIN reaches its maximum value at time T3. Conversely, as VIN begins to decrease at time T4, fsw increases until VIN drops to VIN_C_L = VIN_C_H – VIN_hysteresis at time T5. The EN_DMIN signal then switches low to turn off the adaptive DMIN circuit, and fsw returns to its normal frequency. VIN_hysteresis is used to prevent mode switching.

[0084] In some embodiments, the Ton = Ton_min condition is determined by measuring the width of Ton and comparing it directly with a preset Ton_min threshold. Essentially, using a fixed switching period T, Ton is the on-time of the HSFET when the VSW node voltage is high. When the HSFET is off and the LSFET is on, the VSW node voltage goes low. The average high-low VSW node voltage is equal to D x VIN voltage, and D = VOUT / VIN = Ton / T. For example, if T = 1µs (fsw = 1MHz), the preset threshold Ton = Ton_min is 80ns, resulting in D = 8%. If the average VSW node voltage becomes 8% of the VIN voltage, then Ton = Ton_min. Therefore, the start of the Ton_min condition can be determined by comparing the average VSW node voltage with a preset VIN voltage percentage using a comparator. Thus, once Ton reaches the Ton_min threshold, the adaptive DMIN circuit is enabled, and the EN_DMIN signal switches high, thereby initiating adaptive minimum duty cycle operation.

[0085] Figure 4 This is a simplified flowchart illustrating a method for using a switching mode power supply (SMPS) that embodies certain aspects of the present invention. Figure 4 The method 400 for operating SMPS shown can be briefly summarized as follows and further described below.

[0086] At 410, an error voltage signal is provided based on the difference between the sampled output voltage of the SMPS and the target voltage signal;

[0087] At 420, a clock signal characterized by its oscillation frequency is generated;

[0088] At 430, monitor the duty cycle or connection time Ton;

[0089] In step 431, determine whether Ton is equal to or less than Ton_min;

[0090] If “yes”, then proceed to step 440; otherwise, proceed directly to step 450.

[0091] At 440, the oscillation frequency of the clock signal is changed according to the error voltage signal;

[0092] At 450, pulse width modulation is used to generate a switching control signal based on the error voltage signal and the clock signal;

[0093] At 460, a switching control signal is applied to control the power switching of the SMPS.

[0094] At 410, method 400 includes providing an error voltage signal (VCT) based on the difference between the sampled output voltage of the SMPS and a target voltage signal. In some embodiments, for example Figure 2 as shown in, error amplifier 121 is configured to compare the sampled output voltage 122 with a first reference voltage VR1 to provide an error voltage signal VCT at the output node 123 of error amplifier 121.

[0095] At 420, method 400 includes generating a clock signal characterized by an oscillation frequency. In some embodiments, for example Figure 2 as shown in, generating the clock signal includes charging capacitor 131 using a first current from a first constant current source 133 and comparing the voltage (VC) on the capacitor with a second reference voltage (VR2) using a comparator (OSC CMP) to determine the condition for discharging the capacitor.

[0096] At 430, the method includes monitoring the duty cycle D or the on - time Ton. In some embodiments, as Figure 2 shown in, comparing the average VSW voltage 113 with a preset percentage (e.g., 8%) of the input voltage VIN 111 forms the D_DET circuit 153. The average value of the high - low switched VSW node voltage is equal to the D x VIN voltage and D = VOUT / VIN = Ton / T. For example, if T = 1uS (fsw = 1MHz), the preset threshold Ton = Ton_min is 80nS, resulting in D = 8%. If the average VSW node voltage becomes 8% of the VIN voltage, then Ton = Ton_min.

[0097] At 431, the method includes using a comparator having a first input coupled from a preset percentage of the input voltage and a second input coupled from the average VSW node voltage. If the average VSW node voltage is equal to or less than the preset percentage of the input voltage, the comparator outputs a high signal, indicating that the Ton = <Ton_min condition is reached, and enabling the adaptive DMIN circuit to send a clock signal with a slowed switching frequency to the subsequent step 440. Otherwise, the oscillator clock signal with the normal switching frequency is directly sent to the subsequent step 450.

[0098] At 440, the method includes changing the oscillation frequency of a clock signal based on an error voltage signal. Here, changing the oscillation frequency includes generating a second current based on the error voltage signal and using the second current to change the charging current of a capacitor. The method also includes using an adaptive minimum duty cycle circuit 150, which includes a first PMOS transistor (P-type metal-oxide-semiconductor transistor) PM1 having a gate node coupled to the error voltage signal VCT, a first NMOS transistor (N-type metal-oxide-semiconductor transistor) NM1 having a gate node coupled to a third reference voltage VR3, and a first resistor R1. The adaptive minimum duty cycle circuit 150 further includes a current mirror 151, which has a first branch 151-1 coupled to the first NMOS transistor NM1, the first resistor R1, and the first PMOS transistor PM1 connected in series, and a second branch 151-2 providing a second current I2 to the oscillator circuit 130. As shown at 431, the method includes determining whether a minimum on-time condition has been met, and if so, providing an adaptive minimum duty cycle enable signal that couples the second current to the oscillator circuit.

[0099] At 450, the method includes generating a switching control signal based on an error voltage signal and a clock signal using pulse width modulation. Figure 1 and 2 In this example, the pulse width modulation (PWM) circuit 124 includes a comparator PWM CMP configured to compare an error voltage signal VCT and a sawtooth signal VSUM, and then provide an output signal 125. The PWM circuit 124 also includes a latch 126 configured to receive the output signal 125 from the comparator PWM CMP and a clock signal VSET from the oscillator circuit 130, and to provide first and second switching control signals 127 and 128 to control the first switch 114 and the second switch 115 using PWM control.

[0100] In 460, the method includes applying a switching control signal to control the power switching of the SMPS. Figure 1 and 2 In one example, the PWM circuit 124 is configured to receive the output signal 125 from the comparator PWM CMP and the clock signal VSET from the oscillator circuit 130, and to provide first and second switching control signals 127 and 128 to control the first switch 114 and the second switch 115 using PWM control.

[0101] In some embodiments, determining whether a minimum on-time condition has been met includes comparing a segmented input voltage with a threshold voltage. In an alternative embodiment, determining whether a minimum on-time condition has been met includes comparing a measured on-time (Ton) with a preset minimum on-time (Ton_min).

[0102] Figure 5 The illustration shows simulated waveforms illustrating the operation of a buck converter with an adaptive minimum duty cycle, demonstrating certain aspects of the invention. Figure 6 exhibit Figure 5 A magnified view of a portion of the waveform. Figure 5 Simulation results are presented for a DC-DC buck converter with an adaptive minimum duty cycle design for a given fixed VOUT = 5V and an extended VIN up to 60V. Figure 6 exhibit Figure 5 The enlarged view shows the clean waveforms of the switching node voltage and inductor current for VIN=60V and VOUT=5V.

[0103] exist Figure 5 and 6 In the diagram, the horizontal axis displays time, and the vertical axis displays the simulated waveforms of the input voltage VIN, output voltage VOUT, voltage VSW at switching node 113, and current I_IND in inductor 116. Figure 5 This demonstrates clean waveforms of the switching node voltage VSW and inductor current I_IND of a converter that actually has an adaptive minimum duty cycle circuit, with VIN operating up to 60V. For example... Figure 6 As shown in the enlarged graphic, in Figure 5 In the central portion of approximately VIN = 60V, for a given fixed 5V VOUT, the DC-DC buck converter can be normally regulated with a clean cycle-by-cycle inductor current waveform I_IND and a continuous switching node voltage waveform VSW.

[0104] Figure 7 The demonstration shows simulated waveforms illustrating the operation of the buck converter without the aforementioned adaptive minimum duty cycle. Figure 8 exhibit Figure 7 A magnified view of a portion of the waveform. Figure 7 Simulation results are shown for a DC-DC buck converter without an adaptive minimum duty cycle design, where VIN only extends up to 31.5V for a given fixed VOUT = 5V. Figure 8 exhibit Figure 7 The enlarged view shows the jump pulses in the switching node waveform for a VIN starting at approximately 31.5V and VOUT = 5V, as well as the instability in the inductor current.

[0105] exist Figure 7 and 8 In the diagram, the horizontal axis displays time, and the vertical axis displays the simulated waveforms of the input voltage VIN, output voltage VOUT, voltage VSW at switching node 113, and current I_IND in inductor 116. For example... Figure 7 and 8As demonstrated, without an adaptive minimum duty cycle circuit, the DC-DC buck converter exhibits abnormal line regulation starting from approximately VIN = 31.5V for a given fixed 5V VOUT. Figure 8 As shown in the magnified graph with abnormal line regulation, the switching node waveform VSW begins to exhibit a jumping pulse 810, and the inductor current waveform I_IND also exhibits a subharmonic oscillation 820. When the condition “D_min = Ton_min / T” is met, Ton reaches its physical minimum (Ton_min), and the switching period T is fixed. Any further attempt to reduce D_min will result in a pulse jump in the switching node (VSW) and an irregular waveform in the inductor current (I_IND). The pulse jump in the switching node waveform causes the VOUT voltage to exhibit irregular voltage ripple. When the irregular VOUT voltage is too low, the converter will attempt to supply more inductor current over several cycles to raise the VOUT voltage, corresponding to an upward slope in the inductor current waveform I_IND. However, due to the irregular waveform, VOUT can be overcorrected to be too high; the converter then pulls charge out of the VOUT node, corresponding to a downward slope in the inductor current waveform I_IND. These irregularities become worse when VIN is pulled to even higher voltages.

[0106] The above embodiments provide a cost-effective solution to extend the minimum duty cycle of a DC-DC converter by utilizing a wider operating voltage range. It eliminates the need for additional mask layers or redesigning complex high-voltage amplifiers. As demonstrated in the simulation results, the DC-DC converter with adaptive minimum duty cycle circuitry exhibits an extended operating range and stable waveforms in the output voltage, switching node, and inductor current, without pulse skipping or subharmonic oscillations. This adaptive approach can also be applied to all types of DC-DC converters, and is not limited to buck converters, such as controllers for boost and buck-boost converters.

[0107] While the subject matter has been described in detail with respect to specific embodiments thereof, those skilled in the art will understand that alternatives, variations, and equivalents of such embodiments can be readily derived once the foregoing is understood. Therefore, it should be understood that this disclosure has been presented for illustrative purposes rather than limiting, and does not exclude the inclusion of such modifications, variations, and / or additions to the subject matter. In fact, the methods and systems described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A switching mode power supply (SMPS), comprising: An input node, which is used to couple to the input voltage; Output node, which is used to provide the output voltage; The first switch is coupled between the input node and the switching node; The second switch is coupled between the switching node and the grounding node; An inductor, coupled between the switching node and the output node, is used to provide inductor current to the output node in response to a switching control signal under the control of the first and second switches; An error amplifier is configured to compare a sampled output voltage with a first reference voltage to provide an error voltage signal; An oscillator circuit, which is used to provide a clock signal; An adaptive minimum duty cycle circuit is configured to receive the error voltage signal and generate a current signal in response to the error voltage signal to change the oscillation frequency of the clock signal. The adaptive minimum duty cycle circuit includes: The first PMOS transistor has its gate node coupled to the error voltage signal; The first NMOS transistor has its gate node coupled to a third reference voltage; First resistor; and A current mirror, which has the following characteristics: The first branch is coupled to the first NMOS transistor, the first resistor, and the first PMOS transistor, which are connected in series; and The second branch provides a second current to the oscillator circuit, the current signal including the second current; and A pulse width modulation (PWM) circuit is configured to receive the error voltage signal and the clock signal, and to provide the switching control signal to control the first and second switches.

2. The switching mode power supply according to claim 1, wherein the oscillator circuit comprises: Capacitor; First constant current source; A current mirror, coupled to the first constant current source, to provide a first current for charging the capacitor; A comparator is used to compare the voltage across the capacitor with a second reference voltage to discharge the capacitor. and An inverter, coupled to the output of the comparator, provides a clock signal.

3. The switching mode power supply according to claim 2, wherein the adaptive minimum duty cycle circuit further includes an adaptive minimum duty cycle enable circuit, the adaptive minimum duty cycle enable circuit being configured to determine whether a minimum on-time condition has been met, and if so, to provide an adaptive minimum duty cycle enable signal, the signal causing the second current to couple to the oscillator circuit.

4. The switching mode power supply of claim 3, wherein the adaptive minimum duty cycle enable circuit is further configured to determine that the following condition is satisfied before providing the adaptive minimum duty cycle enable signal: Soft boot complete; Good output voltage and power; and Continuous conduction mode (CCM) or forced PWM mode.

5. The switching mode power supply according to claim 3, wherein the adaptive minimum duty cycle circuit further includes a second current source (IPTAT); The adaptive minimum duty cycle enable signal further couples the second current source (IPTAT) to the oscillator circuit and decouples the first constant current source from the oscillator circuit.

6. The switching mode power supply according to claim 3, wherein the PWM circuit comprises: A comparator is configured to compare the error voltage signal and the sawtooth signal and provide an output signal; A latch is configured to receive the output signal from the comparator and to provide the switching control signal using pulse width modulation (PWM) to control the first and second switches. and A current sensing circuit, comprising an amplifier, a transistor, and a resistor, is configured to provide a signal.

7. The switching mode power supply according to claim 3, wherein the switching mode power supply is configured as a buck converter.

8. A controller for a switching mode power supply (SMPS), comprising: An error amplifier is configured to compare the sampled output voltage of the SMPS with a first reference voltage to generate an error voltage signal; An oscillator circuit, configured to provide a clock signal; An adaptive minimum duty cycle circuit is configured to receive the error voltage signal and generate a current signal in response to the error voltage signal to change the oscillation frequency of the clock signal, wherein the adaptive minimum duty cycle circuit includes: The first PMOS transistor has its gate node coupled to the error voltage signal; The first NMOS transistor has its gate node coupled to a third reference voltage; First resistor; and A current mirror, which has the following characteristics: The first branch is coupled to the first NMOS transistor, the first resistor, and the first PMOS transistor, which are connected in series; and The second branch provides a second current to the oscillator circuit, the current signal including the second current; and A PWM switching control circuit is configured to receive the error voltage signal and the clock signal, and to provide PWM switching control signals for controlling the first power switch and the second power switch of the SMPS.

9. The controller of claim 8, wherein the oscillator circuit comprises: Capacitor; First constant current source; A current mirror, coupled to the first constant current source, to provide a first current for charging the capacitor; A comparator is used to compare the voltage across the capacitor with a second reference voltage to discharge the capacitor. and An inverter, coupled to the output of the comparator, provides a clock signal.

10. The controller of claim 9, wherein the adaptive minimum duty cycle circuit further includes an adaptive minimum duty cycle enable circuit configured to determine whether a minimum on-time condition has been met, and if so, to provide an adaptive minimum duty cycle enable signal that couples the second current to the oscillator circuit.

11. The controller of claim 10, wherein the adaptive minimum duty cycle circuit further comprises a second current source (IPTAT); The adaptive minimum duty cycle enable signal further couples the second current source (IPTAT) to the oscillator circuit and decouples the first constant current source from the oscillator circuit.

12. A method for switching mode power supplies (SMPS), comprising: An error voltage signal is provided based on the difference between the sampled output voltage of the SMPS and the target voltage; A clock signal characterized by its oscillation frequency is generated by an oscillator circuit; A switching control signal is generated based on the error voltage signal and the clock signal using pulse width modulation (PWM). The oscillation frequency of the clock signal is changed according to the error voltage signal; and Apply the switching control signal to control the first power switch and the second power switch of the SMPS; The method further includes using an adaptive minimum duty cycle circuit, the adaptive minimum duty cycle circuit comprising: The first PMOS transistor has its gate node coupled to the error voltage signal; The first NMOS transistor has its gate node coupled to a third reference voltage; First resistor; and A current mirror, which has the following characteristics: The first branch is coupled to the first NMOS transistor, the first resistor, and the first PMOS transistor connected in series; and The second branch provides a second current to the oscillator circuit.

13. The method of claim 12, wherein generating the clock signal comprises: The capacitor is charged using a first current from a first constant current source; and A comparator is used to compare the voltage across the capacitor with a second reference voltage to determine the conditions for discharging the capacitor.

14. The method of claim 13, wherein changing the oscillation frequency comprises: The second current is generated using the error voltage signal as input; and The second current is used to change the charging current of the capacitor.

15. The method of claim 14, further comprising determining whether a minimum on-time condition has been met, and if so, providing an adaptive minimum duty cycle enable signal that couples the second current to the oscillator circuit.

16. The method of claim 15, wherein determining whether the minimum on-time condition has been met includes comparing the divided input voltage with a threshold voltage.

17. The method of claim 15, wherein determining whether the minimum turn-on time condition has been met includes comparing the measured turn-on time with a preset minimum turn-on time.

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