Method for forming a semiconductor structure and semiconductor structure

Abstract

An embodiment of the present application provides a method for forming a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; wherein, the substrate includes word line trenches with stepped sidewalls; the width of the top of the word line trenches is greater than the width of the bottom of the word line trenches; forming an insulating structure on the sidewalls and the bottom of the word line trenches; and forming a word line structure in the word line trenches formed with the insulating structure.

Description

Technical Field

[0001] The present invention relates to, but is not limited to, a method for forming a semiconductor structure and a semiconductor structure. Background Art

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), include multiple memory cells, word lines (WL), and bit lines (BL). Among them, each memory cell includes a transistor and a capacitor. The WL is used to turn on / off the transistor in the memory cell. When the transistor is turned on, both ends of the transistor are conducting, and the potential on the BL is transmitted to the corresponding capacitor.

[0003] DRAM also includes a node contact (NC) and a bit line contact (BLC). When designing DRAM, the lower surface of the NC, the lower surface of the BLC, and the upper surface of the WL need to be designed on the same horizontal plane. However, in actual fabrication of DRAM, due to the influence of process accuracy, etc., the lower surfaces of the NC and BLC and the upper surface of the WL cannot be exactly on the same horizontal plane. For example, the sidewalls of the NC and BLC will overlap with the sidewalls of the WL. The overlapping part between the sidewalls of the NC and BLC and the sidewalls of the WL is called the overlap region, and the overlap region will generate an overlap capacitance or cause transistor leakage. Summary of the Invention

[0004] Embodiments of the present application provide a method for forming a semiconductor structure and a semiconductor structure.

[0005] In a first aspect, embodiments of the present application provide a method for forming a semiconductor structure, including:

[0006] Providing a substrate; wherein, the substrate includes a word line trench with a stepped sidewall; the width of the top of the word line trench is greater than the width of the bottom of the word line trench;

[0007] Forming an insulating structure on the sidewalls and bottom of the word line trench;

[0008] Forming a word line structure in the word line trench formed with the insulating structure.

[0009] In a second aspect, embodiments of the present application provide a semiconductor structure, including:

[0010] A substrate; the substrate includes a word line trench with a stepped sidewall; the width of the top of the word line trench is greater than the width of the bottom of the word line trench;

[0011] An insulating structure formed on the sidewalls and bottom of the word line trench and a word line structure surrounded by the insulating structure.

[0012] In the embodiments of the present application, the sidewalls of the word line trench are arranged in a stepped shape, and the width of the top of the word line trench is greater than the width of the bottom of the word line trench. Then, an insulating structure is formed on the sidewalls and bottom of the word line trench. By changing the shape of the word line trench, the leakage current or overlap capacitance generated in the related art due to the overlap region is reduced through the insulating structure in the word line trench. Description of the Drawings

[0013] Figures 1A to 1N Schematic diagram of the formation process of the word line structure provided in the related art;

[0014] Figure 2A Schematic flow chart of a method for forming a semiconductor structure provided in the embodiments of the present application;

[0015] Figures 2B to 2F Schematic diagram of the process of forming a word line structure provided in the embodiments of the present application;

[0016] Figure 3A Schematic flow chart of another method for forming a semiconductor structure provided in the embodiments of the present application;

[0017] Figures 3B to 3D Schematic diagram of the structure of the third insulating layer in the semiconductor structure formed in the embodiments of the present application;

[0018] Figure 4A Schematic diagram of the structure of the word line trench provided in the embodiments of the present application;

[0019] Figure 4B Schematic flow chart of the process of forming a word line trench in the method for forming a semiconductor structure provided in the embodiments of the present application;

[0020] Figures 4C to 4J Schematic diagram of the process of forming a word line trench in the semiconductor structure formed in the embodiments of the present application;

[0021] Figure 5A Schematic flow chart of the process of forming a first trench in the method for forming a semiconductor structure provided in the embodiments of the present application;

[0022] Figure 5B and Figure 5C Schematic diagram of the structure of the first trench formed in the method for forming a semiconductor structure provided in the embodiments of the present application;

[0023] Figure 6 Schematic diagram of the structure of the second trench formed in the method for forming a semiconductor structure provided in the embodiments of the present application;

[0024] Figure 7A Schematic flow chart of forming a word line structure in the method for forming a semiconductor structure provided by an embodiment of the present application;

[0025] Figures 7B to 7F Schematic diagram of forming a word line structure in a word line trench in the method for forming a semiconductor structure provided by an embodiment of the present application.

[0026] Explanation of reference numerals is as follows:

[0027] 20 - Substrate; 30 - Insulating structure; 401 - Word line conductive layer 50 - Word line insulating layer; 120a - NC bottom surface; 110b - Top surface of word line structure; 130a - BCL bottom surface 100 - Substrate; 101 - Substrate; 102 - Barrier layer; 103 - First mask layer; 104 - First hard mask layer; 105 - Second hard mask layer; 106 - Photoresist layer; 107 - First isolation layer; 108 - Second isolation layer; 110 - Word line structure; 120 - NC; 130 - BLC; 201 - First substrate; 202 - Word line trench; 220 - Substrate; 222 - Photoresist layer; 223 - Mask pattern; 301 - First insulating layer; 302 - Second insulating layer; 303 - Third insulating layer; 304 - Fourth insulating layer; 1011 - Active region; 1012 Isolation layer; 1031 - Second mask layer; 1032 - Third mask layer; 1033 - Fourth mask layer; 1041 - Second hard mask pattern; 1051 - First hard mask pattern; 1101 - Word line metal layer; 1011 - Active region; 1102 - Word line adhesion layer; 1103 - Word line protection layer; 1104 - Word line insulating layer; 204 - Active region; 203 - Isolation region; 2021 - First trench; 2022 - Second trench; AT1 - First mask; AT2 - Second mask; 110a - Word line trench; 202a - Side wall of word line trench; 202b - Bottom of word line trench; 202c - Top of word line trench; 2021a - Bottom of first trench; 202d - Step surface; 40a - Surface of word line conductive layer. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will further describe the specific technical solutions of the present application in detail with reference to the accompanying drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application but are not intended to limit the scope of the present application.

[0029] In subsequent descriptions, the use of suffixes such as "module" or "unit" for representing elements is only for the convenience of description of the present application, and they have no specific meaning in themselves. Therefore, "module" or "unit" can be used interchangeably.

[0030] To better understand the technical solutions provided by the embodiments of the present application, the related technologies will be introduced first.

[0031] Reference Figure 1A In a semiconductor device (e.g., DRAM), the semiconductor structure includes a substrate 101, a word line structure 110, an NC 120, and a BLC 130. Among them, the word line structure 110 includes a word line metal layer 1101, a word line adhesion layer 1102, a word line protection layer 1103, and a word line insulation layer 1104.

[0032] Next, reference Figures 1A to 1N is made to describe the formation process of the semiconductor structure in the related art:

[0033] Reference Figure 1B is made. On the surface of the substrate 101, a barrier layer 102, a first mask layer 103, a first hard mask layer 104, a second hard mask layer 105, and a photoresist layer 106 are sequentially formed. The first mask layer 103 is used to form a mask layer for etching the substrate 101. The barrier layer 102 is used to protect the substrate 101 when etching the first mask layer 103, the first hard mask layer 104, and the second hard mask layer 105 subsequently. The photoresist layer 106 is used to form a pattern for etching the second hard mask layer 105. The photoresist layer 106 is exposed, developed, and sol-gelled, and the second hard mask layer 105 is etched to form Figure 1C the first hard mask structure 1051 as shown. Among them, the pattern of the first hard mask structure 1051 includes a plurality of parallel strip patterns, and this pattern exposes a part of the surface of the first hard mask layer 104.

[0034] Reference Figure 1D is made. A first isolation layer 107 is deposited and formed on the surface of the first hard mask structure 1051 and the part of the surface of the first hard mask layer 104 exposed by the first hard mask structure 1051. The first isolation layer 107 is etched back to form a first isolation structure (not shown in the figure). The etched-back first isolation structure is used to etch the first hard mask layer 104 to form Figure 1E the second hard mask structure 1041 as shown. The pattern of the second hard mask structure 1041 is also a plurality of parallel strip patterns, and this pattern exposes a part of the surface of the first mask layer 103.

[0035] Reference Figure 1F is made. A second isolation layer 108 is deposited on the surface of the second hard mask structure 1041 and the first mask layer 103. The second isolation layer 108 is etched back to form a second isolation structure (not shown in the figure). The second isolation structure is used as a mask layer to etch the first mask layer 103 to form Figure 1G the second mask layer 1031 as shown. The pattern (initial mask pattern) of the second mask layer 1031 also includes a plurality of parallel strip patterns. Among them, Figure 1D and Figure 1E the processes shown andFigure 1F and 1G The processes shown above all adopt the Self-aligned Double Patterning (SADP) technology.

[0036] Referring to Figures 1G to 1I , use the first mask AT1 including the first preset pattern to Figure 1G shear the initial mask pattern in the second mask layer 1031 shown above to form Figure 1H the third mask layer 1032 with the initial active pattern shown above. Use the second mask AT2 including the second preset pattern to shear the third mask layer 1032 with the initial active pattern to form Figure 1I the fourth mask layer 1033 with the active region pattern shown above. Among them, the active region pattern is the pattern of the finally formed active region.

[0037] Referring to Figure 1J , use the fourth mask layer 1033 to etch the substrate 101 and the barrier layer 102 to form the active region 1011 shown in Figure 1K . Deposit SiO2 as the isolation layer 1012 between adjacent active regions 1011 and on the surface of the active region 1011 to isolate two adjacent active regions 1011. Among them, the active region 1011 is used to form active devices such as transistors.

[0038] Referring to Figure 1L , continue to etch part of the active region 1011 and the isolation region 1012 by using photoresist (PR) and the mask layer 1034 to form the substrate 101 including the word line trench 110a shown in Figure 1M . Referring to Figure 1N , form the word line structure 110 in the word line trench 110a, and the word line structure 110 is used to control the on or off of the active device.

[0039] Next, form other structures such as NC 120 and BLC 130 for forming the semiconductor structure, and finally form the semiconductor structure shown in Figure 1A .

[0040] NC 120 is used to electrically connect the source / drain region and other parts in the semiconductor structure. BLC 130 is used to electrically connect the active region and the bit line structure. The material of NC 120 can be a silicon-containing conductive material and has a low resistance, such as one or more of amorphous silicon or polysilicon. The material of BLC 130 can be a silicon-containing conductive material. For example, the material of BLC 130 can be the same as the material of NC 120.

[0041] Theoretically speaking, when designing the semiconductor structure, referring toFigure 1A , the bottom surface 120a of the NC 120 or the bottom surface 130a of the BLC 130 and the top surface 110b of the word line structure 110 should be on the same horizontal plane. However, in the actual fabrication of the semiconductor structure, due to the influence of process precision and the like, it is impossible to make the bottom surface 120a of the NC 120 or the bottom surface 130a of the BLC 130 and the upper surface 110b of the word line structure 110 exactly on the same horizontal plane. At this time, the overlapping part of the side wall of the NC 120 or the side wall of the BLC 130 and the side wall of the word line structure 110 in the vertical direction is called the overlap region (refer to Figure 1A the dotted box shown in), and the strong electric field generated in the overlap region will cause leakage or generate an overlap capacitance. In other words, in the semiconductor structure of the DRAM, the active region is used to form transistors, and the word line structure 110 is used to control the opening / closing of the transistors. A relatively large gate-induced drain leakage current (GIDL) will be generated in the gate-drain overlap region between the word line structure 110 and the drain region in the transistors.

[0042] To solve the above problems, refer to Figure 2A , an embodiment of the present application provides a method for forming a semiconductor structure, including:

[0043] S10. Provide a substrate; wherein, the substrate includes word line trenches with stepped side walls; the width of the top of the word line trenches is greater than the width of the bottom of the word line trenches;

[0044] Here, the substrate can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, and can also include multiple layers, such as a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0045] Word line trenches can be formed in the substrate; wherein, the word line trenches are used to form word line structures, so as to control the conduction or cut-off of active devices in the substrate.

[0046] The side walls of the word line trenches can be stepped, wherein, at least one step can be included on the side walls, for example, it can be one, or at least two. The embodiment of the present application does not limit the number of steps.

[0047] Taking the example of a step included on the sidewall, the stepped word line trench can be formed through two etching processes. For example, the trench above the step surface (which can be understood as the first trench) can be formed through one etching process first, and then the bottom of the first trench can be etched through another etching process to form the trench below the step surface (which can be understood as the second trench). It should be noted that the above is for convenience of description, taking the example of a step included on the sidewall. Those skilled in the art can obtain at least two steps on the sidewall according to this formation process.

[0048] S20. Form an insulating structure on the sidewall and bottom of the word line trench;

[0049] Here, the insulating structure covers the surface of the word line trench. The insulating structure can include at least one insulating layer, for example, it can be one layer or at least two layers. The material of the insulating structure can be silicon dioxide, silicon oxycarbide, etc.

[0050] In some embodiments, the insulating structure can be formed through a deposition process. The deposition process includes any one of the following: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and any other suitable deposition process.

[0051] S30. Form a word line structure in the word line trench formed with the insulating structure.

[0052] In some embodiments, the word line structure can at least include a word line conductive layer. The material of the word line conductive layer can include metal and polysilicon. Among them, the metal materials can include but are not limited to any combination of the above conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. Polysilicon generally covers the top surface of the metal to inhibit oxygen from entering the word line metal layer where the metal is located and improve the conductivity of the word line conductive layer.

[0053] In some embodiments, a word line adhesion layer can also be formed between the word line metal layer and the insulating structure. The word line adhesion layer covers the surface of the word line metal layer except the top surface. The word line adhesion layer is used to improve the adhesion ability between the word line metal layer and the insulating structure. The material of the word line adhesion layer can be titanium nitride.

[0054] In an embodiment of the present application, the sidewalls of the word line groove are arranged to be stepped, and the width of the top of the word line groove is greater than the width of the bottom of the word line groove. Then, an insulating structure is formed on the sidewalls and the bottom of the word line groove. By changing the shape of the word line groove, the leakage or overlap capacitance generated in the overlap area in the related art is reduced through the insulating structure in the word line groove.

[0055] Figures 2B to 2D The schematic diagram of the semiconductor structure forming process provided in the embodiment of the present application is as follows. Figures 2B to 2D The above steps S10 to S30 are further explained.

[0056] refer to Figure 2B The base 20 includes a first substrate 201, a plurality of active regions 204 located on the first substrate 201, and an isolation region 203 for isolating adjacent active regions 204. The plurality of active regions 204 are strip-shaped structures extending along the second direction x.

[0057] The first substrate 201 may be a silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing a selective epitaxial growth process.

[0058] The isolation region 203 may be formed by forming a groove in the substrate 20 and then filling the groove with an isolation material. The material of the isolation region 203 may include silicon nitride or silicon oxide. The substrate 20 also includes a word line groove 202 with a stepped sidewall, and the sidewall includes a step. The word line groove 202 runs through the active region 204 and the isolation region 203, and the word line groove 202 extends along the third direction y, and a plurality of word line grooves 202 are parallel to each other. The width of the top 202c of the word line groove 202 is greater than the width of the bottom 202b of the word line groove 202.

[0059] Figure 2B Cut along DD Figure 2C Structure, reference Figure 2C , an insulating structure 30 is deposited on the sidewall 202a and the bottom 202b of the word line trench 202; after forming the insulating structure 30, a reference Figure 2D The word line structure 40 is shown surrounded by the insulating structure 30 .

[0060] Generally speaking, the substrate 20 may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the first direction. In the direction of the top surface and the bottom surface of the substrate (i.e., the plane where the substrate is located), two second directions and third directions intersecting each other (for example, perpendicular to each other) are defined. For example, the extending direction of the word line trench may be defined as the first direction, and based on the second direction and the third direction, the plane direction of the substrate can be determined. The first direction is perpendicular to the second direction and the third direction respectively. In the embodiments of the present application, the second direction is defined as the x-axis direction, and the third direction is defined as the y-axis direction. The embodiments of the present application do not limit the angle between the second direction x and the third direction y.

[0061] In some embodiments, the implementation of step S20 includes:

[0062] Step S201: Conformally form an insulating structure on the sidewalls and the bottom of the word line trench, wherein the thickness of the insulating structure at the top of the sidewalls is greater than the thickness of the insulating structure at the bottom of the sidewalls.

[0063] Here, conformally forming an insulating structure on the sidewalls and the bottom of the word line trench means that the insulating structure has the same shape as the word line trench. For example, based on the shape of the word line trench, an insulating structure is formed in the word line trench through processes such as deposition, so that the shape of the surface of the insulating structure close to the word line trench is the same as the shapes of the sidewalls and the bottom of the word line trench.

[0064] In the embodiments of the present application, since the width of the top of the word line trench is greater than the width of the bottom of the word line trench, and the insulating structure is conformal to the sidewalls and the bottom of the word line trench, therefore, by controlling the thickness of the insulating structure, the thickness of the insulating structure at the top of the sidewalls of the word line trench can be made greater than the thickness of the insulating structure at the bottom of the sidewalls of the word line trench. Simply put, the insulating structure provided by the embodiments of the present application has a structure that is thicker at the top and thinner at the bottom. When the insulating structure is a gate oxide layer, the gate oxide layer also has a structure that is thicker at the top and thinner at the bottom, that is, the thickness of the gate oxide layer at the top of the sidewalls of the word line trench is greater than the thickness of the gate oxide layer at the bottom of the sidewalls of the word line trench.

[0065] Since the insulating effect of the insulating layer in the insulating structure corresponding to the thicker part is better than that of the insulating layer in the insulating structure corresponding to the thinner part, the capacitance between the word line structure and other structures can be effectively reduced. When the above semiconductor structure is used to form a DRAM, at this time, since the part of the word line structure located in the active region is also used as the gate of the transistor, the above semiconductor structure can improve the switching speed of the transistor and reduce the phenomenon of transistor leakage.

[0066] The above step S201 can be referred to Figure 2C for understanding.

[0067] Reference Figure 2C , the sidewall 202a and the bottom 202b of the word line trench 202 are conformal to the insulating structure 30. Since the width of the top 202c of the word line trench 202 is greater than the width of the bottom 202b of the word line trench 202, it is possible to achieve that Figure 2C the thickness of the insulating structure 30 at the top of the sidewall 202a is greater than the thickness of the insulating structure 30 at the bottom of the sidewall 202a as shown in

[0068] Next, referring to Figure 2C , in some embodiments, the insulating structure 30 may include a first insulating layer 301 and a second insulating layer 302, where:

[0069] The first insulating layer 301 covers at least the sidewall of the word line trench 202 above the step surface 202d;

[0070] The second insulating layer 302 covers the surface of the first insulating layer 301 and the surface of the word line trench 202 not covered by the first insulating layer 301.

[0071] Here, the surface of the word line trench 202 includes the sidewall 202a and the bottom surface 202b of the word line trench 202.

[0072] In some embodiments, referring to Figure 2C , Figure 2E and Figure 2F , the sidewall 202a of the word line trench 202 can be divided into upper and lower parts with the step surface 202d as the boundary. The first insulating layer 301 covers at least the sidewall of the word line trench 202 above the step surface, including:

[0073] Case 1, referring to Figure 2C , the first insulating layer 301 covers the sidewall 202a of the word line trench 202 above the step surface 202d. In other words, the first insulating layer 301 covers the upper half of the sidewall 202a; while the first insulating layer 301 does not cover the sidewall 202a of the word line trench 202 below the step surface 202d and the bottom wall 202b of the word line trench 202. In other words, the first insulating layer 301 does not cover the lower half of the sidewall 202a.

[0074] Case 2, referring to Figure 2E , the first insulating layer 301 covers the entire sidewall 202a of the word line trench 202, that is, the first insulating layer 301 covers the sidewall 202a of the word line trench 202 above the step surface 202d and the sidewall 202a of the word line trench 202 below the step surface 202d. In other words, the first insulating layer 301 does not cover the bottom wall 202b of the word line trench 202.

[0075] Case 3, referring to Figure 2F, the first insulating layer 301 covers the entire sidewall 202a and bottom wall 202b of the word line trench 202, that is, the first insulating layer 301 covers the sidewall 202a above the step surface 202d in the word line trench 202, the sidewall 202a below the step surface 202d, and the bottom wall 202b of the word line trench 202. In other words, the first insulating layer 301 covers the entire surface of the word line trench 202.

[0076] It should be noted that the area of the first insulating layer 301 covering the surface of the word line trench 202 is not limited in the embodiments of the present application.

[0077] Here, the materials of the first insulating layer and the second insulating layer may be different. Correspondingly, the dielectric constants of the first insulating layer and the second insulating layer are also different. For example, the material of the first insulating layer may be silicon carbon oxide (SiCO), and the material of the second insulating layer may be silicon oxide (SiO2). The dielectric constant of silicon carbon oxide (k1 = 4.1) is greater than the dielectric constant of silicon oxide (k2 = 3.9).

[0078] In some embodiments, two insulating layers with different materials may be deposited in the word line trench, namely the first insulating layer and the second insulating layer. In other embodiments, an insulating layer of one material may be deposited in the word line trench, and then the surface of the oxide layer is oxidized. Among them, the unoxidized part is the first insulating layer, and the oxidized part is the second insulating layer.

[0079] In this case, due to the different dielectric constants corresponding to the materials of the first insulating layer and the second insulating layer, the insulating layer with a higher dielectric constant can be equivalent to a thicker insulating layer with a lower dielectric constant, so that the insulating structure has a better insulating effect, thereby effectively reducing the capacitance between the word line structure and other structures. When the above semiconductor structure is used to form a DRAM, at this time, since the part of the word line structure located in the active region is also used as the gate of the transistor, the above semiconductor structure can improve the switching speed of the transistor and reduce the phenomenon of transistor leakage.

[0080] In some embodiments, referring to Figure 2C and Figure 2F , the thickness of the first insulating layer 301 is greater than the thickness of the second insulating layer 302.

[0081] In practical applications, the material of the insulating structure 30 may be SiCO. After the insulating structure 30 is oxidized, the unoxidized SiCO is the first insulating layer 301, and the oxidized SiCO is the second insulating layer 302.

[0082] When the insulating structure is oxidized, since the oxide layer is very thin, the thickness of the first insulating layer is greater than that of the second insulating layer, thereby realizing two insulating layers of different materials, improving the insulation effect of the insulating structure, and reducing the capacitance between the word line structure and other structures.

[0083] The embodiment of the present application further provides a method for forming a semiconductor structure. Refer to Figure 3A , the method includes:

[0084] S301. Provide a substrate; wherein, the substrate includes a word line trench with a stepped sidewall; the width of the top of the word line trench is greater than the width of the bottom of the word line trench;

[0085] Here, step S301 is the same as step S10, and can be understood with reference to step S10.

[0086] S302. Form a third insulating layer at least on the sidewall above the step surface in the word line trench;

[0087] Here, the material of the third insulating layer can be SiCO, and the third insulating layer can be formed by deposition.

[0088] S303. At least oxidize the surface of the third insulating layer to form a second insulating layer; wherein, the unoxidized part of the third insulating layer forms the first insulating layer.

[0089] Here, the surface of the third insulating layer refers to the surface of the third insulating layer that does not contact the word line trench. The method of oxidizing the third insulating layer can include any one of the following: dry oxygen oxidation, wet oxygen oxidation, water vapor oxidation, and any other suitable oxidation process.

[0090] In some embodiments, the implementation of step S303 includes:

[0091] The first case: When the third insulating layer covers the sidewall above the step surface in the word line trench and does not completely cover the surface of the word line trench, oxidize the surface of the word line trench not covered by the third insulating layer and the surface of the third insulating layer to form a second insulating layer; the unoxidized part of the third insulating layer forms the first insulating layer.

[0092] The second case: When the third insulating layer covers the entire sidewall of the word line trench and does not completely cover the surface of the word line trench, oxidize the surface of the word line trench not covered by the third insulating layer and the surface of the third insulating layer to form a second insulating layer; the unoxidized part of the third insulating layer forms the first insulating layer.

[0093] The third case: when the third insulating layer completely covers the surface of the word line trench, oxidize the surface of the third insulating layer to form a second insulating layer. The unoxidized part of the third insulating layer forms the first insulating layer.

[0094] S304. Form a word line structure in the word line trench where the insulating structure is formed.

[0095] Here, step S304 is the same as step S30, and can be understood with reference to step S30.

[0096] In the embodiments of the present application, through the oxidation method, two insulating layers of different materials are realized, thereby improving the insulation effect of the insulating structure and reducing the capacitance between the word line structure and other structures.

[0097] Next, refer to Figure 3B and Figure 3D to describe steps S302 and S303.

[0098] Refer to Figure 3B , for the case where the third insulating layer 303 is formed on the sidewall above the step surface in the word line trench 202 and does not completely cover the surface of the word line trench 202, the surface of the third insulating layer 303 refers to the surface of the third insulating layer 303 that does not contact the word line trench 202. When oxidizing the third insulating layer 303, the oxidation gas first contacts the uncovered part of the surface of the word line trench 202 that is not covered by the third insulating layer 303 and the surface of the third insulating layer 303, and then first oxidizes the uncovered surface of the word line trench 202 that is not covered by the third insulating layer and the surface of the third insulating layer 303 to form Figure 2C the second insulating layer 302 shown, and the unoxidized third insulating layer 303 forms Figure 2C the first insulating layer 301 shown.

[0099] Refer to Figure 3C , for the case where the third insulating layer 303 covers the entire sidewall 202a of the word line trench 202 and does not completely cover the surface of the word line trench 202 (does not cover the bottom wall 202b of the word line trench 202), similarly, during the oxidation treatment, the oxidation gas first contacts the surface of the third insulating layer 303 and the bottom wall 202b of the word line trench 202, and then oxidizes the surface of the third insulating layer 303 and the bottom wall 202b of the word line trench 202 to form Figure 2E the second insulating layer 302 shown, and the unoxidized third insulating layer 303 forms Figure 2E the first insulating layer 301 shown.

[0100] Refer to Figure 3D, for the case where the third insulating layer 303 completely covers the surface of the word line trench 202, that is, the third insulating layer 303 covers the sidewall 202a and the bottom 202b of the word line trench 202. Similarly, during the oxidation treatment, the oxidation gas first contacts the surface of the third insulating layer 303, and then oxidizes the surface of the third insulating layer 303 to form Figure 2F the second insulating layer 302 shown, and the unoxidized third insulating layer 303 forms Figure 2F the first insulating layer 301 shown.

[0101] In some embodiments, referring to Figure 4A , the word line trench 202 includes a first trench 2021 and a second trench 2022 stacked along the depth direction of the word line trench 202; wherein, the width w2 of the first trench 2021 is greater than the width w1 of the second trench 2022, and the interface between the first trench 2021 and the second trench 2022 is the step surface 202d in the word line trench 202;

[0102] Here, the stacked arrangement of the first trench 2021 and the second trench 2022 means that the depth of the first trench 2021 is d2, the depth of the second trench 2022 is d1, and the depth of the word line trench 202 is d3, and d3 = d1 + d2, that is, the bottom surface of the first trench 2021 is the top surface of the second trench 2022.

[0103] In some embodiments, the depth d2 of the first trench 2021 is 1 / 3 of the depth d3 of the word line trench 202. In this way, when depositing an insulating structure in the word line trench, the length of the thicker insulating layer in the insulating structure corresponding to the first trench can be made long enough, which is convenient for improving the insulation effect of the insulating layer overlapping with the word line conductive layer after the word line conductive layer is subsequently provided.

[0104] In this case, S302 "forming a third insulating layer at least on the sidewall above the step surface in the word line trench" includes:

[0105] S302a: forming the third insulating layer on the sidewall of the first trench.

[0106] Next, referring to Figure 4A , step S302a will be described.

[0107] Referring to Figure 4A , a third insulating layer 303 is formed on the sidewall of the first trench 2021. Among them, the thickness of the third insulating layer 303 can be equal to half of the difference between the width of the first trench and the width of the second trench. After the surface of the third insulating layer 303 and the surface of the word line trench 202 not covered by the third insulating layer 303 are oxidized, the formation is as shown in Figure 2CThe insulating structure 30 shown. Among them, the unoxidized part of the third insulating layer forms the first insulating layer 301 in the insulating structure 30; the oxidized parts of the surface of the third insulating layer 303 and the surface of the word line trench 202 not covered by the third insulating layer 303 form the second insulating layer 302 in the insulating structure 30. The first insulating layer 301 covers the sidewalls of the first trench 2021; the second insulating layer 302 covers the first insulating layer 301 and covers the surface of the second trench 2022.

[0108] In some embodiments, the "providing a substrate" in step S10 includes Figure 4B the following steps shown:

[0109] S101. Provide a substrate.

[0110] S102. Etch the substrate to form the first trench.

[0111] Here, a dry etching technique or a wet etching technique can be used, such as reactive ion etching technique, plasma etching technique, to etch the substrate.

[0112] Correspondingly, the "forming the third insulating layer on the sidewalls of the first trench" in S302a includes:

[0113] Step S321: Form a fourth insulating layer in the first trench and on the substrate;

[0114] Here, the fourth insulating layer is formed by a deposition process, and the deposition process includes any one of the following: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and any other suitable deposition process.

[0115] Exemplarily, since the thickness of the deposition layer formed by ALD is extremely uniform and the consistency is extremely excellent, ALD is used to deposit the fourth insulating structure. The material of the fourth insulating layer can be a material with a relatively large dielectric constant, for example: silicon carbon oxide (SiCO), the dielectric constant k1 of silicon carbon oxide is 4.1, at this time, the thickness of the silicon carbon oxide deposited by ALD is about 3 to 8 nanometers (nm).

[0116] Step S322: Remove the fourth insulating layer on the substrate and at the bottom of the first trench, and retain the fourth insulating layer on the sidewalls of the first trench to form the third insulating layer;

[0117] In some embodiments, the fourth insulating layer on the substrate and at the bottom of the first trench is removed by a dry etching process, and the fourth insulating layer on the sidewall of the first trench is retained to form a third insulating layer.

[0118] S103 , etching the bottom of the first trench to form the second trench.

[0119] Reference below Figures 4A to 4F , the above steps S101 to S103 are explained.

[0120] refer to Figure 4C The substrate 220 includes a first substrate 201 and active regions 204 and isolation regions 203 located on the first substrate 201 . The plurality of active regions 204 are separated from each other, and the isolation regions 203 are formed by filling gaps between the active regions 204 .

[0121] The configuration of the substrate 220 may refer to the configuration of the above-mentioned base 20 (excluding the structure of the word line trench 202 ).

[0122] refer to Figure 4D ,for Figure 4C The schematic diagram of the three-dimensional structure obtained by cutting along EE is shown below for a clearer explanation. Figure 4D For explanation purposes only.

[0123] refer to Figure 4E , etching the substrate 220 to form a first trench 2021.

[0124] Figure 4F for Figure 4E A schematic diagram of the corresponding structure including a complete first groove obtained by cutting along FF.

[0125] The height of the first groove 2021 is d2.

[0126] Continue etching the bottom 2021a of the first trench 2021 to form Figure 4A The second groove 2022 is shown.

[0127] Reference below Figures 4G to 4J , the above steps S321 to S322 are explained.

[0128] refer to Figure 4G , a fourth insulating layer 304 is formed in the first trench 2021 and on the substrate 220 .

[0129] Figure 4H for Figure 4G The corresponding schematic diagram of the structure including the complete first groove obtained by cutting along AA. Figure 4H, the fourth insulating layer 304 on the substrate 220 and at the bottom 2021a of the first trench 2021 is removed, while the fourth insulating layer 304 on the sidewall 202a of the first trench 2021 is retained, forming Figure 4I and Figure 4J the third insulating layer 303 shown in

[0130] In some embodiments, step S102, "etching the substrate to form the first trench", includes Figure 5A the following steps shown in

[0131] Step S121: Form a photoresist layer on the substrate;

[0132] Here, photoresist, also known as photoresistive agent, refers to a corrosion-resistant thin film material whose solubility changes upon irradiation or radiation by ultraviolet light, electron beam, ion beam, X-ray, etc. Photoresist is light-sensitive and includes components such as photosensitive resin, sensitizer, and solvent. During the photolithography process, it is used as an anti-corrosion coating material.

[0133] Step S122: Pattern the photoresist layer to form a mask pattern;

[0134] Here, patterning the photoresist layer means exposing and developing the photoresist layer, dissolving part of the photoresist layer, and the undissolved part of the photoresist layer forms a mask pattern. The first window in the mask pattern is a hollow pattern.

[0135] Step S123: Use the mask pattern as a mask to etch the substrate to form the first trench.

[0136] The following refers to Figures 5B to 5C to illustrate the above steps S121 to S123.

[0137] Referring to Figure 5B , a photoresist layer 222 is formed on the substrate 220.

[0138] Referring to Figure 5C , the photoresist layer 222 is patterned. The photoresist layer 222 is exposed and developed, and part of the photoresist layer 222 is dissolved. The undissolved part of the photoresist layer 222 forms a mask pattern 223. The mask pattern 223 includes a first window 223a. The first window 223a is a hollow pattern, and the first window 223a corresponds to the first trench 2021.

[0139] Using the mask pattern 223 as a mask layer, the surface of the substrate 220 exposed by the first window 223a is etched to form Figure 4E the first trench 2021 shown in

[0140] In some embodiments, step S103, "etching the bottom of the first trench to form the second trench", includes:

[0141] Step S131: Using the third insulating layer as a mask, etching the bottom of the first trench to form the second trench.

[0142] The following refers to Figure 4I and Figure 6 to illustrate the above step S131.

[0143] Figure 4I FIG. is a schematic diagram for forming the third insulator 303 on the sidewall of the first trench 2021. Among them, the surface of the etched substrate 220 is exposed at the bottom 2021a of the first trench 2021. Using the third insulating layer 303 as a mask, etching the bottom 2021a of the first trench 2021 to form Figure 6 the second trench 2022 shown.

[0144] In this case, since the second trench 2022 is formed by etching the surface of the substrate 220 exposed by the first trench 2021, the width w2 of the first trench is greater than the width w1 of the second trench 2022.

[0145] In some embodiments, the word line structure includes a word line conductive layer and a word line insulating layer. Step S30, "forming a word line structure in the word line trench formed with the insulating structure", includes Figure 7A the following steps shown:

[0146] Step S301: Forming a word line conductive layer in the word line trench formed with the insulating structure;

[0147] Here, by depositing to form a word line conductive layer in the word line trench formed with the insulating structure, the material of the word line conductive layer may include metal and polysilicon, and the metal materials may include, but are not limited to, any combination of the above conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc.

[0148] Step S302: Forming a word line insulating layer on the word line conductive layer in the word line trench; the interface between the word line conductive layer and the word line insulating layer is higher than the step surface of the word line trench.

[0149] Here, the word line insulating layer may include: for example, silicon oxide, silicon carbon oxide or silicon nitride oxide. The method of forming the word line insulating layer may be LPCVD.

[0150] The following refers to Figures 7B to 7F to illustrate the above step S301 and step S302.

[0151] Refer to Figure 7B, a word line conductive layer 401 is deposited in the word line trench 202 formed with the insulating structure 30. The word line conductive layer 401 fills the first trench 2021 and the second trench 2022, and the surface of the word line conductive layer 401 is flush with the upper surface of the substrate 220.

[0152] Figure 7C For Figure 7B The corresponding structural schematic diagram including the complete first trench obtained by sectioning along B-B.

[0153] Reference Figure 7D , etch the word line conductive layer 401 so that the surface 40a of the etched word line conductive layer 401 is higher than the step surface 202d of the word line trench 202.

[0154] Then, fill and form on the word line conductive layer 401 in the word line trench 202 Figure 7E And Figure 7F The word line insulating layer 50 shown; at this time, referring to Figure 7F , the interface 40a between the word line conductive layer 401 and the word line insulating layer 50 is higher than the step surface 202d of the word line trench 202.

[0155] In the embodiment of the present application, by setting the interface between the word line conductive layer and the word line insulating layer in the word line structure to be higher than the step surface of the word line trench, and the insulating structure in the overlap region between the word line conductive layer and the NC or BLC includes two insulating layers with different dielectric constants, and the two insulating layers with different dielectric constants are equivalent to a thicker insulating layer with a lower dielectric constant, which can effectively reduce the capacitance between the word line structure and other structures. When the above semiconductor structure is used to form a DRAM, at this time, since the part of the word line structure located in the active region is also used as the gate of the transistor, the above semiconductor structure can improve the switching speed of the transistor and reduce the phenomenon of transistor leakage.

[0156] The embodiment of the present application also provides a method for forming a semiconductor structure, including:

[0157] S401, provide Figure 4C The substrate 220 shown;

[0158] S402: Refer to Figure 5B , form a photoresist layer 222 on the substrate 220;

[0159] S403: Pattern the photoresist layer 222 to form Figure 5C The mask pattern 223 shown;

[0160] S404: Use the mask pattern 223 as a mask to etch the substrate 220 to form Figure 4E And Figure 4F The first trench 2021 shown in;

[0161] S405: Refer to Figure 4G , form a fourth insulating layer 304 in the first trench 2021 and on the substrate 220;

[0162] S406: Refer to Figure 4H , remove the fourth insulating layer 304 on the substrate 220 and at the bottom 2021a of the first trench 2021, and retain the fourth insulating layer 304 on the sidewall 202a of the first trench 2021 to form Figure 4I the third insulating layer 303 as shown;

[0163] S407: Using the third insulating layer 303 as a mask, etch the bottom 2021a of the first trench 2021 to form Figure 6 the second trench 2022 as shown;

[0164] S408: Refer to Figure 3B , oxidize the surface of the third insulating layer 303 to form Figure 2C the second insulating layer 302 as shown; wherein, the unoxidized part of the third insulating layer 303 forms the first insulating layer 301;

[0165] S409: Refer to Figure 7B , form a word line conductive layer 401 in the word line trench 202 where the insulating structure 30 is formed;

[0166] S410: Refer to Figure 7D , etch the word line conductive layer 401 such that the surface 40a of the etched word line conductive layer 401 is higher than the step surface 202d of the word line trench 202;

[0167] S410: Refer to Figure 7E and Figure 7F , form a word line insulating layer 50 on the word line conductive layer 401 in the word line trench 202; the interface between the word line conductive layer 401 and the word line insulating layer 50 is higher than the step surface 202d of the word line trench 202.

[0168] The features disclosed in several method or structural embodiments provided by this application can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0169] The description of the above semiconductor structure embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the semiconductor structure embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0170] As described above, it is only an exemplary embodiment of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; wherein, the substrate includes word line trenches with stepped sidewalls; the width of the top of the word line trenches is greater than the width of the bottom of the word line trenches; Conformally forming an insulating structure on the sidewalls and bottom of the word line trenches, wherein the thickness of the insulating structure at the top of the sidewalls is greater than the thickness of the insulating structure at the bottom of the sidewalls; Forming a word line structure in the word line trenches formed with the insulating structure.

2. The method according to claim 1, wherein The insulating structure includes a first insulating layer and a second insulating layer, wherein: The first insulating layer at least covers the sidewalls above the stepped surfaces in the word line trenches; The second insulating layer covers the surface of the first insulating layer and the surfaces of the word line trenches not covered by the first insulating layer.

3. The method according to claim 2, wherein Wherein, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

4. The method according to claim 2, characterized in that, The conformally forming an insulating structure on the sidewalls and bottom of the word line trenches includes: Forming a third insulating layer at least on the sidewalls above the stepped surfaces in the word line trenches; At least oxidizing the surface of the third insulating layer to form a second insulating layer; wherein, the unoxidized part of the third insulating layer forms the first insulating layer.

5. The method according to claim 4, wherein The at least oxidizing the surface of the third insulating layer to form the second insulating layer includes: In the case where the third insulating layer covers the sidewalls above the stepped surfaces in the word line trenches and does not completely cover the surfaces of the word line trenches, oxidizing the surfaces of the word line trenches not covered by the third insulating layer and the surface of the third insulating layer to form a second insulating layer; In the case where the third insulating layer completely covers the surfaces of the word line trenches, oxidizing the surface of the third insulating layer to form a second insulating layer.

6. The method according to claim 4, characterized in that The word line trenches include a first trench and a second trench stacked along the depth direction of the word line trenches; wherein, the width of the first trench is greater than the width of the second trench, and the interface between the first trench and the second trench is the stepped surface in the word line trenches; The forming a third insulating layer at least on the sidewalls above the stepped surfaces in the word line trenches includes: Forming the third insulating layer on the sidewalls of the first trench.

7. The method according to claim 6, characterized in that, The providing a substrate includes: Providing a substrate; etching the substrate to form the first trench; Correspondingly, the forming the third insulating layer on the sidewalls of the first trench includes: forming a fourth insulating layer in the first trench and on the substrate, removing the fourth insulating layer on the substrate and at the bottom of the first trench, and retaining the fourth insulating layer on the sidewalls of the first trench to form the third insulating layer; The providing a substrate further includes: Etching the bottom of the first trench to form the second trench.

8. The method according to claim 7, characterized in that, The etching the substrate to form the first trench includes: Forming a photoresist layer on the substrate; Patterning the photoresist layer to form a mask pattern; Etching the substrate using the mask pattern as a mask to form the first trench.

9. The method according to claim 7, characterized in that, The etching the bottom of the first trench to form the second trench includes: Etching the bottom of the first trench using the third insulating layer as a mask to form the second trench.

10. The method according to claim 7, wherein Form a fourth insulating layer on the surface of the first trench and the substrate, including: Use atomic layer deposition to form the fourth insulating layer on the surface of the first trench and the substrate.

11. The method according to any one of claims 1 to 10, characterized in that, The word line structure includes a word line conductive layer and a word line insulating layer. Forming the word line structure in the word line trench formed with the insulating structure includes: Form a word line conductive layer in the word line trench formed with the insulating structure; Form a word line insulating layer on the word line conductive layer in the word line trench; the interface between the word line conductive layer and the word line insulating layer is higher than the step surface of the word line trench.

12. The method according to any one of claims 6 to 10, characterized in that, The depth of the first trench is 1 / 3 of the depth of the word line trench.

13. A semiconductor structure, characterized in that, Including: Substrate; The substrate includes word line trenches with stepped sidewalls; The width of the top of the word line trench is greater than the width of the bottom of the word line trench; An insulating structure located on the sidewalls and bottom of the word line trench and a word line structure surrounded by the insulating structure, and the thickness of the insulating structure at the top of the sidewall is greater than the thickness of the insulating structure at the bottom of the sidewall.

14. The semiconductor structure according to claim 13, wherein The insulating structure includes a first insulating layer and a second insulating layer, where: The first insulating layer covers at least the sidewalls above the step surface in the word line trench; The second insulating layer covers the surface of the first insulating layer and the surface of the word line trench not covered by the first insulating layer.

15. The semiconductor structure according to claim 14, wherein, The thickness of the first insulating layer is greater than the thickness of the second insulating layer.

16. The semiconductor structure according to claim 14 or 15, characterized in that, The word line trench includes a first trench and a second trench stacked along the depth direction of the word line trench; wherein, the width of the first trench is greater than the width of the second trench, and the interface between the first trench and the second trench is the step surface in the word line trench; The first insulating layer covers the sidewalls of the first trench; the second insulating layer covers the first insulating layer and covers the surface of the second trench.

17. The semiconductor structure according to claim 16, wherein, The depth of the first trench is 1 / 3 of the depth of the word line trench.

18. The semiconductor structure according to any one of claims 13 to 15, characterized in that The word line structure includes a word line conductive layer and a word line insulating layer.

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