Semiconductor Structure and Method for Preparing the Same

Abstract

The present application discloses a semiconductor structure and a method for preparing the same, belonging to the field of semiconductor technology. Among them, the method for preparing the semiconductor structure includes: providing a substrate; forming a trench in the substrate; forming a bit line in the trench; filling the trench by using an epitaxial growth process and depositing on the surface of the substrate to form a first active region, the first active region covering the bit line; patterning and etching the first active region to form a columnar conductive channel; and forming a gate around the conductive channel. In the semiconductor structure prepared by this method, the first source region can surround the bit line, increasing the contact area between the first active region and the bit line, reducing the contact resistance between the first active region and the bit line, thereby improving the charge transfer speed and ensuring the signal transmission performance.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a bit line structure and a method for manufacturing the same, as well as a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. The main principle of operation is to use the amount of charge stored in a capacitor to represent whether a binary bit (bit) is 1 or 0.

[0003] Recently, in the semiconductor industry, in order to improve the integration level, DRAMs below 40 nm are being developed. However, for currently developed DRAMs below 40 nm, there is a problem that as the integration level increases, the signal transmission performance deteriorates. Summary of the Invention

[0004] The purpose of this application is to provide a bit line structure and a method for manufacturing the same, as well as a semiconductor structure and a method for manufacturing the same, to solve the problem of poor signal transmission performance in high-integration DRAMs in the prior art.

[0005] According to the first aspect of the embodiments of this application, a method for manufacturing a semiconductor structure is provided. The method may include:

[0006] Providing a substrate, on which an insulating layer with a crisscross pattern is formed;

[0007] Forming a trench in the substrate, the trench penetrating the insulating layer;

[0008] Forming a bit line in the trench;

[0009] Using an epitaxial growth process to fill the trench and depositing on the surface of the substrate to form a first active region, the first active region covering the bit line;

[0010] Pattern-etching the first active region to form a columnar conductive channel;

[0011] Forming a gate around the conductive channel.

[0012] In some alternative embodiments of this application, forming a trench in the substrate may specifically be:

[0013] Using a dry etching process to form a trench in the substrate.

[0014] In some alternative embodiments of this application, forming a bit line in the trench may include:

[0015] Using a deposition process to sequentially deposit a bit line metal layer and a first sacrificial layer in the trench to obtain a first filling structure that fills the trench;

[0016] Etch away the region of the first filling structure close to the sidewall of the trench, so as to leave a gap between the first filling structure and the sidewall of the trench;

[0017] Etch away the first sacrificial layer to obtain the bit line.

[0018] In some alternative embodiments of the present application, the bit line metal layer includes a stacked first barrier layer, a metal layer, and a second barrier layer;

[0019] Use a deposition process to sequentially deposit the bit line metal layer and the first sacrificial layer in the trench to obtain a first filling structure that fills the trench. Specifically, it can be:

[0020] Use a deposition process to sequentially deposit the first barrier layer, the bit line metal, the second barrier layer, and the first sacrificial layer inside the trench to obtain a first filling structure that fills the trench.

[0021] In some alternative embodiments of the present application, before using a deposition process to sequentially deposit the bit line metal layer and the first sacrificial layer in the trench to obtain a first filling structure that fills the trench, forming a bit line in the trench may further include:

[0022] Deposit and form a second sacrificial layer in the trench;

[0023] After etching away the region of the first filling structure close to the sidewall of the trench so as to leave a gap between the first filling structure and the sidewall of the trench, the method for preparing the semiconductor structure further includes:

[0024] Etch away a part of the second sacrificial layer, and the remaining part of the second sacrificial layer is used to support the bit line metal layer.

[0025] In some alternative embodiments of the present application, etching away a part of the second sacrificial layer may specifically be:

[0026] Use wet etching to etch away a part of the second sacrificial layer.

[0027] In some alternative embodiments of the present application, etching away the region of the first filling structure close to the sidewall of the trench so as to leave a gap between the first filling structure and the sidewall of the trench may specifically be:

[0028] Use dry etching to etch away the region of the first filling structure close to the sidewall of the trench so as to leave a gap between the first filling structure and the sidewall of the trench.

[0029] In some alternative embodiments of the present application, the deposition process may be:

[0030] Chemical vapor deposition process; or

[0031] Atomic layer deposition process.

[0032] In some alternative embodiments of the present application, there are multiple conductive channels, and forming a gate around the conductive channels may include:

[0033] Depositing a gate oxide dielectric layer on the sidewalls of the columnar conductive channels;

[0034] Filling a conductive layer between the multiple conductive channels, and the gate oxide dielectric layer and the conductive layer constitute the gate.

[0035] In some alternative embodiments of the present application, after forming a gate around the conductive channels, the method for fabricating a semiconductor structure may further include:

[0036] Depositing a second active region on the conductive layer by using an epitaxial growth process.

[0037] In some alternative embodiments of the present application, after depositing a second active region on the conductive layer by using an epitaxial growth process, the method for fabricating a semiconductor structure may further include:

[0038] Pattern etching the second active region to form a columnar active region structure.

[0039] According to a second aspect of the embodiments of the present application, there is provided a semiconductor structure, which may include:

[0040] A substrate, on which there are insulating layers and trenches that crisscross each other, and the trenches cross each other;

[0041] Bit lines, which are located in the trenches;

[0042] A first active region, which covers the bit lines and fills the trenches;

[0043] Multiple columnar conductive channels, which are located in the first active region;

[0044] A gate, which is located between the multiple columnar conductive channels.

[0045] In some alternative embodiments of the present application, it may further include:

[0046] A second active region, which is located above the columnar conductive channels.

[0047] In some alternative embodiments of the present application, the second active region may be columnar.

[0048] In some alternative embodiments of the present application, the materials of the first active region and the second active region may be:

[0049] Silicon material doped with n-type impurities;

[0050] Silicon material doped with P-type impurities;

[0051] Silicon germanium material doped with n-type impurities; or

[0052] Silicon-germanium material doped with P-type impurities.

[0053] The above technical solution of the present application has the following beneficial technical effects:

[0054] The method of the embodiment of the present application includes providing a substrate; forming a trench in the substrate; forming a bit line in the trench; filling the trench by using an epitaxial growth process and depositing a first active region on the surface of the substrate, the first active region covering the bit line; patterning and etching the first active region to form a columnar conductive channel; and forming a gate around the conductive channel. In this way, the first source region can surround the bit line, increasing the contact area between the first active region and the bit line, reducing the contact resistance between the first active region and the bit line, thereby improving the charge transfer speed and ensuring the signal transmission performance. Description of the Drawings

[0055] Figure 1 It is a schematic flow chart of a method for preparing a semiconductor structure in an exemplary embodiment of the present application;

[0056] Figure 2 It is a schematic diagram of a substrate structure in an exemplary embodiment of the present application;

[0057] Figure 3 It is a schematic diagram of a substrate structure with a trench formed in an exemplary embodiment of the present application;

[0058] Figure 4 It is a schematic diagram of a structure for forming a first filling structure in an exemplary embodiment of the present application;

[0059] Figure 5 It is a schematic diagram of a structure after etching a gap in an exemplary embodiment of the present application;

[0060] Figure 6 It is a schematic diagram of a structure after completely etching away the first sacrificial layer in an exemplary embodiment of the present application;

[0061] Figure 7 It is a schematic diagram of a structure after partially etching away the first sacrificial layer in an exemplary embodiment of the present application;

[0062] Figure 8 It is a schematic diagram of a structure for epitaxially growing a first active region in an exemplary embodiment of the present application;

[0063] Figure 9 It is a schematic diagram of a structure for epitaxially growing a first active region in another exemplary embodiment of the present application;

[0064] Figure 10 It is a schematic diagram of a structure for forming a columnar conductive channel in an exemplary embodiment of the present application;

[0065] Figure 11It is a schematic structural diagram of forming a gate in an exemplary embodiment of the present application;

[0066] Figure 12 It is a schematic structural diagram of depositing a bit line and a first sacrificial layer in an exemplary embodiment of the present application;

[0067] Figure 13 It is a schematic structural diagram of depositing a bit line and a first sacrificial layer in another exemplary embodiment of the present application;

[0068] Figure 14 It is a schematic structural diagram after removing the sacrificial layer by wet etching in another exemplary embodiment of the present application;

[0069] Figure 15 It is a schematic structural diagram after etching the gap in another exemplary embodiment of the present application;

[0070] Figure 16 It is a schematic semiconductor structure diagram prepared in an exemplary embodiment of the present application;

[0071] Figure 17 It is a schematic semiconductor structure diagram in another exemplary embodiment of the present application;

[0072] Figure 18 It is a schematic semiconductor structure diagram in yet another exemplary embodiment of the present application. Detailed implementation manners

[0073] To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the specific implementation manners and the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0074] Schematic layer structure diagrams according to embodiments of the present application are shown in the drawings. These figures are not drawn to scale, where for the purpose of clarity, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes and relative positions according to actual needs.

[0075] Obviously, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0076] In the description of the present application, it should be noted that the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0077] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0078] Currently, in order to improve the integration of dynamic random access memory, vertical channel transistors are used. However, as the integration increases, there is also a problem of decreasing signal transmission performance. The inventor has found through research that the reason for the decrease in signal transmission performance is the contact resistance between the bit line contact structure and the active region. For this reason, the present application provides a method for preparing a semiconductor structure to solve this problem.

[0079] The following will combine the drawings and specifically illustrate the method for preparing a semiconductor structure provided by the embodiments of the present application through specific embodiments and their application scenarios.

[0080] As Figure 1 shown, according to the first aspect of the embodiments of the present application, a method for preparing a semiconductor structure is provided, and the method may include:

[0081] S110: Provide a substrate 1, on which an insulating layer is formed in a crisscross pattern;

[0082] S120: Form a trench in the substrate 1, and the trench penetrates the insulating layer;

[0083] S130: Form a bit line 2 in the trench;

[0084] S140: Use the epitaxial growth process to fill the trench and deposit a first active region 4 on the surface of the substrate 1, and the first active region 4 covers the bit line 2;

[0085] S150: Pattern and etch the first active region 4 to form a columnar conductive channel 5;

[0086] S160: Form a gate around the conductive channel 5.

[0087] The first source region of the semiconductor structure prepared by the method of the above embodiment can surround the bit line 2, increasing the contact area between the first active region 4 and the bit line 2, reducing the contact resistance between the first active region 4 and the bit line 2, thereby improving the charge transfer speed and ensuring the signal transmission performance.

[0088] For a more detailed introduction, the above steps will be described separately below:

[0089] First is step S110: Provide a substrate 1, on which an insulating layer is formed in a crisscross pattern.

[0090] In this step, the material of the substrate 1 includes but is not limited to silicon crystal or germanium crystal, silicon-on-insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysproside), alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or their combination). Exemplarily, a silicon-on-insulator substrate 1 is provided, such as Figure 2 as shown.

[0091] Next is step S120: forming a trench 11 in the substrate 1, and the trench penetrates the isolation layer.

[0092] Forming the trench 11 on the substrate 1 in this step can be carried out by dry etching or wet etching, as long as a trench 11 with a preset size can be formed on the substrate 1.

[0093] Exemplarily, dry etching is performed in the substrate 1 to form the trench 11, that is, the bit line 2 groove, as Figure 3 shown.

[0094] Next is step S130: forming a bit line 2 in the trench 11.

[0095] In this step, first, the bit line 2 and the first sacrificial layer 31 can be sequentially deposited inside the trench 11 by a deposition method to obtain a first filling structure that fills the trench 11, as Figure 4 shown.

[0096] Exemplarily, the deposition method can be a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process; the material of the sacrificial layer can include silicon oxide; the bit line 2 metal layer can include a barrier layer and a metal layer, where the material of the barrier layer can include titanium nitride (TiN), and this barrier layer can improve wear resistance, reduce the friction coefficient, and prevent adhesion. The material of the metal layer can include tungsten (W).

[0097] Then, the area of the first filling structure close to the side wall of the trench 11 is etched away to leave a gap between the first filling structure and the side wall of the trench 11, as Figure 5 shown;

[0098] Exemplarily, the dry etching method with better controllability and flexibility can be selected for etching the first filling structure by dry etching to obtain a side-by-side gap structure corresponding to the channel region.

[0099] Finally, the first sacrificial layer 31 is etched away.

[0100] Exemplarily, the etching method can be wet etching. Using wet etching to remove the first sacrificial layer 31 on the bit line 2 structure to form a structure as shown in Figure 6 or using wet etching to remove a part of the first sacrificial layer 31 on the bit line 2 structure, as shown in Figure 7 . The reason for choosing wet etching is that wet etching has the characteristics of good selectivity, good repeatability, high production efficiency, simple equipment, and low cost.

[0101] Next is step S140: Filling the trench 11 by epitaxial growth process and depositing and forming a first active region 4 on the surface of the substrate 1, and the first active region 4 covers the bit line 2.

[0102] In this step, a semiconductor thin film is deposited and grown inside the trench 11 and on the surface of the substrate 1 by epitaxial growth process, that is, the first active region 4 covering the bit line 2 in this embodiment, as shown in Figure 8 . The first active region 4 can be a silicon (Si) material doped with n-type impurities; a silicon (Si) material doped with P-type impurities; a silicon-germanium (SiGe) material doped with n-type impurities; or a silicon-germanium (SiGe) material doped with P-type impurities. This surrounding contact method covering the bit line 2 structure can greatly increase the contact area between the first active region 4 and the bit line 2, thereby reducing the contact resistance between the first active region 4 and the bit line 2, and further improving the charge transfer speed and ensuring the signal transmission performance. This step can also be carried out on the basis that the first sacrificial layer 31 is not completely etched away to form a structure with a part of the first sacrificial layer 31, as shown in Figure 9 .

[0103] For the bit line 2 structure prepared by the above method steps, the first active region 4 can surround the bit line 2 metal, increasing the contact area between the first active region 4 and the bit line 2 metal, thereby reducing the contact resistance between the first active region 4 and the bit line 2 metal, and further improving the charge transfer speed and ensuring the signal transmission performance.

[0104] Next is S150: Pattern etching the first active region 4 to form a columnar conductive channel 5.

[0105] In this step, an epitaxial process and dry etching are carried out on the first active region 4 to form a columnar conductive channel 5, as shown in Figure 10 . Exemplarily, on the first active region 4, a GAA channel is formed by EPI epitaxy, adding a layer of photomask, and etching to form a columnar channel structure. The doping material of the channel can be the same (junctionless) or different (junction type) from the first active region 4, and the doped impurity can be n-type or p-type.

[0106] Finally, it is step S160: Forming a gate around the conductive channel 5.

[0107] This step is to perform single-atom deposition on the sidewalls of the columnar conductive channels 5 to form the gate oxide dielectric layer 6; among which there are multiple columnar conductive channels 5, and a conductive layer 7 is filled between the multiple columnar conductive channels 5. The gate oxide dielectric layer 6 and the conductive layer 7 constitute the gate, as Figure 11 shown.

[0108] Exemplarily, performing single-atom deposition on the sidewalls of the columnar conductive channels 5 to form the gate oxide dielectric layer 6 can specifically be to perform single-atom deposition on the sidewalls, and use dry etching to remove the dielectric layers at the top and bottom, and finally form the sidewall gate oxide dielectric layer 6 flush with the channel. The material of the gate oxide dielectric layer 6 can include silicon oxide. Among them, there are multiple columnar conductive channels 5. Filling a conductive material on the bit line 2 structure to form the conductive layer 7 surrounding the gate oxide dielectric layer 6 can be to fill a conductive material in the gaps of the gate oxide dielectric layer 6. This conductive material can include titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), tungsten (W), ruthenium (Ru), copper (Cu), etc. The above structure is ground to form the conductive layer 7.

[0109] The first source region of the semiconductor structure obtained through the above steps can surround the bit line 2, increasing the contact area between the first active region 4 and the bit line 2, reducing the contact resistance between the first active region 4 and the bit line 2, thereby improving the charge transfer speed and ensuring the signal transmission performance.

[0110] In some alternative embodiments of the present application, due to the good anisotropy, high selectivity, good controllability, flexibility, repeatability of dry etching, the operation of fine lines is safe, it is easy to realize automation, there is no chemical waste liquid, and no pollution is introduced during the processing, and the cleanliness is high. Therefore, forming the trench 11 on the substrate 1 can specifically be:

[0111] Using the dry etching process to form the trench 11 on the substrate 1.

[0112] In some alternative embodiments of the present application, forming the bit line 2 in the trench 11 can include:

[0113] Using the deposition process to sequentially deposit the bit line 2 metal layer and the first sacrificial layer 31 in the trench 11 to obtain the first filling structure that fills the trench 11;

[0114] Etching away the region of the first filling structure close to the sidewall of the trench 11 so that there is a gap between the first filling structure and the sidewall of the trench 11;

[0115] Etching away the first sacrificial layer 31 to obtain the bit line 2.

[0116] There is a gap between the first filling structure of the semiconductor structure prepared by the method of the above embodiment and the side wall of the trench 11. Thus, the active region can wrap the bit line 2 in all directions, increasing the contact area between the active region and the bit line 2, reducing the contact resistance between the active region and the bit line 2, thereby improving the charge transfer speed and ensuring the signal transmission performance.

[0117] As Figure 12 shown, in some alternative embodiments of the present application, the bit line 2 metal layer includes a stacked first barrier layer, a metal layer, and a second barrier layer;

[0118] Using a deposition process, the bit line 2 metal layer and the first sacrificial layer 31 are sequentially deposited in the trench 11 to obtain a first filling structure that fills the trench 11. Specifically, it can be:

[0119] Using a deposition process, the first barrier layer, the bit line 2 metal, the second barrier layer, and the first sacrificial layer 31 are sequentially deposited inside the trench 11 to obtain a first filling structure that fills the trench 11.

[0120] In this embodiment, the materials of the first barrier layer and the second barrier layer may include titanium nitride (TiN), and the material of the metal layer may include tungsten metal (W). Depositing the first barrier layer and the second barrier layer can improve the wear resistance of the bit line 2 structure, reduce the friction coefficient of the bit line 2 structure, and prevent the bonding of the sacrificial layer to the bit line 2 structure.

[0121] In some alternative embodiments of the present application, before using a deposition process to sequentially deposit the bit line 2 metal layer and the first sacrificial layer 31 in the trench 11 to obtain a first filling structure that fills the trench 11, forming the bit line 2 in the trench 11 may further include:

[0122] Depositing and forming a second sacrificial layer 32 in the trench 11, as Figure 13 shown;

[0123] After etching away the region of the first filling structure close to the side wall of the trench 11 so that there is a gap between the first filling structure and the side wall of the trench 11, the method for preparing the semiconductor structure further includes:

[0124] Etching away a part of the second sacrificial layer 32, and the remaining part of the second sacrificial layer 32 is used to support the bit line 2 metal layer.

[0125] In this embodiment, two sacrificial layers, the first sacrificial layer 31 and the second sacrificial layer 32, are deposited inside the trench 11.

[0126] Exemplarily, a second sacrificial layer 32, a first barrier layer, a metal layer, a second barrier layer, and a first sacrificial layer 31 are sequentially deposited inside the trench 11 by a deposition method to form a first filling structure that fills the trench 11. After forming this structure, the region of the first filling structure close to the sidewall of the trench 11 is etched away so that there is a gap between the first filling structure and the sidewall of the trench 11. In this way, wet etching can be carried out using this gap to remove the second sacrificial layer 32 at the bottom part, and the remaining part of the second sacrificial layer 32 is used to support the upper bit line 2 structure.

[0127] There is a gap between the first filling structure of the semiconductor structure prepared by the method of the above embodiment and the sidewall of the trench 11, and there is also a gap between the bottom of the bit line and the substrate 1. Furthermore, the active region can completely cover the bit line 2 in all directions, greatly increasing the contact area between the active region and the bit line 2, reducing the contact resistance between the active region and the bit line 2, and then improving the charge transfer speed and ensuring the signal transmission performance.

[0128] In some alternative embodiments of the present application, etching away part of the second sacrificial layer 32 may specifically be:

[0129] Using wet etching to remove part of the second sacrificial layer 32, as Figure 14 shown.

[0130] As Figure 15 shown, in some alternative embodiments of the present application, etching away the region of the first filling structure close to the sidewall of the trench 11 so that there is a gap between the first filling structure and the sidewall of the trench 11 may specifically be:

[0131] Using dry etching to remove the region of the first filling structure close to the sidewall of the trench 11 so that there is a gap between the first filling structure and the sidewall of the trench 11.

[0132] In some alternative embodiments of the present application, the deposition process may be:

[0133] Chemical vapor deposition process; or

[0134] Atomic layer deposition process.

[0135] In some alternative embodiments of the present application, after forming a gate around the conductive channel 5, the method for preparing the semiconductor structure may further include:

[0136] Using an epitaxial growth process to deposit and form a second active region 8 on the conductive layer 7.

[0137] In some alternative embodiments of the present application, after using an epitaxial growth process to deposit and form a second active region 8 on the conductive layer 7, the method for preparing the semiconductor structure may further include:

[0138] The second active region 8 is etched graphically to form a columnar active region structure.

[0139] After this embodiment, the method may further include: forming an insulating isolation structure 9 on the sidewalls of the columnar second active region 8, and the insulating isolation structure 9 wraps around the sidewalls of the columnar second active region 8.

[0140] Exemplarily, the columnar second active region 8 of the GAA is formed by EPI. The doping material of the columnar second active region 8 may be the same as that of the first active region 4. An additional mask layer is added, and a columnar structure is formed after dry etching; an insulating material (such as silicon oxide) is filled in the spacing gaps between the plurality of columnar second active regions 8 to form the insulating isolation structure 9.

[0141] Such as Figure 17 As shown, in the second aspect of the embodiments of the present application, a semiconductor structure is provided. The semiconductor structure may include:

[0142] A substrate 1, on which there are insulating layers (not shown) and trenches 11 that crisscross each other;

[0143] Bit lines 2, the bit lines 2 are located in the trenches 11, and the trenches penetrate the insulating layers;

[0144] A first active region 4, the first active region 4 covers the bit lines 2 and fills the trenches 11;

[0145] A plurality of columnar conductive channels 5, the columnar conductive channels 5 are located in the first active region 4;

[0146] A gate, the columnar gate is located between the plurality of columnar conductive channels 5.

[0147] In this step, the material of the substrate 1 includes but is not limited to silicon crystal or germanium crystal, silicon-on-insulator (SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or dysprosium indide), alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or their combination).

[0148] In the semiconductor structure of this embodiment, the first source region wraps around the bit lines 2, increasing the contact area between the first active region 4 and the bit lines 2, reducing the contact resistance between the first active region 4 and the bit lines 2, thereby improving the charge transfer speed and ensuring the signal transmission performance.

[0149] In some alternative embodiments of the present application, it may further include:

[0150] A second active region 8, the second active region 8 is located above the columnar conductive channels 5.

[0151] In some alternative embodiments of the present application, the second active region 8 may be columnar.

[0152] In the semiconductor structure of the above embodiment, the first source region surrounds the bit line 2, increasing the contact area between the first active region 4 and the bit line 2, reducing the contact resistance between the first active region 4 and the bit line 2, thereby improving the charge transfer speed and ensuring the signal transmission performance.

[0153] In some alternative embodiments of the present application, the materials of the first active region 4 and the second active region 8 may be:

[0154] Silicon material doped with n-type impurities;

[0155] Silicon material doped with P-type impurities;

[0156] Silicon-germanium material doped with n-type impurities; or

[0157] Silicon-germanium material doped with P-type impurities.

[0158] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, comprising: providing a substrate, on which an intersecting isolation layer is formed; forming a trench in the substrate, the trench penetrating the isolation layer; forming a bit line in the trench; using an epitaxial growth process to fill the trench and deposit a first active region on the substrate surface, the first active region covering the bit line; pattern etching the first active region to form a columnar conductive channel; forming a gate around the conductive channel; The forming a bit line in the trench includes: using a deposition process to sequentially deposit a bit line metal layer and a first sacrificial layer in the trench to obtain a first filling structure filling the trench; etching away the region of the first filling structure close to the trench sidewall so that there is a gap between the first filling structure and the trench sidewall; etching away the first sacrificial layer to obtain the bit line; Before using the deposition process to sequentially deposit a bit line metal layer and a first sacrificial layer in the trench to obtain a first filling structure filling the trench, the forming a bit line in the trench further includes: depositing a second sacrificial layer in the trench; After etching away the region of the first filling structure close to the trench sidewall so that there is a gap between the first filling structure and the trench sidewall, the method for preparing the semiconductor structure further includes: etching away a part of the second sacrificial layer, and the remaining part of the second sacrificial layer is used to support the bit line metal layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The forming a trench in the substrate is specifically: using a dry etching process to form a trench in the substrate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The bit line metal layer includes a stacked first barrier layer, a metal layer and a second barrier layer; The using a deposition process to sequentially deposit a bit line metal layer and a first sacrificial layer in the trench to obtain a first filling structure filling the trench is specifically: using a deposition process to sequentially deposit a first barrier layer, a bit line metal, a second barrier layer and a first sacrificial layer inside the trench to obtain a first filling structure filling the trench.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching away a part of the second sacrificial layer is specifically: using a wet etching process to etch away a part of the second sacrificial layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching away the region of the first filling structure close to the trench sidewall so that there is a gap between the first filling structure and the trench sidewall is specifically: using a dry etching process to etch away the region of the first filling structure close to the trench sidewall so that there is a gap between the first filling structure and the trench sidewall.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The deposition process is: chemical vapor deposition process; or atomic layer deposition process.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, There are multiple conductive channels, and forming a gate around the conductive channels includes: Depositing a gate oxide dielectric layer on the sidewalls of the columnar conductive channels; Filling a conductive layer between the multiple conductive channels, and the gate oxide dielectric layer and the conductive layer form a gate.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein After forming a gate around the conductive channels, the method for manufacturing the semiconductor structure further includes: Depositing a second active region on the conductive layer by using an epitaxial growth process.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein After depositing a second active region on the conductive layer by using an epitaxial growth process, the method for manufacturing the semiconductor structure further includes: Pattern etching the second active region to form a columnar active region structure.

10. A semiconductor structure, wherein the semiconductor structure is manufactured by using the manufacturing method according to any one of claims 1-9, and is characterized in that It includes: A substrate, on which an insulating layer and trenches that crisscross each other are provided, and the trenches penetrate through the insulating layer; A bit line, and the bit line is located in the trenches; A first active region, which covers the bit line and fills the trenches; Multiple columnar conductive channels, and the columnar conductive channels are located in the first active region; A gate, and the gate is located between the multiple columnar conductive channels.

11. The semiconductor structure according to claim 10, wherein It further includes: A second active region, and the second active region is located above the columnar conductive channels.

12. The semiconductor structure according to claim 11, wherein The second active region is columnar.

13. The semiconductor structure according to claim 11, wherein The materials of the first active region and the second active region are: Silicon material doped with n-type impurities; Silicon material doped with P-type impurities; Silicon germanium material doped with n-type impurities; or Silicon germanium material doped with P-type impurities.

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