Method for forming a semiconductor structure and semiconductor structure

Abstract

An embodiment of the present application provides a method for forming a semiconductor structure and a semiconductor structure. Wherein, the method includes: providing a substrate, the substrate includes bit line trenches extending along a first direction and arranged along a second direction; forming a bit line structure in the bit line trenches; etching the substrate formed with the bit line structure to form an active region corresponding to the bit line structure; wherein: each column of the active regions arranged along the first direction includes active regions extending along a third direction, the first direction, the second direction and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

Description

Technical Field

[0001] This application relates to, but is not limited to, a method for forming a semiconductor structure and a semiconductor structure. Background Art

[0002] Semiconductor devices, such as Dynamic Random Access Memory (DRAM), include multiple memory cells, word lines (WL), and bit lines (BL). In related technologies, the manufacturing processes for WL and BL are relatively complex and need to be improved. Summary of the Invention

[0003] Embodiments of this application provide a method for forming a semiconductor structure and a semiconductor structure.

[0004] On the one hand, embodiments of this application provide a method for forming a semiconductor structure, including:

[0005] Providing a substrate, the substrate including bit line trenches extending along a first direction and arranged along a second direction;

[0006] Forming a bit line structure in the bit line trenches;

[0007] Etching the substrate having the bit line structure formed thereon to form an active region corresponding to the bit line structure; wherein:

[0008] Each column of the active regions arranged along the first direction includes active regions extending along a third direction, the first direction, the second direction, and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

[0009] On the other hand, embodiments of this application provide a semiconductor structure, including:

[0010] A substrate;

[0011] A bit line structure formed in the substrate, extending along a first direction and arranged along a second direction;

[0012] An active region corresponding to the bit line structure; wherein, each column of the active regions arranged along the first direction includes at least two active regions extending along a third direction;

[0013] The first direction, the second direction, and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

[0014] In the embodiments of the present application, a bit line structure is formed in a substrate including bit line trenches, and then the substrate is etched to form an active region, providing a method for forming a semiconductor structure different from the related art. The difference lies in that: in the related art, the active region is formed first and then the bit line structure is formed, while the solution provided by the embodiments of the present application forms the bit line structure first and then the active region. In this way, the solution provided by the embodiments of the present application does not require the use of filling and multiple etching processes, simplifying the process of forming the semiconductor structure. Description of the Drawings

[0015] Figures 1A to 1G It is a schematic structural diagram of the formation process of a semiconductor structure in the related art;

[0016] Figure 2A It is a schematic flow diagram of the method for forming a semiconductor structure provided by the embodiments of the present application;

[0017] Figures 2B to 2E It is a schematic structural diagram of the formation process of a semiconductor structure provided by the embodiments of the present application;

[0018] Figure 3A It is another schematic flow diagram of the method for forming a semiconductor structure provided by the embodiments of the present application;

[0019] Figure 3B It is a schematic structural diagram of the formation process of a semiconductor structure provided by the embodiments of the present application;

[0020] Figure 4A It is another schematic flow diagram of the method for forming a semiconductor structure provided by the embodiments of the present application;

[0021] Figures 4B to 4E It is a schematic structural diagram of the formation process of a semiconductor structure provided by the embodiments of the present application;

[0022] Figure 5A It is a schematic flow diagram of the method for forming a semiconductor structure in the embodiments of the present application;

[0023] Figure 5B It is a schematic structural diagram of the formation process of a semiconductor structure provided by the embodiments of the present application;

[0024] Figure 6A It is a schematic flow diagram of the method for forming a semiconductor structure in the embodiments of the present application;

[0025] Figures 6B to 6F It is a schematic structural diagram of the formation process of a semiconductor structure provided by the embodiments of the present application;

[0026] Figure 7A It is yet another schematic flow diagram of the method for forming a semiconductor structure provided by the embodiments of the present application;

[0027] Figures 7B to 7C Schematic structural diagram of the formation process of the semiconductor structure provided by the embodiment of the present application;

[0028] Figure 8A Schematic flow chart of the method for forming the semiconductor structure provided by the embodiment of the present application;

[0029] Figures 8B to 8E Schematic structural diagram of the formation process of the semiconductor structure provided by the embodiment of the present application;

[0030] Figure 9A Schematic flow chart of the method for forming the semiconductor structure provided by the embodiment of the present application;

[0031] Figures 9B to 9D Schematic structural diagram of the formation process of the semiconductor structure provided by the embodiment of the present application;

[0032] Figure 10A Schematic flow chart of the method for forming the semiconductor structure provided by the embodiment of the present application;

[0033] Figure 10B Schematic structural diagram of the formation process of the semiconductor structure provided by the embodiment of the present application.

[0034] The descriptions of the reference numerals are as follows:

[0035] 20 - substrate; 100 / 200 - substrate; 101 / 203 - word line trench; 102 / 204 - word line structure; 103 - first isolation layer; 104 / 2021b - conductive layer; 105 - first bit line contact layer; 106 / 202 - bit line structure; 120 - first insulating layer; 121 / 2010 - first mask layer; 122 / 2011 - first photoresist layer; 123 - metal conductive layer; 124 - second isolation layer; 125 - amorphous carbon layer; 126 - second mask layer; 127 - second photoresist layer; 201 - bit line trench; 205 - isolation layer; 206 - capping layer; 207 - sacrificial layer; 208 - air gap; 209 - insulating layer; 210 - word line structure layer; 210a - word line barrier layer; 210b - word line metal layer; 211 - mask layer; 212 - photoresist layer; 213 - mask pattern; 1001 / 2001 - active region; 1002 / 2002 - isolation region; 2021 - bit line conductive layer; 2021a - bit line barrier layer; 2022 - bit line contact layer; 214 - first mask bar; 215 - word line protection structure; 216 - second mask bar. Detailed implementation manners

[0036] Next, the specific technical solutions of the present application will be further described in detail in conjunction with the accompanying drawings in the embodiments of the present application. The following embodiments are used to illustrate the technical solutions of the present application, but are not used to limit the protection scope of the present application.

[0037] In the related art, such as Figures 1A to 1E , the formation process of a semiconductor structure will be described.

[0038] Referring to Figure 1A , a substrate 100 is provided, and the substrate 100 is etched to a preset thickness to form a plurality of semiconductor pillars arranged at intervals along the AA' direction in the substrate 100, and isolation trenches are formed between the semiconductor pillars. The height direction of the semiconductor pillars is the thickness direction of the substrate, and a plurality of active regions 1001 are subsequently formed in the semiconductor pillars. The active regions 1001 are strip-shaped pillars extending along the third direction (Z-axis direction), and the active regions 1001 are used to form active devices such as transistors. Silicon dioxide is deposited between adjacent active regions 1001 and on the surface of the active regions 1001 as an isolation region 1002, and the isolation region 1002 is used to isolate two adjacent active regions 1001 to form a plurality of active devices.

[0039] Referring to Figure 1B , the active regions 1001 and the isolation regions 1002 are etched to form a plurality of mutually parallel word line trenches 101, and the word line trenches 101 extend along the second direction (Y-axis direction) and are arranged along the first direction (X-axis direction).

[0040] Referring to Figure 1C , a word line structure 102 is formed in the word line trenches 101.

[0041] Referring to Figure 1D , a first isolation layer 103, a conductive layer 104, a first insulating layer 120, a first mask layer 121, and a first photoresist layer 122 are sequentially formed on the surfaces of the word line structure 102, the etched active regions 1001, and the etched isolation regions 1002. The first photoresist layer 122 is used to pattern the first mask layer 121, and then the patterned first mask layer 121 is used to etch the first isolation layer 103, the conductive layer 104, and the first insulating layer 120. The first mask layer 121 can be a multi-layer structure. For example, the first mask layer 121 can include a hard mask layer, a barrier layer, and an insulating layer stacked in sequence.

[0042] Referring to Figure 1E , Figure 1E The left figure in Figure 1E and the right figure in

[0043] are different cross-sections of the same structure. The conductive layer 104 is etched to form a first bit line contact layer 105. The first insulating layer 120 is used to protect the conductive material located below the second insulating layer 120 from being contaminated when the conductive layer 104 is etched to form the first bit line contact layer 105, and is removed after the conductive layer 104 is etched to form the bit line contact layer 105. Figure 1F and Figure 1G, a metal conductive layer 123, a second isolation layer 124, an amorphous carbon layer 125 (Amorphous Carbon Layer, ALC), a second mask layer 126, and a second photoresist layer 127 are sequentially formed on the bit line contact layer 105. The second photoresist layer 127 patterns the second mask layer 126, and then the patterned second mask layer 126 is used to etch the metal conductive layer 123, the second isolation layer 124, and the bit line contact layer 105. The etched metal conductive layer 123 and the etched first bit line contact layer 105 form a plurality of mutually parallel bit line structures 106, and the etched second isolation layer 124 forms a third isolation layer.

[0044] Since parasitic capacitance will be generated between the plurality of bit line structures 106, which is particularly obvious between adjacent bit line structures 106, it is necessary to fill silicon nitride at the bottom of the bit line structures 106 and form a Nitride-Oxide-Nitride (N-O-N) structure on the sidewalls of the bit line structures 106.

[0045] Based on the above, the manufacturing process of the semiconductor structure is relatively complex.

[0046] To solve the above problems, an embodiment of the present application provides a method for forming a semiconductor structure, refer to Figure 2A , including the following steps:

[0047] S10. Provide a substrate, where the substrate includes bit line trenches extending along a first direction and arranged along a second direction.

[0048] The substrate can be a silicon substrate, or can include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InP), or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0049] Here, the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the fourth direction. In the direction of the top surface and the bottom surface of the substrate, two intersecting (e.g., perpendicular to each other) first direction and second direction are defined. For convenience of description, in the embodiments of the present application, the arrangement direction of a plurality of bit line trenches is defined as the second direction, and the extending direction of the bit line trenches is defined as the first direction. Based on the first direction and the second direction, the planar direction of the substrate can be determined. In the embodiments of the present application, the plane where the first direction and the second direction are located is defined as the horizontal plane. The first direction and the second direction have a certain included angle. The third direction is located between the first direction and the second direction, and the first direction, the second direction and the third direction are in the same plane. For ease of understanding, the first direction can be understood as the X-axis direction, the second direction can be understood as the Y-axis direction, the third direction can be understood as the Z-axis direction, and the fourth direction can be understood as the U-axis direction, such as the thickness direction of the substrate.

[0050] Here, the bit line trench has a preset depth. The depth direction of the bit line trench is the thickness direction of the substrate, that is, the fourth direction U direction, and the preset depth of the bit line trench is less than the thickness of the substrate.

[0051] S20. Form a bit line structure in the bit line trench.

[0052] Here, the bit line structure may be completely located within the bit line trench, or part of the bit line structure may be located within the bit line trench, that is, the top surface of part of the bit line structure is higher than the top surface of the substrate.

[0053] Here, the bit line structure is used to be electrically connected to the active region in the semiconductor device. The bit line structure may be a single-layer structure or a multi-layer composite structure. The bit line structure may include a bit line metal layer, and the material of the bit line metal layer includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0054] S30. Etch the substrate formed with the bit line structure to form an active region corresponding to the bit line structure; wherein, each column of the active regions arranged along the first direction includes active regions extending along the third direction. The first direction, the second direction and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset included angle and a second preset included angle with the first direction.

[0055] Here, wet etching, dry etching or other suitable etching processes can be used, for example, plasma etching, reactive ion etching, etc. The first preset included angle and the second preset included angle may be less than 90 degrees.

[0056] Next, refer to Figures 2B to 2D, the above steps S10 to S30 will be described. First, referring to Figure 2B , perform step S10 to provide a substrate 20, where the substrate 20 includes at least two bit line trenches 201 extending in the X-axis direction and arranged in the Y-axis direction; the at least two bit line trenches 201 are parallel to each other. Referring to Figure 2C , perform step S20 to form a bit line structure 202 in each bit line trench 201. Adjacent bit line structures 202 are parallel to each other in the X-axis direction and arranged in the Y-axis direction.

[0057] Next, referring to Figure 2D , perform step S30 to etch the substrate 20 formed with the bit line structure 202 to form an active region 2001 corresponding to the bit line structure 202. The plurality of active regions 2001 extend in the Z-axis direction, each bit line structure 202 corresponds to a column of active regions 2001, and each column of active regions 2001 includes at least two spaced-apart active regions 2001.

[0058] In this way, the substrate remaining after etching in step S30 can be regarded as a substrate 200, and the depth of the bit line trench 201 can be the height of the bit line structure 202. At the same time, each active region 2001 is divided into two parts by the corresponding bit line structure 202, and can be used as the source region / drain region of a semiconductor device to form a transistor, and the bit line structure 202 is electrically connected to the source region / drain region of the corresponding transistor.

[0059] In implementation, the conductive type of the source region / drain region and the substrate 200 can be different. For example, the source region / drain region can be an N-type semiconductor, and the substrate 200 can be a P-type semiconductor.

[0060] In some embodiments, the method of forming the substrate 20 can refer to Figure 2E , and at least includes the following steps:

[0061] Provide a substrate 200, sequentially form a first mask layer 2010 and a first photoresist layer 2011 on the substrate 200, pattern the first mask layer 2010 by using the first photoresist layer 2011 to form a bit line pattern 2012, and the bit line pattern 2012 exposes the surface of the substrate 200 corresponding to the bit line trench 201. Etch the substrate 200 through the bit line pattern 2012 to form a substrate 20 with bit line trenches 201 extending in the X-axis direction and arranged in the Y-axis direction.

[0062] Here, the substrate can be a silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film substrate obtained by performing a selective epitaxial growth process. The etching can be dry etching or wet etching.

[0063] In the embodiments of the present application, a bit line structure is formed in a substrate including bit line trenches, and then the substrate is etched to form active regions, providing a method for forming a semiconductor structure different from the related art. The difference lies in that in the related art, the active regions are formed first and then the bit line structure is formed, while in the embodiments of the present application, the bit line structure is formed first and then the active regions are formed. Thus, the solution provided by the embodiments of the present application does not require the use of filling and multiple etching processes, simplifying the process for forming the semiconductor structure.

[0064] Based on Figure 2A the provided method for forming a semiconductor structure, a semiconductor structure as Figure 2D shown is formed, and the structure includes:

[0065] a substrate;

[0066] a bit line structure 202 formed in the substrate and extending along a first direction (X-axis direction) and arranged along a second direction (Y-axis direction);

[0067] active regions 2001 corresponding to the bit line structure 202; wherein, each column of active regions 2001 arranged along the first direction includes at least two active regions 2001 extending along a third direction (Z-axis direction);

[0068] the first direction, the second direction, and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

[0069] The embodiments of the present application provide a method for forming a semiconductor structure. Referring to Figure 3A , after step S30, it further includes: S40. Filling an insulating material between the active regions to form an isolation region; wherein, the isolation region is used to isolate the active regions.

[0070] Here, the insulating material may include one or more of silicon oxides, and the insulating material can be formed by any suitable deposition process, for example, Chemical Vapor Deposition (CVD) process, Physical Vapor Deposition (PVD) process, or Atomic Layer Deposition (ALD) process, etc. The isolation region can be used as a Shallow Trench Isolation (STI).

[0071] The following refers to Figure 3B to illustrate step S40. Depositing an insulating material between the active regions 2001 to form an isolation region 2002, and the isolation region is a connected one. The isolation region 2002 is used to isolate adjacent active regions 2001.

[0072] Based on Figure 3A a method for forming a semiconductor structure provided, form a semiconductor as shown in Figure 3B Figure 1, the semiconductor structure further includes: an isolation region 2002 located between active regions 2001; wherein, the isolation region 2002 is used to isolate the active regions 2001.

[0073] In some embodiments, referring to Figure 4A Figure 2, after step S40, steps S50 and S60 are further included. Wherein:

[0074] S50, etch the active regions, the isolation region, and the bit line structure with a preset width and a preset depth to form a plurality of word line trenches arranged along the first direction and extending along the second direction.

[0075] Here, the preset depth may be less than the thickness of the substrate.

[0076] S60, form a word line structure in each of the word line trenches.

[0077] Here, the word line structure may be an embedded type, and the word line structure may include a conductive material, for example, tungsten, cobalt, copper, aluminum, polysilicon, titanium nitride, or any combination of the above conductive materials.

[0078] Next, referring to Figures 4B to 4E Figure 3, steps S50 and S60 will be described. First, referring to Figure 4B Figure 3 Figure 4C and Figure 4C Figure 4 Figure 4B wherein, Figure 4D Figure 3 Figure 4E is Figure 4E a cross-sectional structure diagram along AA', execute step S50, etch the active region 2001, the isolation region 2002, and the bit line structure 202 to form a plurality of word line trenches 203 arranged along the X-axis direction and extending along the Y-axis direction. The word line trenches 203 have a preset width w1 and a preset depth d1. Secondly, referring to Figure 4D Figure 5

[0079] In some embodiments, referring to Figure 5A Figure 6, the bit line structure includes a bit line metal layer and a bit line conductive layer. Step S20 can be implemented by steps S201 to S202. Wherein:

[0080] S201, form a bit line metal layer in each of the bit line trenches.

[0081] Here, the material of the bit line metal layer can be a metal material, a metal compound, or a combination of the above materials. Among them, the metal materials are, for example, tungsten, cobalt, copper, and aluminum, and the metal compounds are, for example, titanium nitride. The material of the bit line contact layer can be single-crystalline silicon, polycrystalline silicon, or other conductive materials.

[0082] S202. Form at least a bit line contact layer on the surface of the bit line metal layer, and the bit line contact layer is connected to the active region.

[0083] Here, the material of the bit line contact layer can be single-crystalline silicon, polycrystalline silicon, or other conductive materials.

[0084] Reference Figure 5B To illustrate steps S201 and S202, the bit line structure 202 includes a bit line metal layer 2021 and a bit line contact layer 2022. Correspondingly, a bit line structure 202 is formed in each bit line trench (see the bit line trench 201 in Figure 2B . It includes: forming a bit line metal layer 2021 in each bit line trench 201, and forming at least a bit line contact layer 2022 on the surface of the bit line metal layer 2021. The bit line contact layer 2022 is connected to the active region 2001 to achieve the electrical connection between the bit line structure 202 and the active region 2001. When the semiconductor structure includes a transistor, the active region 2001 is provided with a source region / drain region, and the bit line structure 202 is electrically connected to the source region / drain region through the bit line contact layer 2022.

[0085] In this embodiment, the bit line structure includes a two-layer structure of a bit line metal layer and a bit line contact layer, which can reduce the resistance of the bit line structure and provide better electrical conductivity for the bit line structure.

[0086] In some embodiments, continuing to refer to Figure 5B , after step S202, there is also step S203: forming a capping layer 206 on the bit line contact layer 2022. Here, the material of the capping layer 206 can be silicon nitride, the upper surface of the capping layer 206 is flush with the surface of the active region 2001, and the capping layer 206 is used to protect the bit line contact layer 2022 to prevent the performance of the bit line structure 202 from being affected or even failing due to damage to the bit line contact layer 2022 during subsequent other process steps.

[0087] In some embodiments, the bit line metal layer includes a bit line barrier layer and a conductive layer; referring to Figure 6A , step S20 can also be implemented through steps S601 to S606. Among them:

[0088] S601. Form an isolation layer in each of the bit line trenches.

[0089] Here, the function of the isolation layer is to isolate the bit line structure and the substrate, and the material of the isolation layer can be silicon nitride.

[0090] S602. Form a sacrificial layer in the bit line trench in which the isolation layer is formed, where the sacrificial layer covers at least the sidewalls of the bit line trench.

[0091] Here, the material of the sacrificial layer can be the same as that of the isolation layer, that is, it can also be silicon nitride. The sacrificial layer can cover the sidewalls and the bottom of the bit line trench, or it can only cover the sidewalls of the bit line trench. In other words, the sacrificial layer can be regarded as the sidewall of the bit line metal layer.

[0092] S603. Form a bit line barrier layer in the bit line trench in which the sacrificial layer is formed, where the bit line barrier layer covers the sidewalls and the bottom surface of the sacrificial layer;

[0093] Here, the function of the bit line barrier layer is to protect the active region and prevent the materials used for forming the conductive layer subsequently from contaminating the active region, resulting in device failure. The material of the bit line barrier layer can be titanium nitride.

[0094] S604. Form a conductive layer, where the conductive layer fills the bit line trench and the top surface of the conductive layer is lower than the upper surface of the substrate.

[0095] Here, the material of the conductive layer can be tungsten, cobalt, copper, aluminum, or other suitable materials.

[0096] S605. Form a bit line contact layer at least on the surface of the bit line metal layer, where the bit line contact layer is connected to the active region.

[0097] So far, the three-layer structure including the isolation layer, the bit line metal layer, and the bit line contact layer is included in the bit line trench from bottom to top. Among them, the bit line metal layer includes a sandwich structure, and from the sidewall inside the bit line trench, it includes a sacrificial layer, a bit line barrier layer, and a conductive layer in sequence. Thus, the surface of the bit line metal layer in step S605 refers to the upper surface of the bit line metal layer, and the upper surface includes the end faces of the sacrificial layer, the bit line barrier layer, and the conductive layer.

[0098] S606. Form a capping layer on the bit line contact layer.

[0099] The following refers to Figures 6B to 6E to illustrate the above steps S601 to S606.

[0100] Refer to Figure 6B , execute step S601, and deposit and form an isolation layer 205 in the bit line trench 201. See Figure 6C , execute step S602, and form a sacrificial layer 207 in the bit line trench 201 in which the isolation layer 205 is formed, where the sacrificial layer 207 covers the sidewalls and the bottom of the bit line trench 201.

[0101] See Figure 6D, Steps S603 and S604 are performed. In the bit line trench 201 formed with the sacrificial layer 207, a bit line barrier layer 2021a is formed, and the bit line barrier layer 2021a covers the side wall and the bottom surface of the sacrificial layer 207; a conductive layer 2021b is formed, and the conductive layer 2021b is filled in the bit line trench 201 and the top surface of the conductive layer 2021b is lower than the upper surface of the substrate (see Figure 2B the substrate 20 in

[0102] See Figure 6E , Steps S605 and S606 are performed. A bit line contact layer 2022 is formed on the surface of the bit line metal layer 2021, and the bit line contact layer 2022 is connected to the active region 2001; a capping layer 206 is formed on the bit line contact layer 2022. Here, the bit line metal layer 2021 includes the bit line barrier layer 2021a and the conductive layer 2021b.

[0103] Based on Steps S601 to S606, a semiconductor structure as shown in Figure 6E is formed. In the semiconductor structure provided by the embodiments of the present application, the bit line structure 202 includes a bit line metal layer 2021 and a bit line contact layer 2022. The semiconductor structure further includes: an isolation layer 205 in contact with the bit line metal layer 2021 and located below the bit line metal layer 2021, and a capping layer 206 on the surface of the bit line contact layer 2022.

[0104] In some embodiments, Step S50, etching the active region, the isolation region, and the bit line structure with a preset width and a preset depth along the second direction to form a plurality of word line trenches arranged along the first direction, includes:

[0105] Using the surface of the capping layer as the etching starting point and at least the surface of the bit line contact layer in contact with the bit line metal layer as the etching end point, etching the active region, the isolation region, and the bit line structure with a preset width and a preset depth, and retaining a preset thickness of the bit line metal layer to form a plurality of word line trenches arranged along the first direction and extending along the second direction.

[0106] Here, wet etching or dry etching can be used to form the word line trenches. The preset depth is equal to the thickness of the capping layer, or the preset depth is greater than the sum of the thicknesses of the capping layer and the bit line contact layer, and the preset depth is less than the sum of the thicknesses of the bit line metal layer, the bit line contact layer, and the capping layer. In other words, the bottom surface of the word line trench can be flush with the top surface of the bit line metal layer, or the bottom surface of the word line trench can be lower than the top surface of the bit line metal layer and higher than the bottom surface of the bit line metal layer.

[0107] Refer to Figure 6FThe above steps will be described. Taking the surface of the capping layer 206 as the etching starting point and the etching end point being located in the bit line metal layer 2021, the active region 2001, the isolation region 2002 and the bit line structure 202 are etched to form a plurality of mutually parallel word line trenches 203 having a preset depth d2 and a preset width w2.

[0108] In this embodiment, a bit line metal layer with a preset thickness is retained, which can ensure the normal operation of the bit line structure.

[0109] In some embodiments, referring to Figure 7A , after forming the plurality of word line trenches arranged along the first direction, the method further includes: S70, etching the sacrificial layer to form an air gap between the sidewalls of the bit line structure and the bit line trench. Here, wet etching of the sacrificial layer can be used.

[0110] Referring to Figure 7B , the sacrificial layer 207 is etched to form an air gap 208 (Air Gap) between the sidewalls of the bit line structure 202 and the bit line trench 201. Since parasitic capacitance will be generated between multiple bit line structures 202, this situation is particularly obvious between adjacent bit line structures 202. Since the dielectric constant of air is generally considered to be approximately equal to 1 and the sacrificial layer 207 can play an insulating and isolating role with a dielectric constant generally greater than 1, by etching the sacrificial layer 207 and providing an air gap 208 between the sidewalls of the bit line trench 201, the dielectric constant of the dielectric layer between the bit line metal layer 2021 and the substrate 20 can be reduced while ensuring insulation, and the dielectric constant of the dielectric layer between the bit line structure 202 and the active region 2001, between the bit line structure 202 and the isolation region, and between multiple bit line structures 202 can be reduced, thereby reducing the parasitic capacitance between the bit line structure 202 and the active region 2001, between the bit line structure 202 and the isolation region, and between multiple bit line structures 202.

[0111] Based on Figure 7A The semiconductor structure forming method provided forms a structure as shown in Figure 7B . In some embodiments, referring to Figure 7B , the semiconductor structure further includes an air gap 208 formed on the sidewall of the bit line metal layer 2021.

[0112] In addition, referring to Figure 7C , when etching the sacrificial layer 207 and when the materials of the capping layer 206 and the isolation layer 207 are the same or similar, a part of the surface of the capping layer 206 will be etched.

[0113] In some embodiments, referring to Figure 8A , step S60, forming a word line structure in each word line trench may include the following steps:

[0114] S801. Form an insulating layer on the surface of each of the word line trenches.

[0115] Here, the insulating layer is the gate oxide layer of the word line structure. The material of the insulating layer may include one or more of silicon oxides, for example, silicon dioxide. The insulating layer can be formed by any suitable deposition process, such as chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process, etc.

[0116] S802. Form a word line structure layer on the surface of the insulating layer.

[0117] Here, the word line structure layer may include a word line barrier layer and a word line metal layer. The word line barrier layer is used to improve the adhesion effect between the word line metal layer and other structures. The material of the word line barrier layer can be titanium nitride, and the material of the word line metal layer can be tungsten.

[0118] S803. Etch the word line structure layer to form a word line structure; wherein, the top surface of the word line structure is lower than the bottom surface of the bit line contact layer.

[0119] Next, refer to Figures 8B to 8D , and describe the above steps S801 to S803.

[0120] Refer to Figure 8B , execute step S801 to form an insulating layer 209 on the surface of each word line trench 203. Execute step S802 to form a word line structure layer 210 as shown in Figure 8C on the surface of the insulating layer 209. The word line structure layer 210 may include a word line barrier layer 210a and a word line metal layer 210b. Execute step S803 to etch the word line structure layer 210 to form a word line structure 204 as shown in Figure 8D ; wherein, the top surface of the word line structure 204 is lower than the bottom surface of the bit line contact layer 2022.

[0121] In some embodiments, after step S60, it further includes: forming a word line protection structure on the surface of the word line structure. Refer to Figure 8E , and form a word line protection structure 215 on the surface of the word line structure 204.

[0122] In some embodiments, step S603 includes: using the surface of the word line structure layer as the etching starting point and the 1 / 3 to 2 / 3 thickness of the bit line metal layer as the etching end point to etch the word line structure layer to form the word line structure. As shown in Figure 8D , the top surface of the word line structure 204 is lower than the top surface of the bit line metal layer 2021, and the distance between the top surface of the word line structure 204 and the top surface of the bit line metal layer 2021 is 1 / 3 of the thickness of the bit line metal layer 2021.

[0123] In this embodiment, when forming the word line structure, by setting the etching end point, the cross-sectional area of the word line structure is increased. Since the larger the cross-sectional area of the word line structure, the smaller the resistance, the formed word line structure has a smaller resistance. In addition, without cutting off the bit line structure, the overlapping area between the word line structure and the bit line structure can be reduced, thereby reducing the parasitic capacitance.

[0124] Correspondingly, in some embodiments, referring to Figure 8D , the semiconductor structure further includes: a plurality of word line structures 204 extending along the second direction (Y-axis direction) and arranged along the first direction (X-axis direction);

[0125] The bottom surface of the word line structure 204 is located at 1 / 3 to 2 / 3 of the height of the bit line metal layer 2021;

[0126] The top surface of the word line structure 204 is lower than the surface where the bit line contact layer 2022 contacts the bit line metal layer 2021.

[0127] In some embodiments, referring to Figure 9A , step S30 is implemented through steps S301 to S303. Among them:

[0128] S301. A mask layer and a photoresist layer are sequentially formed on the surface of the substrate on which the bit line structure is formed.

[0129] Here, the mask layer can be a double-layer structure or a single-layer structure. The material used for the mask layer can be one or several of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, titanium, and the mask layer can be formed by any one of the following processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating process or any other suitable process.

[0130] S302. Pattern the mask layer and the photoresist layer to form a mask pattern.

[0131] Here, patterning means using a lithography process to make the photoresist layer and the mask layer have a mask pattern, where the mask pattern defines the position of the active region.

[0132] S303. Use the mask pattern to etch the substrate on which the bit line structure is formed to form a column of active regions along the first direction corresponding to each bit line trench; wherein, the bottom surface of the active region is lower than the bottom surface of each corresponding bit line structure.

[0133] The following refers to Figures 9B to 9D to illustrate steps S301 to S303. Referring to Figure 9B, a mask layer 211 and a photoresist layer 212 are sequentially formed on the surface of the substrate 20 on which the bit line structure 202 is formed. Continuing to refer to Figure 9B , the mask layer 211 and the photoresist layer 212 are patterned to form a mask pattern 213 as shown in Figure 9C . Continuing to refer to Figure 9C , the substrate 20 on which the bit line structure 202 is formed is etched using the mask pattern 213. The substrate 20 is protected by the mask pattern 213 and thus remains during the etching process. The portions of the substrate 20 that are not protected by the mask pattern 213 are etched, and finally a plurality of isolated active regions 2001 as shown in Figure 9D are formed. The plurality of active regions 2001 are divided into multiple columns, and each bit line structure 202 has a corresponding column of active regions 2001 along the X-axis direction. The bottom surface of any one of the active regions 2001 is lower than the bottom surface of the corresponding bit line structure 202.

[0134] In some embodiments, referring to Figure 10A , step S302 can be implemented through step S3021 and step S3022. Wherein:

[0135] S3021. Pattern the mask layer using the photoresist layer to form a plurality of first mask strips parallel to each other along a third direction.

[0136] S3021. Pattern each of the first mask strips at least once to form the mask pattern; wherein, the mask pattern includes at least two second mask strips with a preset length.

[0137] Here, the length of the first mask strip is greater than the length of the second mask strip.

[0138] Next, referring to Figure 9B , Figure 10B and Figure 9C will describe steps S3021 to S3022.

[0139] Referring to Figure 9B , processes such as exposure, development, and resist washing are performed on the photoresist layer 212. The portion of the mask layer 211 that is protected by the remaining portion of the photoresist layer 212 is etched, and the portion protected by the photoresist 212 is retained to form a plurality of first mask strips 214 parallel to each other and extending along the Z-axis direction as shown in Figure 10B . The extending direction of the first mask strip 214 is the extending direction of the subsequent formed active regions 2001.

[0140] Referring to Figure 10B , the first mask strip 214 is patterned at least once to cut the first mask strip 214, forming as shown in Figure 9CThe mask pattern 213 shown. Thus, each mask pattern 213 includes at least two segments of second mask strips 216 having a preset length. By way of example, the first mask strip 214 is etched using a first shearing photomask and a second shearing photomask in sequence to form a plurality of second mask strips 216, and the plurality of second mask strips 216 constitute the mask pattern 213. The preset length of the second mask strip 216 is the length of the active region 2001.

[0141] The features disclosed in the method or semiconductor structure embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or semiconductor structure embodiments.

[0142] The description of the above semiconductor structure embodiments is similar to the description of the above method embodiments and has beneficial effects similar to those of the method embodiments. For the technical details not disclosed in the semiconductor embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0143] As described above, the above are only exemplary embodiments of this application and are not used to limit the protection scope of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included in the protection scope of this application. Therefore, the protection scope of the embodiments of this application shall be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including bit line trenches extending in a first direction and arranged in a second direction; Forming a bit line structure in the bit line trenches; Etching the substrate having the bit line structure formed thereon to form an active region corresponding to the bit line structure; wherein: Each column of the active regions arranged in the first direction includes active regions extending in a third direction, the first direction, the second direction, and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

2. The method according to claim 1, characterized in that Further including: Filling an insulating material between the active regions to form an isolation region; wherein, the isolation region is used to isolate the active regions.

3. The method according to claim 2, wherein Further including: Etching the active regions, the isolation region, and the bit line structure with a preset width and a preset depth to form a plurality of word line trenches arranged in the first direction and extending in the second direction; Forming a word line structure in each of the word line trenches.

4. The method according to claim 3, characterized in that The bit line structure includes a bit line metal layer and a bit line contact layer; The forming the bit line structure in each of the bit line trenches includes: Forming a bit line metal layer in each of the bit line trenches; Forming at least a bit line contact layer on the surface of the bit line metal layer, and the bit line contact layer is connected to the active region.

5. The method according to claim 4, wherein Before forming the bit line metal layer in each of the bit line trenches, further including: forming an isolation layer in each of the bit line trenches; After forming at least the bit line contact layer on the surface of the bit line metal layer, further including: Forming a capping layer on the bit line contact layer.

6. The method according to claim 5, characterized in that, The bit line metal layer includes a bit line barrier layer and a conductive layer; the method further includes: Forming a sacrificial layer in the bit line trench having the isolation layer formed thereon, the sacrificial layer covering the sidewalls and the bottom surface of the bit line trench; The forming the bit line metal layer in each of the bit line trenches includes: Forming a bit line barrier layer in the bit line trench having the sacrificial layer formed thereon, the bit line barrier layer covering the sidewalls and the bottom surface of the sacrificial layer; Forming a conductive layer, the conductive layer filling the bit line trench and the top surface of the conductive layer being lower than the upper surface of the substrate.

7. The method according to claim 5, characterized in that, The etching the active regions, the isolation region, and the bit line structure with a preset width and a preset depth along the second direction to form a plurality of word line trenches arranged in the first direction and extending in the second direction includes: Using the surface of the capping layer as an etching starting point and at least using the surface where the bit line contact layer contacts the bit line metal layer as an etching end point, etching the active regions, the isolation region, and the bit line structure with a preset width and a preset depth, and retaining a preset thickness of the bit line metal layer to form a plurality of word line trenches arranged in the first direction and extending in the second direction.

8. The method according to claim 6, wherein After forming the plurality of word line trenches arranged in the first direction, the method further includes: Etching the sacrificial layer to form an air gap between the bit line structure and the sidewall of the bit line trench.

9. The method according to claim 4, wherein The forming a word line structure in each of the word line trenches includes: Forming an insulating layer on the surface of each of the word line trenches; Forming a word line structure layer on the surface of the insulating layer; Etch the word line structure layer to form a word line structure; wherein, the top surface of the word line structure is lower than the bottom surface of the bit line contact layer.

10. The method according to claim 9, characterized in that, The etching of the word line structure layer to form a word line structure includes: Using the surface of the word line structure layer as the etching starting point and the 1 / 3 - 2 / 3 position of the thickness of the bit line metal layer as the etching end point, etch the word line structure layer to form the word line structure.

11. The method according to any one of claims 1 to 10, characterized in that, The etching of the substrate having the bit line structure formed thereon to form an active region corresponding to the bit line structure includes: Sequentially form a mask layer and a photoresist layer on the surface of the substrate having the bit line structure formed thereon; Pattern the mask layer and the photoresist layer to form a mask pattern; Use the mask pattern to etch the substrate having the bit line structure formed thereon to form a column of active regions along the first direction corresponding to each bit line trench; wherein, the bottom surface of the active region is lower than the bottom surface of each corresponding bit line structure.

12. The method according to claim 11, wherein The patterning of the mask layer and the photoresist layer to form a mask pattern includes: Simultaneously etch the mask layer and the photoresist layer to form a plurality of first mask strips parallel to each other along the third direction; Perform patterning on each of the first mask strips at least once to form the mask pattern; wherein, the mask pattern includes at least two second mask strips having a preset length.

13. The method according to any one of claims 3 to 10, characterized in that, After forming a word line structure in each word line trench, the method further includes: Form a word line protection structure on the surface of the word line structure.

14. A semiconductor structure, characterized in that, Including: A substrate; Bit line structures formed in the substrate and extending along a first direction and arranged along a second direction; Active regions corresponding to the bit line structures; wherein, each column of the active regions arranged along the first direction includes at least two active regions extending along the third direction, and each active region is divided into two parts by the corresponding bit line structure in the third direction, and the bit line structure is electrically connected to the two divided parts; The first direction, the second direction, and the third direction are in the same plane, and the second direction and the third direction respectively have a first preset angle and a second preset angle with the first direction.

15. The structure according to claim 14, wherein, Further including: Isolation regions located between the active regions; wherein, the isolation regions are used to isolate the active regions.

16. The structure according to claim 15, characterized in that, The bit line structure includes a bit line metal layer and a bit line contact layer, and the semiconductor structure further includes: an isolation layer in contact with the bit line metal layer and located below the bit line metal layer, and a capping layer on the surface of the bit line contact layer.

17. The structure according to claim 16, characterized in that, Further including: Air gaps formed on the sidewalls of the bit line metal layer.

18. The structure according to claim 16, characterized in that, Further including: A plurality of word line structures extending along the second direction and arranged along the first direction; The bottom surface of the word line structure is located at the 1 / 3 to 2 / 3 position of the height of the bit line metal layer; The top surface of the word line structure is lower than the surface where the bit line contact layer contacts the bit line metal layer.

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