Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, an isolation structure, a plurality of bit line structures, a plurality of word line structures, a plurality of bit line contacts, and a plurality of contact pads. The substrate includes a cell region and a peripheral region. The isolation structure is disposed in the cell region of the substrate to define a plurality of active regions. The bit line structures are disposed in the substrate parallel to each other and each extends in a first horizontal direction and across the plurality of active regions. The word line structures are disposed on the substrate parallel to each other and each extends in a second horizontal direction. The bit line contacts are disposed on the substrate and between the word line structures, wherein a top surface of the bit line contacts is lower than a top surface of the word line structures. The contact pads are disposed on the top surface of the bit line contacts and electrically connected to the bit line contacts.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Memory can be mainly divided into volatile memory, such as dynamic random access memory (DRAM), and non-volatile memory, such as flash memory. Generally speaking, DRAM may include storage nodes for storing charge carriers. Typically, storage pads are formed in the cell region of the DRAM to electrically connect the storage nodes to storage node contacts, in order to improve the alignment between the storage nodes and the storage node contacts.

[0003] However, the above-mentioned fabrication process for forming storage pads usually requires multiple photolithography processes to define, and the formation process can easily damage the structure, wiring or components in other film layers, which will lead to problems such as poor device performance, poor fabrication yield and high manufacturing cost. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for manufacturing the same, which can omit at least one photomask during the formation process and is less likely to damage the structure, wiring or components in other film layers, so that the semiconductor device has at least the following advantages: good manufacturing process yield, competitive cost and good component performance.

[0005] An embodiment of the present invention provides a semiconductor device including a substrate, an isolation structure, a plurality of bit line structures, a plurality of word line structures, a plurality of bit line contacts, and a plurality of pads. The substrate includes cell regions and peripheral regions. The isolation structure is disposed in the cell regions of the substrate to define a plurality of active regions. Each of the active regions extends in a long axis direction. The long axis direction is a diagonal direction relative to a first horizontal direction and a second horizontal direction, wherein the first horizontal direction is perpendicular to the second horizontal direction. The bit line structures are disposed parallel to each other in the substrate and each extends in the first horizontal direction across the plurality of active regions. The word line structures are disposed parallel to each other on the substrate and each extends in the second horizontal direction. Bit line contacts are disposed on the substrate and between the word line structures, wherein the top surface of the bit line contact is lower than the top surface of the word line structure. Pads are disposed on the top surface of the bit line contacts and are electrically connected to the bit line contacts.

[0006] In some embodiments, the semiconductor device further includes an insulating layer disposed on the word line structure and surrounding the pad. The pad includes a first portion surrounded by the insulating layer and a second portion below the first portion and located on the sidewall of the word line structure. The width of the first portion gradually decreases in the direction away from the second portion.

[0007] In some embodiments, the width of the first portion is greater than the width of the second portion.

[0008] In some embodiments, the width of the second portion of the pad is approximately equal to the width of the bit line contact.

[0009] In some embodiments, the semiconductor device further includes a plurality of barrier structures, each extending in a second horizontal direction and spaced apart from each other in a first horizontal direction. Each barrier structure is a serpentine pattern and includes a plurality of curved portions disposed on the letter line structure and a plurality of straight portions connecting the plurality of curved portions. The curved portions of the barrier structure contact a pad.

[0010] In some embodiments, the semiconductor device further includes an insulating layer disposed on the word line structure and located between a plurality of pads and between a plurality of barrier structures.

[0011] In some embodiments, the pad includes a first sidewall that contacts the retaining wall structure and a second sidewall that contacts the insulating layer.

[0012] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming an isolation structure in a cell region of a substrate to define a plurality of active regions, wherein each of the active regions extends in a long axis direction, the long axis direction being a diagonal direction relative to a first horizontal direction and a second horizontal direction, the first horizontal direction being perpendicular to the second horizontal direction; forming a plurality of parallel bit line structures in the substrate, wherein each of the bit line structures extends in the first horizontal direction and crosses the plurality of active regions; forming a plurality of parallel word line structures on the substrate, wherein each of the word line structures extends in the second horizontal direction and crosses the plurality of active regions. Extending in a planar direction; forming multiple bit line contact patterns on a substrate and between multiple word line structures; forming an epitaxial pattern on the top surface of each of the bit line contact patterns by selective epitaxial growth; forming an insulating layer on the word line structures to cover the sidewalls of the epitaxial pattern; using the insulating layer as a mask, removing the epitaxial pattern and a portion of the bit line contact pattern located below the epitaxial pattern to form multiple bit line contacts and multiple openings exposing the top surface of the bit line contacts, the sidewalls of the word line structures, and the sidewalls of the insulating layer; and forming a pad electrically connected to the bit line contact in each opening.

[0013] In some embodiments, the width of the epitaxial pattern gradually decreases in a direction away from the top surface of the bit line contact pattern.

[0014] In some embodiments, the width of the epitaxial pattern at the bottom surface is greater than the width of the element contact pattern.

[0015] In some embodiments, the method of manufacturing a semiconductor device further includes: forming a plurality of barrier structures extending in a second horizontal direction and spaced apart from each other in a first horizontal direction above a word line structure before forming an epitaxial pattern. Each barrier structure is formed in a serpentine pattern and includes a plurality of curved portions disposed on the word line structure and a plurality of straight portions connecting the plurality of curved portions. After forming an insulating layer, the epitaxial pattern includes sidewalls in contact with the insulating layer and sidewalls in contact with the barrier structures.

[0016] In some embodiments, an insulating layer is formed between a plurality of pads and between a plurality of retaining structures.

[0017] In some embodiments, the pad includes a first sidewall that contacts the retaining wall structure and a second sidewall that contacts the insulating layer.

[0018] Based on the above, in the semiconductor device and manufacturing method of the present invention, an epitaxial pattern is formed on the top surface of a self-electrode contact pattern by selective epitaxial growth, and an insulating layer is used as a mask to remove the epitaxial pattern and a portion of the bit line contact pattern below it to form a bit line contact and expose an opening on the top surface of the bit line contact. This allows the pads to be well formed in the opening without omitting at least one photomask, resulting in the semiconductor device and manufacturing method having at least the following advantages: good manufacturing process yield, competitive cost, and good device performance. Attached Figure Description

[0019] Figure 1 This is a top view schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention, showing the formation of an epitaxial pattern in a cell region.

[0020] Figures 2A to 6B This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 7 This is a top view schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention, showing the formation of an epitaxial pattern in a cell region.

[0022] Figures 8A to 12B This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0023] Symbol Explanation

[0024] 10: Isolation Structure

[0025] 12: Source / Drain

[0026] 14: Gate Structure

[0027] 16: Dielectric layer

[0028] 18: Insulation Pattern

[0029] 22: Silicide layer

[0030] 30: Source / Drain Contacts

[0031] 32: Barrier Layer

[0032] 34: Conductive layer

[0033] 100: Base

[0034] 110: Isolation Structure

[0035] 112: Bitline Structure

[0036] 120: Character Line Structure

[0037] 125: Insulation Pattern

[0038] 130: Pattern of contact element

[0039] 132: Position line contact element

[0040] 135: Retaining Wall Structure

[0041] 140, 142: Extension patterns

[0042] 150: Insulation layer

[0043] 160: Silicide layer

[0044] 170: Connecting pad

[0045] 172: Barrier Layer

[0046] 174: Conductive layer

[0047] 1000, 2000: Semiconductor devices

[0048] AA: Active Zone

[0049] CR: Cellular region

[0050] D1: First Direction

[0051] D2: Second Direction

[0052] OP1, OP11, OP2: Openings

[0053] PR: Surrounding Area Detailed Implementation

[0054] The invention is described more fully with reference to the accompanying drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0055] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be intermediate elements present. If an element is referred to as being "directly on" or "directly connected" to another element, there are no intermediate elements present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may refer to the presence of other elements between two elements. As used herein, "electrical connection" may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0056] As used herein, “about,” “approximately,” or “substantially” includes the value mentioned and the average value within an acceptable range of deviations that can be determined by one of ordinary skill in the art, taking into account the measurement under discussion and the specific amount of error associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties, and a single standard deviation may not be applicable to all properties.

[0057] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.

[0058] Figure 1 This is a top view schematic diagram of a semiconductor device manufacturing method according to an embodiment of the present invention, showing the formation of an epitaxial pattern in a cell region. Figures 2A to 6B This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2A (a) in the middle is Figure 1 A schematic diagram of the cross section taken along section line A-A'. Figure 2A (b) in the middle is Figure 1 A schematic diagram of the cross-section taken along section line B-B'. Figure 2B In the manufacturing method of semiconductor devices and Figure 2A The diagram shows the surrounding region corresponding to the cell region. Figure 1 The section line A-A' in the diagram extends, for example, in the first direction D1 and lies between the two bit line structures 112. Figure 1The section line B-B' in the diagram extends, for example, along the extension direction of the active region AA (as described later along the major axis) and passes through the active region AA. For ease of explanation, Figure 1 Some components (such as insulating pattern 125, etc.) are omitted from the drawing, and Figure 1 The section lines A-A' and B-B' shown are merely examples; the actual cross-sectional structure is based on... Figure 2A , Figure 3A , Figure 4A , Figure 5A and Figure 6A (a) and (b) shown are the main ones.

[0059] Please refer to Figure 1 and Figure 2A In some embodiments, semiconductor devices (e.g. Figure 6A and Figure 6B The manufacturing method of the semiconductor device 1000 shown may include the following steps.

[0060] First, an isolation structure 110 is formed in the cell region CR of the substrate 100 to define a plurality of active regions AA. In some embodiments, each of the active regions AA may extend in the long axis direction. For example, the active region AA may be, for instance, a strip pattern extending in the long axis direction. In some embodiments, the long axis direction may be a diagonal direction relative to a first horizontal direction D1 and a second horizontal direction D2. In some embodiments, the first horizontal direction D1 may be perpendicular to the second horizontal direction D2.

[0061] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, etc. Alternatively, the substrate 100 may be a doped semiconductor substrate (e.g., with P-type or N-type dopants) or an undoped semiconductor substrate, but the invention is not limited thereto.

[0062] The isolation structure 110 may be, for example, a shallow trench isolation (STI) structure, but is not limited thereto. In some embodiments, the isolation structure 10 may also be formed in the peripheral region PR of the substrate 100 to define multiple logical active regions. The logical active regions may be regions where logic elements are subsequently formed. For example, such as... Figure 2B The gate structure 14 and source / drain 12 of the logic element shown can be formed in the logic active region.

[0063] Next, a plurality of parallel bit line structures 112 are formed in the substrate 100. In some embodiments, each of the bit line structures 112 may extend in a first horizontal direction D1 and cross a plurality of active regions AA. In some embodiments, the bit line structure 112 may be formed via the following steps: First, a bit line trench (not shown) is formed in the substrate 100. Next, a dielectric layer (not shown) is formed on the side surface and bottom surface of the bit line trench. Then, a bit line (not shown) disposed on the dielectric layer is formed in the bit line trench. The bit line may be a single-layer structure or a multi-layer structure. The bit line may include a conductive material. For example, the bit line may include doped polysilicon, a metallic material (e.g., tungsten), a conductive metal nitride (e.g., WN, TiSiN, WSiN, TiN, or TaN), or a combination thereof.

[0064] Then, a plurality of word line structures 120 parallel to each other are formed on the substrate 100. In some embodiments, each of the word line structures 120 may extend in a second horizontal direction D2. In some embodiments, the word line structure 120 may include word lines (not shown), a capping layer (not shown) formed on the top surface of the word lines, and spacers (not shown) formed on the sidewalls of the word lines and the sidewalls of the capping layer. The word lines may be single-layer or multi-layer structures. The word lines WL may include conductive materials. For example, the word lines may include doped polysilicon, metallic materials (e.g., tungsten), conductive metal nitrides (e.g., WN, TiSiN, WSiN, TiN, or TaN), or combinations thereof. The capping layer may include an insulating material (e.g., silicon nitride). The spacers may be single-layer or multi-layer structures. The spacers may include insulating materials (e.g., oxides, nitrides, or combinations thereof).

[0065] Then, bit line contact patterns 130 are formed on the substrate 100 and between the word line structures 120. The material of the bit line contact pattern 130 may be polysilicon. In some embodiments, the method of forming the bit line contact pattern 130 may include the following steps. First, an insulating layer (not shown) covering the sidewalls of the word line structures 120 is formed in the space between the substrate 100 and the word line structures 120. Next, the insulating layer is patterned to form an opening (not shown) exposing the substrate 100. Then, a conductive material (e.g., polysilicon) is filled into the opening to form the bit line contact pattern 130. In some embodiments, the bit line contact pattern 130 may be disposed between the word line structures 120 and between the insulating patterns 125 formed after the insulating layer is patterned. From a top view, the bit line contact pattern 130 may be configured between the word line structures 120 and between the bit line structures 112. In some embodiments, a portion of the insulating pattern 125 may be considered as part of the word line structure 120, such as part of the spacers of the word line structure 120, but the invention is not limited thereto.

[0066] Subsequently, epitaxial patterns 140 spaced apart from each other are formed on the top surface of each of the bit line contact patterns 130 by selective epitaxial growth. In some embodiments, the width of the epitaxial patterns 140 gradually decreases in the direction away from the top surface of the bit line contact pattern 130. In other words, the spacing between the epitaxial patterns 140 gradually increases in the direction away from the top surface of the bit line contact pattern 130. In some embodiments, the width of the epitaxial patterns 140 at the bottom surface is greater than the width of the bit line contact pattern 130. That is, the epitaxial patterns 140 are formed on the top surface of the bit line contact pattern 130, the top surface of the partial insulating pattern 125, and the top surface of the partial word line structure 120.

[0067] Please refer to Figure 2B An isolation structure 10 and a source / drain 12 may be formed in the peripheral region PR of the substrate 100, while a gate structure 14, a dielectric layer 16, and an insulating pattern 18 may be formed on the peripheral region PR of the substrate 100. The isolation structure 10, the source / drain 12, the gate structure 14, the dielectric layer 16, and the insulating pattern 18 may be formed simultaneously by some of the above-described fabrication processes or by other fabrication processes, and the present invention is not limited thereto. The source / drain 12 may be doped with P-type dopant or N-type dopant, but is not limited thereto. In some embodiments, the gate structure 14 may include a gate (not shown) formed on the logic active region of the substrate 100, a gate dielectric layer (not shown) formed between the gate and the substrate 100, and gap walls formed on opposite sidewalls of the gate and extending toward the substrate 100 to cover opposite sidewalls of the gate dielectric layer. The gate may include common gate materials such as polysilicon or metal. The gate dielectric layer may include common gate dielectric materials such as silicon dioxide or high-k dielectric materials. The spacer walls may include common spacer wall materials such as silicon oxide. The dielectric layer 16 may include common dielectric materials such as silicon dioxide. The insulating pattern 18 may include common insulating materials such as oxides or nitrides.

[0068] Please refer to Figure 2A and Figure 3A An insulating material layer (not shown) is formed on the word line structure 120 and the insulating pattern 125 to cover the sidewalls of the epitaxial pattern 140. In some embodiments, the insulating material layer may cover the sidewalls and top surface of the epitaxial pattern 140. Next, a planarization process is performed on the insulating material layer and the epitaxial pattern 140 to form the epitaxial pattern 142 and the insulating layer 150. In some embodiments, chemical-mechanical polishing (CMP) may be used for the planarization process. The material of the insulating layer 150 may be, for example, silicon nitride. Please refer to... Figure 2B and Figure 3BThe insulating layer 150 is also formed on the dielectric layer 16 in the peripheral region PR and covers the insulating pattern 18.

[0069] Please refer to Figure 3A and Figure 4A Using the insulating layer 150 as a mask, the exposed epitaxial pattern 142 and a portion of the bit line contact pattern 130 located below the epitaxial pattern 142 are removed to form a plurality of bit line contacts 132 and a plurality of openings OP1 exposing the top surface of the bit line contacts 132, the sidewalls of the word line structure 120, the sidewalls of the insulating layer 150, and the sidewalls of the insulating pattern 125. The top surface of the bit line contacts 132 is lower than the top surface of the word line structure 120. In some embodiments, an etch-back method may be used to remove the epitaxial pattern 142 and a portion of the bit line contact pattern 130 located below the epitaxial pattern 142.

[0070] Please refer to Figure 3B and Figure 4B The insulating layer 150 can act as a mask in the peripheral region PR to prevent the underlying film layer from being affected by the manufacturing process of removing the epitaxial pattern 142 and part of the bit line contact pattern 130.

[0071] Please refer to Figure 4A and Figure 4B as well as Figure 5A and Figure 5B Multiple openings OP2 are formed in the insulating layer 150, the insulating pattern 18, and the dielectric layer 16 in the peripheral region PR to expose the source / drain 12.

[0072] Please refer to Figure 5A and Figure 5B as well as Figure 6A and Figure 6B A silicide layer 160 and a silicide layer 22 are formed on the surfaces of the bit line contact 132 and the source / drain electrode 12 exposed by openings OP1 and OP2, respectively. The silicide layer 160 and the silicide layer 22 may include cobalt silicide (CoSi). x Nickel silicide (NiSi) x ) or manganese silicide (MnSi) x Next, pads 170 and source / drain contacts 30, which are electrically connected to bit line contacts 132 and source / drain contacts 12, are formed on silicide layer 160 in opening OP1 and on silicide layer 22 in opening OP2, respectively.

[0073] In some embodiments, an insulating layer 150 may be disposed on the word line structure 120 and surround the pad 170. The pad 170 may include a first portion surrounded by the insulating layer 150 and a second portion below the first portion and located on a sidewall of the word line structure 120. In some embodiments, the width of the first portion of the pad 170 gradually decreases in a direction away from the second portion of the pad 170. In some embodiments, the width of the first portion of the pad 170 is greater than the width of the second portion of the pad 170. In some embodiments, the width of the second portion of the pad 170 is approximately equal to the width of the bit line contact 132.

[0074] In some embodiments, such as Figure 6A As shown, the pad 170 may include a barrier layer 172 and a conductive layer 174. The barrier layer 172 may be formed on the sidewalls and bottom surface of the opening OP1. The conductive layer 174 may be formed on the barrier layer 172 and fill the opening OP1. The barrier layer 172 may include common barrier layer materials such as Ti, TiN, Ta, or TaN. The conductive layer 174 may include common conductive materials such as tungsten.

[0075] In some embodiments, such as Figure 6B As shown, the source / drain contact 30 may include a barrier layer 32 and a conductive layer 34. The barrier layer 32 may be formed on the sidewalls and bottom surface of the opening OP2. The conductive layer 34 may be formed on the barrier layer 32 and fill the opening OP2. The barrier layer 32 may include common barrier layer materials such as Ti, TiN, Ta, or TaN. The conductive layer 34 may include common conductive materials such as tungsten.

[0076] In some embodiments, when the semiconductor device 1000 is a DRAM, the pad 170 may serve as a memory pad for the DRAM to electrically connect a memory node (not shown) subsequently formed thereon to the bit line contact 132.

[0077] Based on the above, the semiconductor device 1000 can selectively epitaxially grow an epitaxial pattern 140 on the top surface of the bit line contact pattern 130, and use an insulating layer 150 as a mask to remove the epitaxial pattern 140 and a portion of the bit line contact pattern 130 below it to form a bit line contact 132 and an opening OP1 that exposes the top surface of the bit line contact 132. This eliminates the need for two photomasks conventionally used to form storage pads and allows the pad 170 to be well formed in the opening OP1.

[0078] Figure 7 This is a top view schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention, showing the formation of an epitaxial pattern in a cell region. Figures 8A to 12B This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention. Figure 8A (a) in the middle is Figure 7 A schematic diagram of the cross section taken along section line A-A'. Figure 8A (b) in the middle is Figure 7 A schematic diagram of the cross-section taken along section line B-B'. Figure 8B In the manufacturing method of semiconductor devices and Figure 8A The diagram shows the surrounding region corresponding to the cell region. Figure 7 The section line A-A' in the diagram extends, for example, in the first direction D1 and lies between the two bit line structures 112. Figure 7 The section line B-B' in the diagram extends, for example, along the extension direction of the active region AA (as described later along the major axis) and passes through the active region AA. For ease of explanation, Figure 7 Some components (such as insulating pattern 125, etc.) are omitted from the drawing, and Figure 7 The section lines A-A' and B-B' shown are merely examples; the actual cross-sectional structure is based on... Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A (a) and (b) shown are the main ones.

[0079] Semiconductor devices (e.g.) Figure 12A and Figure 12B The manufacturing method of the semiconductor device 2000 shown may include the following steps. In the manufacturing method of the semiconductor device 2000, the materials, structures and / or relative positions of components that are the same as or similar to those of the semiconductor device 1000 are indicated by the same or similar component designations, which will not be repeated here.

[0080] Please refer to Figure 7 and Figure 8A After forming the bit line contact pattern 130, a plurality of barrier structures 135 extending in the second horizontal direction D2 and spaced apart from each other in the first horizontal direction D1 are formed above the word line structure 120. In some embodiments, each barrier structure 135 may be formed in a serpentine pattern and may include a plurality of curved portions disposed on the word line structure 120 and a plurality of straight portions connecting the plurality of curved portions.

[0081] Next, an epitaxial pattern 140 is formed on the top surface of each of the self-aligning contact patterns 130 by selective epitaxial growth. The epitaxial patterns 140 are spaced apart by a barrier structure 135, thus preventing the epitaxial patterns 140 from contacting each other and causing short circuits due to contact between the pads 170 formed in subsequent fabrication processes. In some embodiments, the epitaxial pattern 140 may be formed on the sidewall of a curved portion of the barrier structure 135. In some embodiments, the epitaxial pattern 140 may be grown from the sidewall of the curved portion of the barrier structure 135 in a direction away from that sidewall to form a shape such that… Figure 7Shapes as shown (e.g., teardrop shape). In some embodiments, such as Figure 7 As shown, the extension pattern 140 is located on the sidewall of the retaining wall structure 135 on the same side in the first direction D1 (e.g., extension patterns 140 in the same row). In some embodiments, such as Figure 7 As shown, the extensional patterns 140 are alternately located on opposite sidewalls of the retaining wall structure 135 in the second direction D2 (e.g., extensional patterns 140 in the same column).

[0082] Please refer to Figure 8B An isolation structure 10 and a source / drain electrode 12 may be formed in the peripheral region PR of the substrate 100, while a gate structure 14, a dielectric layer 16, and an insulating pattern 18 may be formed on the peripheral region PR of the substrate 100. The isolation structure 10, the source / drain electrode 12, the gate structure 14, the dielectric layer 16, and the insulating pattern 18 may be formed simultaneously through some of the above-described fabrication processes or through other fabrication processes, and the present invention is not limited thereto.

[0083] Please refer to Figure 8A and Figure 9A An insulating material layer (not shown) is formed on the character line structure 120 and the insulating pattern 125 to cover the sidewalls of the epitaxial pattern 140. In some embodiments, the insulating material layer may cover the sidewalls and top surface of the epitaxial pattern 140. Next, a planarization process (e.g., CMP) is performed on the insulating material layer and the epitaxial pattern 140 to form the epitaxial pattern 142 and the insulating layer 150. In some embodiments, the epitaxial pattern 140 may include sidewalls contacting the insulating layer 150 and sidewalls contacting the barrier structure 135. In some embodiments, the top surfaces of the barrier structure 135, the epitaxial pattern 142, and the insulating layer 150 are coplanar. Please refer to... Figure 8B and Figure 9B The insulating layer 150 is also formed on the dielectric layer 16 in the peripheral region PR and covers the insulating pattern 18.

[0084] Please refer to Figure 9A and Figure 10A Using the insulating layer 150 as a mask, the exposed epitaxial pattern 142 and a portion of the bit line contact pattern 130 located below the epitaxial pattern 142 are removed to form a plurality of bit line contacts 132 and a plurality of openings OP11 exposing the top surface of the bit line contacts 132, the sidewalls of the word line structure 120, the sidewalls of the insulating layer 150, and the sidewalls of the insulating pattern 125. The top surface of the bit line contacts 132 is lower than the top surface of the word line structure 120. In some embodiments, an etch-back method may be used to remove the epitaxial pattern 142 and a portion of the bit line contact pattern 130 located below the epitaxial pattern 142.

[0085] Please refer to Figure 9B and Figure 10B The insulating layer 150 can act as a mask in the peripheral region PR to prevent the underlying film layer from being affected by the manufacturing process of removing the epitaxial pattern 142 and part of the bit line contact pattern 130.

[0086] Please refer to Figure 10A and Figure 10B as well as Figure 11A and Figure 11B Multiple openings OP2 are formed in the insulating layer 150, the insulating pattern 18, and the dielectric layer 16 in the peripheral region PR to expose the source / drain 12.

[0087] Please refer to Figure 11A and Figure 11B as well as Figure 12A and Figure 12B A silicide layer 160 and a silicide layer 22 are formed on the surfaces of the bit line contact 132 and the source / drain electrode 12 exposed by openings OP11 and OP2, respectively. Next, a pad 170 and a source / drain contact 30, electrically connected to the bit line contact 132 and the source / drain electrode 12, are formed on the silicide layer 160 of opening OP11 and the silicide layer 22 of opening OP2, respectively. In some embodiments, the curved portion of the barrier structure 135 may contact the pad 170.

[0088] In some embodiments, an insulating layer 150 may be formed between pads 170 and between a plurality of barrier structures 135. In some embodiments, pads 170 may include a first sidewall contacting a barrier structure 135 and a second sidewall contacting the insulating layer 150. Pads 170 may include a second portion surrounded by word line structures 120 and a first portion above the second portion. In some embodiments, the width of the first portion of pad 170 gradually decreases in a direction away from the second portion of pad 170. In some embodiments, the width of the first portion of pad 170 is greater than the width of the second portion of pad 170. In some embodiments, the width of the second portion of pad 170 is approximately equal to the width of the bit line contact 132.

[0089] In some embodiments, such as Figure 12A As shown, the pad 170 may include a barrier layer 172 and a conductive layer 174. The barrier layer 172 may be formed on the sidewalls and bottom surface of the opening OP11. The conductive layer 174 may be formed on the barrier layer 172 and fill the opening OP11.

[0090] In some embodiments, such as Figure 12B As shown, the source / drain contact 30 may include a barrier layer 32 and a conductive layer 34. The barrier layer 32 may be formed on the sidewalls and bottom surface of the opening OP2. The conductive layer 34 may be formed on the barrier layer 32 and fill the opening OP2.

[0091] In some embodiments, when the semiconductor device 2000 is a DRAM, the pad 170 may serve as a memory pad for the DRAM to electrically connect a memory node (not shown) subsequently formed thereon to the bit line contact 132.

[0092] Based on the above, the semiconductor device 2000 can selectively epitaxially grow an epitaxial pattern 140 on the top surface of the bit line contact pattern 130, and use an insulating layer 150 as a mask to remove the epitaxial pattern 140 and a portion of the bit line contact pattern 130 below it to form a bit line contact 132 and an opening OP11 exposing the top surface of the bit line contact 132. This eliminates the need for a photomask and allows the pads 170 to be well formed in the opening OP11, resulting in the semiconductor device 2000 having good fabrication yield, manufacturing cost, and device performance. On the other hand, before forming the epitaxial pattern 140, the above embodiment uses a barrier structure 135 to prevent the epitaxial patterns 140 formed by selective epitaxial growth from contacting each other, so that the subsequently formed pads 170 will not contact each other and cause a short circuit.

[0093] In summary, in the semiconductor device and manufacturing method of the present invention, an epitaxial pattern is formed on the top surface of a self-electrode contact pattern by selective epitaxial growth, and an insulating layer is used as a mask to remove the epitaxial pattern and a portion of the bit line contact pattern below it to form a bit line contact and expose an opening on the top surface of the bit line contact. This allows the pads to be well formed in the opening without omitting at least one photomask, resulting in the semiconductor device and manufacturing method having at least the following advantages: good process yield, competitive cost, and good device performance.

Claims

1. A semiconductor device, comprising: The basement includes the cell region and the peripheral region; An isolation structure is disposed in the cell region of the substrate to define a plurality of active regions, wherein each of the plurality of active regions extends in a long axis direction, the long axis direction being a diagonal direction relative to a first horizontal direction and a second horizontal direction, the first horizontal direction being perpendicular to the second horizontal direction; Multiple bitline structures are arranged parallel to each other in the substrate, and each extends in the first horizontal direction and crosses multiple active regions; Multiple character line structures are arranged parallel to each other on the base, and each extends in the second horizontal direction; Multiple bit line contacts are disposed on the substrate and between the multiple word line structures, wherein the top surface of the bit line contacts is lower than the top surface of the word line structures; as well as Multiple pads are respectively disposed on the top surface of the multiple bit line contacts and electrically connected to the bit line contacts.

2. The semiconductor device of claim 1, further comprising: An insulating layer is disposed on the plurality of the word line structures and surrounds the plurality of the contact pads. The pad includes a first portion surrounded by the insulating layer and a second portion below the first portion and located on the sidewall of the letter line structure. The width of the first portion gradually decreases in the direction away from the second portion.

3. The semiconductor device of claim 2, wherein the width of the first portion is greater than the width of the second portion.

4. The semiconductor device of claim 2, wherein the width of the second portion of the pad is equal to the width of the bit line contact.

5. The semiconductor device of claim 1, further comprising: Multiple retaining wall structures, each extending in the second horizontal direction and spaced apart from each other in the first horizontal direction, wherein each retaining wall structure is a serpentine pattern and includes multiple curved portions disposed on the letter line structure and multiple straight portions connecting the multiple curved portions. The curved portion of the retaining wall structure contacts the pad.

6. The semiconductor device of claim 5, further comprising: An insulating layer is disposed on the plurality of the letter line structures and located between the plurality of the pads and between the plurality of the retaining wall structures.

7. The semiconductor device of claim 6, wherein the pad includes a first sidewall in contact with the barrier structure and a second sidewall in contact with the insulating layer.

8. A method for manufacturing a semiconductor device, comprising: An isolation structure is formed in the cell region of the substrate to define a plurality of active regions, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction relative to a first horizontal direction and a second horizontal direction, the first horizontal direction being perpendicular to the second horizontal direction; A plurality of bit line structures are formed in the substrate, each of which extends in the first horizontal direction and crosses the plurality of active regions. A plurality of parallel character line structures are formed on the substrate, each of which extends in the second horizontal direction; Multiple bit line contact patterns are formed on the substrate and between the multiple word line structures; An epitaxial pattern is formed on the top surface of each of the plurality of bit line contact patterns by selective epitaxial growth. An insulating layer is formed on the plurality of the word line structures to cover the sidewalls of the epitaxial pattern; Using the insulating layer as a mask, the epitaxial pattern and a portion of the bit line contact pattern located below the epitaxial pattern are removed to form a plurality of bit line contacts and expose the top surface of the bit line contacts, the sidewalls of the word line structure, and a plurality of openings on the sidewalls of the insulating layer. as well as A pad electrically connected to the bit line contact is formed in each of the openings.

9. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the width of the epitaxial pattern gradually decreases in a direction away from the top surface of the bit line contact pattern.

10. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the width of the epitaxial pattern at the bottom surface is greater than the width of the bit line contact pattern.

11. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: Before forming the extended pattern, a plurality of barrier structures extending in the second horizontal direction and spaced apart from each other in the first horizontal direction are formed above the letter line structure, wherein each barrier structure is formed in a serpentine pattern and includes a plurality of curved portions disposed on the letter line structure and a plurality of straight portions connecting the plurality of curved portions, and After the insulating layer is formed, the epitaxial pattern includes the sidewalls that contact the insulating layer and the sidewalls that contact the retaining wall structure.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein the insulating layer is formed between the plurality of said pads and between the plurality of said barrier structures.

13. The method of manufacturing a semiconductor device as claimed in claim 11, wherein the pad includes a first sidewall in contact with the barrier structure and a second sidewall in contact with the insulating layer.

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