Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a storage node pad, a capacitor structure and a support structure. The storage node pad is arranged on the substrate. The capacitor structure is arranged on the storage node pad and comprises a plurality of capacitors. The capacitors comprise, from bottom to top, a bottom electrode layer, a capacitor dielectric layer and a top electrode layer. The top of the bottom electrode layer has a groove. The support structure comprises, from bottom to top, a plurality of first support layers and a plurality of second support layers. The support structure connects two adjacent capacitors. The groove is respectively directed to each second support layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor memory device and a manufacturing method thereof. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, so it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend.

[0003] Generally, the dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from the word line (WL) and the bit line (BL). In response to product demand, the density of memory cells in the array region must continue to increase, causing the difficulty and complexity of related manufacturing processes and designs to increase. Therefore, the existing technology or structure still needs to be further improved to effectively improve the performance and reliability of the related storage device.

[0004] Therefore, the present application provides a semiconductor device and a manufacturing method thereof to solve the above problems. SUMMARY

[0005] To achieve the above purpose, one embodiment of the present application provides a semiconductor device, at least part of the bottom electrode layer of which is additionally provided with a groove with a notch facing the second support layer, so as to additionally separate the distance between the bottom electrode layers, which is beneficial to form a capacitor dielectric layer and a top electrode layer with more optimized structure. Therefore, the semiconductor device can improve the structural reliability of the storage node, and further optimize its function and performance.

[0006] To achieve the above purpose, one embodiment of the present application provides a manufacturing method of a semiconductor device, which locally reduces the thickness of the top of the bottom electrode layer by lateral etching in the etching manufacturing process, so as to additionally form a groove with a notch facing the second support layer on the bottom electrode layer. In this way, the manufacturing process of the subsequent capacitor dielectric layer and the top electrode layer can be optimized. Therefore, the manufacturing method of the semiconductor device of the present application can form a storage node with structural reliability and device performance even under the premise of continuously increasing the density of memory cells.

[0007] A semiconductor device according to one embodiment of the present invention includes a substrate, memory node pads, a capacitor structure, and a support structure. The memory node pads are disposed on the substrate. The capacitor structure is disposed on the memory node pads and includes multiple capacitors. Each capacitor includes, from bottom to top, a bottom electrode layer, a dielectric layer, and a top electrode layer. The top of the bottom electrode layer has a groove. The support structure includes, from bottom to top, multiple first support layers and multiple second support layers, connecting two adjacent capacitors, wherein the grooves face each of the second support layers.

[0008] A method for fabricating a semiconductor device according to an embodiment of the present invention includes the following steps. First, a substrate is provided, and a plurality of memory node pads are formed on the substrate. Next, a capacitor structure is formed on the memory node pads, the capacitor structure including a plurality of capacitors, each capacitor including a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, the top of the bottom electrode layer having a groove. Then, a support structure is formed to connect two adjacent capacitors, the support structure including a first support layer and a second support layer from bottom to top, wherein the groove faces each of the second support layers. Attached Figure Description

[0009] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0010] Figures 1 to 7 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a first embodiment of the present invention is provided, wherein:

[0011] Figure 1 This is a schematic cross-sectional view of the semiconductor device of the present invention after the support layer structure has been formed;

[0012] Figure 2 This is a schematic cross-sectional view of the semiconductor device of the present invention after the electrode material layer has been formed;

[0013] Figure 3 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the first etching process.

[0014] Figure 4 This is a schematic cross-sectional view of the semiconductor device of the present invention after the bottom electrode layer has been formed;

[0015] Figure 5 This is a schematic cross-sectional view of the semiconductor device of the present invention after etching the support layer structure;

[0016] Figure 6 This is a schematic cross-sectional view of the semiconductor device of the present invention after the third support material layer and the first support material layer have been completely removed; and

[0017] Figure 7 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after capacitor formation.

[0018] Figures 8 to 9 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a second embodiment of the present invention is provided, wherein:

[0019] Figure 8 This is a schematic cross-sectional view of the semiconductor device of the present invention after the bottom electrode layer has been formed; and

[0020] Figure 9 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after capacitor formation.

[0021] Figures 10 to 11 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a third embodiment of the present invention is provided, wherein:

[0022] Figure 10 This is a schematic cross-sectional view of the semiconductor device of the present invention after the third support material layer and the first support material layer have been completely removed; and

[0023] Figure 11 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after capacitor formation.

[0024] Figure 12 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to a fourth embodiment of the present invention is shown.

[0025] The reference numerals in the attached figures are explained as follows:

[0026] 100, 300, 400, 500 semiconductor devices

[0027] 101 Insulation Zone

[0028] 110 substrate

[0029] 130 insulation layer

[0030] 131 oxide layer

[0031] 133 Nitride Layer

[0032] 135 oxide layer

[0033] 140 gap wall structure

[0034] 141 First gap wall

[0035] 143 Second gap wall

[0036] 145 Third gap wall

[0037] 150 contacts

[0038] 160-bit line

[0039] 160a bit line contact

[0040] 161 semiconductor layer

[0041] 163 Barrier Layer

[0042] 165 conductive layer

[0043] 167 cap layer

[0044] 170 dielectric layer

[0045] 180 storage node pads

[0046] 190 Support Layer Structure

[0047] 191 First Support Material Layer

[0048] 192 through hole

[0049] 193 Second Support Material Layer

[0050] 195 Third Support Material Layer

[0051] 197 Fourth Support Material Layer

[0052] 200 electrode material layers

[0053] 210 Initial Bottom Electrode Layer

[0054] 211, 411 Part 1

[0055] Part Two of 213, 313, and 513

[0056] 215, 315, 515 inclined surfaces

[0057] 217, 317 grooves

[0058] 220 mask pattern

[0059] 230, 232, 332, 430, 432 bottom electrode layers

[0060] 234 capacitor dielectric layer

[0061] 236 top electrode layer

[0062] 240, 440 support structure

[0063] 241 First Support Layer

[0064] 243, 443 Second Support Layer

[0065] 250, 350, 450 capacitor structures

[0066] T1 First Thickness

[0067] T2 second thickness

[0068] P1 First Etching Process

[0069] P2, P5 Second Etching Process

[0070] P21 and P51 vertical downward etching process

[0071] Lateral etching processes for P22 and P52

[0072] P3 Third Etching Process

[0073] P4, P6 Fourth Etching Process Detailed Implementation

[0074] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0075] Please refer to Figures 1 to 7 The illustration shows the steps of a method for manufacturing a semiconductor device 100 according to the first embodiment of the present invention. First, as... Figure 1 As shown, a substrate 110 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. At least one insulating region 101, such as a shallow trench isolation (STI), is formed within the substrate 110. Multiple active areas (AA, not shown) are defined on the substrate 110. In one embodiment, the insulating region 101 is formed, for example, by first forming multiple trenches (not shown) in the substrate 110 using an etching process, and then filling the trenches with an insulating material (e.g., silicon oxide or silicon oxynitride, etc.), but this is not a limitation.

[0076] Furthermore, multiple buried gates (not shown) are further formed within the substrate 110. These buried gates extend parallel to each other along a direction (e.g., the x-direction, not shown) and intersect with the active region, serving as buried word lines (BWLs, not shown) of the semiconductor device 100. Multiple bit lines 160 and multiple contacts 150 may be formed above the substrate 110. Each bit line 160 extends parallel to each other along another direction perpendicular to the aforementioned direction (e.g., the y-direction, not shown), alternating with each contact 150 in that direction. Although the overall extension direction of the active region, the buried gates, and the bit lines 160 is not specifically shown in the accompanying drawings of this embodiment, those skilled in the art will readily understand that, viewed from a top view, the bit lines 160 should be perpendicular to the buried gates and intersect with both the active region and the buried gates.

[0077] Specifically, each bit line 160 is formed on the substrate 110 in a spaced manner and includes, but is not limited to, a semiconductor layer (e.g., polysilicon) 161, a barrier layer 163 (e.g., titanium and / or titanium nitride), a conductive layer 165 (e.g., a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 167 (e.g., silicon oxide, silicon nitride, or silicon oxynitride). It should be noted that, in principle, all bit lines 160 are parallel to each other on an insulating layer 130 above the substrate 110. The insulating layer 130 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure, but is not limited to this. In addition, each bit line 160 extends and crosses multiple active regions, wherein the bit line 160 that crosses each active region can further extend into each active region by means of a bit line contact (BLC) 160a formed below it.

[0078] It should also be noted that the bit line contact 160a is integrally formed with the semiconductor layer 161 of the bit line 160 and directly contacts the underlying substrate 110 (i.e., the active region). On the other hand, each contact 150 is also formed on the substrate 110 in a mutually spaced manner and extends further into each of the active regions. Thus, each contact 150 can serve as a storage node contact (SNC) of the semiconductor device 100, directly contacting the underlying substrate 110 (including the active region and the insulating region 101). In one embodiment, the contact 150 is made of a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and each contact 150 is insulated from each bit line 160 by a spacer structure 140. In one embodiment, the spacer structure 140 may selectively have a single-layer structure or a structure such as... Figure 1 The composite layer structure shown may include, for example, a first spacer wall 141 (e.g., including silicon nitride), a second spacer wall 143 (e.g., including silicon oxide), and a third spacer wall 145 (e.g., including silicon nitride) stacked sequentially on the sidewalls of each line 160, but is not limited thereto.

[0079] Please refer to again Figure 1 As shown, a plurality of storage node pads (SN pads) 180 are formed within the dielectric layer 170 on the substrate 110, positioned above the contacts 150 and bit lines 160 and respectively aligned with each contact 150. In one embodiment, the storage node pads 180 also include a low-resistance metal material such as aluminum, titanium, copper, or tungsten, for example, a metal material different from that of the contacts 150, but not limited thereto. In another embodiment, the storage node pads 180 may also be integrally formed with the contacts 150 and may include the same material. Subsequently, a capacitor structure 250 may be formed above the storage node pads 180 to directly contact and electrically connect to the storage node pads 180 below.

[0080] In one embodiment, the fabrication process of the capacitor structure 250 includes, but is not limited to, the following steps. First, a support layer structure 190 is formed on the dielectric layer 170 above the substrate 110, for example, comprising at least one oxide material layer and at least one nitride material layer alternately stacked. In this embodiment, the support layer structure 190 includes, for example, a first support material layer 191 (e.g., silicon oxide), a second support material layer 193 (e.g., silicon nitride or silicon carbonitride), a third support material layer 195 (e.g., silicon oxide), and a fourth support material layer 197 (e.g., silicon nitride or silicon carbonitride, etc., but not limited thereto) stacked sequentially from bottom to top. Preferably, the oxide material layer (e.g., including the first support material layer 191 and the third support material layer 195) may have a relatively large thickness, for example, about 5 to 10 times or more the thickness of the nitride material layer (e.g., including the second support material layer 193 or the fourth support material layer 197). Furthermore, the thickness of the nitride material layer (e.g., including the fourth support material layer 197) disposed away from the substrate 110 is preferably greater than the thickness of the nitride material layer (e.g., including the second support material layer 193) disposed adjacent to the substrate 110. Figure 1 As shown, but not limited to. Thus, the overall thickness of the support layer structure 190 can reach approximately 1600 to 2000 angstroms, but not limited to.

[0081] Those skilled in the art will understand that the specific stacking number of the aforementioned oxide material layers (such as the first support material layer 191 or the third support material layer 195) and the aforementioned nitride material layers (such as the second support material layer 193 or the fourth support material layer 197) is not limited to the aforementioned number, but can be adjusted according to actual needs, such as 3 layers, 4 layers, or other numbers. Then, a plurality of through holes 192 are formed in the support layer structure 190, sequentially penetrating the fourth support material layer 197, the third support material layer 195, the second support material layer 193, and the first support material layer 191, and aligning with the underlying memory node pads 180. In this way, the top surface of each memory node pad 180 can be exposed from each of the aforementioned through holes 192, such as... Figure 1 As shown.

[0082] Next, as Figure 2 As shown, an electrode material layer 200 is formed by deposition on the substrate 110. In detail, the electrode material layer 200 is conformally formed on the support layer structure 190, for example, covering the top surface of the fourth support material layer 197, the surface of each via 192, and the top surface of each memory node pad 180. The electrode material layer 200 may include, for example, a low-resistivity metal such as aluminum, titanium, copper, or tungsten, but is not limited thereto.

[0083] Then, as Figure 3As shown, a first etching process P1 is performed, such as a dry etching process, to remove the electrode material layer 200 covering the top surface of the fourth support material layer 197, forming multiple initial bottom electrode layers 210. Each initial bottom electrode layer 210 is formed within a via 192 and uniformly covers the top surface of each memory node pad 180 and the surface of each via 192, thus having a uniform first thickness T1. Furthermore, each initial bottom electrode layer 210 simultaneously covers two opposite sidewalls of each via 192, thus having two upwardly extending first portions 211 of equal height in the direction perpendicular to the substrate 110. The top surface of each first portion 211 is, for example, coplanar with the top surface of the fourth support material layer 197. Thus, each initial bottom electrode layer 210 can have a bilaterally symmetrical structure, for example, as shown below. Figure 3 The U-shaped structure shown is not limited to this.

[0084] like Figure 4 As shown, multiple mask patterns 220 are formed on the support layer structure 190, covering a portion of the fourth support material layer 197 and a portion of the through-holes 192. A second etching process P2 is performed through the mask patterns 220, for example, another dry etching process. Specifically, each mask pattern 220 is sequentially formed on the support layer structure 190 such that it simultaneously covers any through-hole 192 and the support layer structure 190 on both sides of it, exposing the two adjacent through-holes 192 on the left and right sides of any through-hole 192. This allows the remaining portion of the fourth support material layer 197 to be exposed from the mask patterns 220 and removed by the vertically downward etching process P21 in the second etching process P2, exposing the underlying third support material layer 195. Conversely, when removing the remaining portion of the fourth support material layer 197, the first portion 211, also exposed from the mask patterns 220, can be partially removed by both the vertically downward etching process P21 and the lateral etching process P22 in the second etching process P2. The height of the exposed first part 211 can be reduced by the vertical downward etching process P21, and the thickness of the exposed first part 211 can be locally reduced by the lateral etching process P22, thus forming a second part 213 with a lower height and a thinner local thickness.

[0085] It should be noted that in this embodiment, various parameters of the lateral etching process P22 (such as etching temperature, etching rate, or etching selectivity) are further adjusted to intentionally form a uniform and relatively small second thickness T2 on the top of the second portion 213. Simultaneously, in accordance with the etching angle of the lateral etching process P22, a gradually downward-sloping inclined surface 215 facing the unetched fourth support material layer 197 is formed on the second portion 213. This allows for the formation of a groove 217 on the top of each second portion 213, with the notch facing the fourth support material layer 197.Figure 4 As shown. Thus, the top aperture of each through-hole 192 exposed by the mask pattern 220 can be correspondingly enlarged. Furthermore, it should be noted that the inclined surface 215 on the second portion 213 is positioned between the unetched fourth support material layer 197 and the second support material layer 193 in the direction perpendicular to the substrate 110, such that the portion of the second portion 213 above the inclined surface 215 has a relatively small second thickness T2, while the portion below the inclined surface 215 has a relatively large first thickness T1.

[0086] like Figure 5 As shown, a third etching process P3 is performed using the mask pattern 220, such as a dry etching process or a wet etching process with a relatively high etching ratio, to completely remove the third support material layer 195 exposed from the mask pattern 220, as well as the second support material layer 193 and the first support material layer 191 directly below it. In other words, the third etching process P3 removes the support layer structure 190 that directly contacts each of the second portions 213, while retaining the support layer structure 190 that directly contacts each of the first portions 211, and then completely removes the mask pattern 220.

[0087] Next, as Figure 6 As shown, a fourth etching process P4 is performed, such as an isotropic wet etching process, to completely remove the remaining third support material layer 195 and the first support material layer 191. Specifically, the isotropic wet etching process involves introducing an etchant such as tetramethylammonium hydroxide (TMAH). The space created after the support layer structure 190 was removed by the aforementioned third etching process P3 continues to remove the remaining third support material layer 195 and the first support material layer 191 to both sides, but is not limited to the aforementioned etchant. In this way, multiple bottom electrode layers 230 and 232 can be formed. Each bottom electrode layer 230 has two upwardly extending first portions 211 of the same height in the direction perpendicular to the substrate 110, presenting a symmetrical U-shaped structure. The bottom electrode layer 232 has two opposing first portions 211 and second portions 213 in the direction perpendicular to the substrate 110, presenting an asymmetrical U-shaped structure.

[0088] Meanwhile, the remaining second support material layer 193 (such as Figure 5 (as shown) and the remaining fourth support material layer 197 (as shown) Figure 5As shown, a first support layer 241 and a second support layer 243 can be formed respectively. The first support layer 241 and the second support layer 243, arranged sequentially from bottom to top, can together form a support structure 240 supporting the bottom electrode layers 230 and 232, and directly contact and support the first portion 211 of each bottom electrode layer 230 and 232. The top surface of the second support layer 243 can be flush with and higher than the top surface of the first portion 211 of each bottom electrode layer 230 and 232. Preferably, the thickness of the second support layer 243 is greater than the thickness of the first support layer 241 located adjacent to the substrate 110, for example, approximately 2 to 5 times the thickness of the first support layer 241. Figure 6 As shown, but not limited to.

[0089] Then, as Figure 7 As shown, a deposition process is performed on substrate 110 to sequentially form a capacitor dielectric layer 234 and a top electrode layer 236. Thus, bottom electrode layers 230 and 232, capacitor dielectric layer 234, and top electrode layer 236 can jointly form a capacitor structure 250. Specifically, capacitor dielectric layer 234 conformally covers the exposed surfaces of bottom electrode layers 230 and 232 and dielectric layer 170, while top electrode layer 236 fills the remaining space between bottom electrode layers 230 and 232. Furthermore, portions of capacitor dielectric layer 234 and top electrode layer 236 can be further filled between second support layer 243 and first support layer 241, and further filled between first support layer 241 and dielectric layer 170. In one embodiment, the capacitor dielectric layer 234 includes, for example, a dielectric material with a high dielectric constant, selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2), and zirconium oxide-aluminum oxide-zirconia (ZAZ), preferably zirconium oxide-aluminum oxide-zirconia; the top electrode layer 236 includes, for example, a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto.

[0090] Thus, the fabrication process of capacitor structure 250 is completed. Capacitor structure 250 includes multiple vertically extending capacitors as storage nodes (SN) of semiconductor device 100. These storage nodes are electrically connected to transistor components (not shown) of semiconductor device 100 via storage node pads 180 and storage node plugs (i.e., contacts 150), ensuring good contact between capacitor structure 250 and the storage node plugs disposed on substrate 110. Therefore, semiconductor device 100 of this embodiment can form a dynamic random access memory (DRAM) device, which is composed of at least one transistor component and at least one capacitor forming the smallest unit (memory cell) in a DRAM array to receive voltage information from bit line 160 and the buried word line.

[0091] According to the fabrication method in the first embodiment of the present invention, the semiconductor device 100 is fabricated by simultaneously performing an etching process (such as...) when partially removing the fourth support material layer 197. Figure 4 In the second etching process (P2) shown, the vertically downward etching process P21 etches the first portion 211 of the initial bottom electrode layer 210 to reduce the height of the first portion 211. Simultaneously, the lateral etching process P22 in the same etching process locally reduces the thickness of the first portion 211, forming a lower-height, locally thinner second portion 213. Thus, at least a portion of the bottom electrode layer 232 is composed of the first portion 211 and the second portion 213 of different heights, presenting an asymmetrical U-shaped structure. Furthermore, it should be noted that the top of the second portion 213 has a groove 217 with a notch facing the second support layer 243, allowing the top diameter of each through-hole 192 to be correspondingly enlarged, thereby further increasing the distance between the first portion 211 and the second portion 213 of each bottom electrode layer 230, 232 (e.g., ...). Figure 4 (As shown). Under this operation, the subsequent deposition and fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236 can be carried out more smoothly, allowing the capacitor dielectric layer 234 to uniformly and conformally cover the bottom electrode layers 230 and 232, while the top electrode layer 236 can densely fill the remaining space, forming a more structurally optimized semiconductor device 100. Therefore, the semiconductor device 100 fabrication method in the first embodiment of the present invention can effectively improve the fabrication defects caused by the increase in memory cell density, optimize the fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236, and thereby improve the functionality and structural reliability of the semiconductor device 100.

[0092] Furthermore, those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication method of the present invention may also have other forms, and are not limited to those described above. For example, when partially removing the support layer structure 190 through the mask pattern 220, it is also possible to first use the second etching process P2 to remove the remaining portion of the fourth support material layer 197 and the third support material layer 195 below it, exposing the second support material layer 193. Then, an isotropic wet etching process is used to completely remove the remaining third support material layer 195. Subsequently, a subsequent etching process is used to remove the exposed second support material layer 193 and the first support material layer 191 below it through the mask pattern 220, and another isotropic wet etching process is used to completely remove the remaining first support material layer 191. Other embodiments or variations of the method for the semiconductor device of the present invention will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. Furthermore, the same components in the various embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the various embodiments.

[0093] Please refer to Figures 8 to 9 The diagram illustrates the steps of a method for fabricating a semiconductor device 300 according to a second embodiment of the present invention. The fabrication steps of the semiconductor device 300 in this embodiment are generally the same as those of the semiconductor device 100 in the first embodiment described above, and will not be repeated here. The main difference between this embodiment and the first embodiment is that, in this embodiment, by adjusting the parameters of the second etching process P5, the vertically downward etching process P51 does not affect the height of the first portion 211, and only the lateral etching process P52 locally reduces the thickness of the exposed first portion 211, thereby forming a second portion 313 with a height equal to the height of the first portion 211 and a locally thinner thickness.

[0094] It should be noted that the second part 313 is also locally formed with a uniform and relatively small second thickness T2, and a gradually downward sloping inclined surface 315 facing the unetched fourth support material layer 197, so that the top of the second part 313 can form a groove 317 with a notch facing the fourth support material layer 197, such as... Figure 8As shown. It should be noted that the inclined surface 315 on the second portion 313 is positioned between the top and bottom surfaces of the unetched fourth support material layer 197 in the direction perpendicular to the substrate 110, resulting in a relatively small second thickness T2 in the portion of the second portion 313 above the inclined surface 315, and a relatively large first thickness T1 in the portion below the inclined surface 315. Thus, at least a portion of the bottom electrode layer 332 is composed of a first portion 211 and a second portion 313 of the same height, both with their top surfaces flush with the top surface of the fourth support material layer 197. Due to the relatively thin local thickness of the second portion 313, the bottom electrode layer 332 exhibits an asymmetrical U-shaped structure. Under this operation, the top aperture of each via 192 exposed from the mask pattern 220 can also be correspondingly enlarged, which is beneficial for subsequent deposition processes.

[0095] Then, the process continues as described in the aforementioned embodiments. Figure 5 The third etching process shown is P3. Figure 6 The fourth etching process P4 shown is related to... Figure 7 The deposition process of the capacitor dielectric layer 234 and the top electrode layer 236 shown forms a structure as follows: Figure 9 The semiconductor device 300 shown here, in which the bottom electrode layers 230 and 332, the capacitor dielectric layer 234, and the top electrode layer 236 can jointly form a capacitor structure 350. In this embodiment, the fabrication and material selection of the capacitor dielectric layer 234 and the top electrode layer 236 are generally the same as those in the first embodiment described above, and will not be repeated here.

[0096] Thus, the semiconductor device 300 of this embodiment is completed. The capacitor structure 350 of this embodiment also forms a plurality of vertically extending capacitors by sequentially stacking bottom electrode layers 230, 332, capacitor dielectric layer 234, and top electrode layer 236, serving as storage nodes of the semiconductor device 300. These capacitors are electrically connected to the transistor assembly (not shown) of the semiconductor device 300 through storage node pads 180 and storage node plugs (i.e., contacts 150). Therefore, the semiconductor device 300 of this embodiment can also form a dynamic random access memory device.

[0097] According to the fabrication method in the second embodiment of the present invention, the semiconductor device 300 is fabricated by simultaneously performing an etching process (such as...) when partially removing the fourth support material layer 197. Figure 8In the second etching process P5 shown, the lateral etching process P52 locally reduces the thickness of the first portion 211, forming a locally thinner second portion 313. Thus, at least a portion of the bottom electrode layer 332 includes a second portion 313 with the same height as the first portion 211, a top surface flush with the top surface of the second support layer 243, but a locally thinner thickness, resulting in an overall asymmetrical U-shaped structure. The inclined surface 315 of the second portion 313 is higher than the bottom surface of the second support layer 243 in a direction perpendicular to the substrate 110. In this configuration, the top of the second portion 313 also has a groove 317 with a notch facing the second support layer 243 to further increase the distance between the first portion 211 and the second portion 313 of each bottom electrode layer 230, 332 (e.g., ...). Figure 8 As shown, this facilitates the subsequent deposition and fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236. Therefore, the fabrication method of the semiconductor device 300 in the second embodiment of the present invention can also effectively improve the fabrication defects caused by the increase in memory cell density, optimize the fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236, and thereby improve the functional and structural reliability of the semiconductor device 300.

[0098] Please refer to Figures 10 to 11 The diagram illustrates the steps of a method for fabricating a semiconductor device 400 according to a third embodiment of the present invention. The fabrication steps of the semiconductor device 400 in this embodiment are generally the same as those of the semiconductor device 100 in the first embodiment described above, and will not be repeated here. The main difference between this embodiment and the first embodiment is that, in this embodiment, when removing... Figure 5 When the mask pattern 220 is shown, it is partially etched together as shown. Figure 5 The remaining fourth support material layer 197 and the first part 211 are shown.

[0099] In detail, this embodiment further forms a first portion 411 with a smaller height and a second support layer 443 with a thinner thickness when removing the mask pattern 220. The height of the first portion 411 is the same as the height of the second portion 213, and slightly lower than the top surface of the second support layer 443. Then, a fourth etching process P6 is performed to completely remove the mask pattern 220. Figure 5The remaining third support material layer 195 and the first support material layer 191 are shown. Thus, part of the bottom electrode layer 430 consists of two first portions 411 of the same height and uniform first thickness T1, while the other part of the bottom electrode layer 432 consists of a first portion 411 and a second portion 213 of the same height, both with their top surfaces lower than the top surface of the second support layer 443. Because the second portion 213 has a locally thinner thickness, the bottom electrode layer 432 exhibits an asymmetrical U-shaped structure. It should be noted that in this embodiment, the inclined surface 215 on the second portion 213 is still located between the second support layer 443 and the first support layer 241 in the direction perpendicular to the substrate 110, resulting in a relatively smaller second thickness T2 above the inclined surface 215 and a relatively larger first thickness T1 below the inclined surface 215. Under this operation, the top aperture of some vias 192 can also be correspondingly enlarged, which is beneficial for subsequent deposition processes.

[0100] Then, as Figure 11 As shown, the deposition process continues to form a capacitor dielectric layer 234 and a top electrode layer 236. Thus, the bottom electrode layers 430 and 432, the capacitor dielectric layer 234, and the top electrode layer 236 together form a capacitor structure 450. In this embodiment, the fabrication and material selection of the capacitor dielectric layer 234 and the top electrode layer 236 are largely the same as in the first embodiment described above, and will not be repeated here. Thus, the semiconductor device 400 of this embodiment is completed. The capacitor structure 450 of this embodiment also includes a plurality of vertically extending capacitors as storage nodes of the semiconductor device 400, and is electrically connected to the transistor assembly (not shown) of the semiconductor device 400 through storage node pads 180 and storage node plugs (i.e., contacts 150). Therefore, the semiconductor device 400 of this embodiment can also form a dynamic random access memory device.

[0101] According to the fabrication method in the third embodiment of the present invention, when removing the mask pattern 220, the semiconductor device 400 partially etches the remaining fourth support material layer 197 and the first portion 211 simultaneously through the etching fabrication process. Thus, a portion of the bottom electrode layer 430 is composed of two first portions 411 of the same height, with their top surfaces slightly lower than the top surface of the second support layer 443, while another portion of the bottom electrode layer 432 is composed of a first portion 411 and a second portion 213 of the same height, both with their top surfaces lower than the top surface of the second support layer 443. In this configuration, the top of the second portion 213 also has a groove 217 with a notch facing the second support layer 443, to further increase the distance between the first portion 411 and the second portion 313 of each bottom electrode layer 430, 432 (e.g., ...). Figure 10As shown, this facilitates the subsequent deposition and fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236. Therefore, the fabrication method of the semiconductor device 400 in the third embodiment of the present invention can also effectively improve the fabrication defects caused by the increase in memory cell density, optimize the fabrication processes of the capacitor dielectric layer 234 and the top electrode layer 236, and thereby improve the functional and structural reliability of the semiconductor device 400.

[0102] Please refer to Figure 12 The illustration shows a schematic diagram of the fabrication steps of the semiconductor device 500 in the fourth embodiment of the present invention. The fabrication steps of the semiconductor device 500 in this embodiment are generally the same as those of the semiconductor device 100 in the first embodiment, and will not be repeated here. The main difference between this embodiment and the first embodiment is that, in this embodiment, by adjusting various parameters of the etching process, the inclined surface 515 of the second portion 513 can face the inclined surface 515 of the adjacent second portion 513. This allows the top space between two adjacent second portions 513 to be correspondingly increased, which is also beneficial for the subsequent deposition processes of the capacitor dielectric layer 234 and the top electrode layer 236.

[0103] According to one embodiment of the present invention, by adjusting different parameters of the etching process, the top surface of the second portion 513 is flush with the top surface of the first portion 211, such that the inclined surface 515 is positioned between the bottom surface of the second support layer 243 and the first support layer 241 in the direction perpendicular to the substrate 110. Figure 12 As shown. However, in another embodiment, the parameters of the etching process can be modified according to actual needs, and the top surface of the second portion 513 may not be flush with the top surface of the second support layer 243, for example, it may be lower than the top surface of the second support layer 243, but it is not limited thereto. In addition, in yet another embodiment (not shown), the parameters of the etching process can be modified according to actual needs, and the first portion 211 may have a top surface that is flush with the second portion 513, and the top surface may also be selected as described above. Figure 9 As shown, it is level with the top surface of the second support layer 243, or as described above. Figure 11 The top surface of the second support layer 243 is shown below the second support layer 243, while the inclined surface 515 on the second part 513 can be as described above. Figure 9 As shown, in the direction perpendicular to the substrate 110, it is higher than the bottom surface of the second support layer 243 and lies between the bottom and top surfaces of the second support layer 243, or as described above. Figure 11 As shown, it is also located between the bottom surface of the second support layer 243 and the first support layer 241.

[0104] Therefore, the manufacturing method of the semiconductor device 500 in the fourth embodiment of the present invention can also effectively improve the manufacturing defects caused by the increase in memory cell density, optimize the manufacturing process of capacitor dielectric layer 234 and top electrode layer 236, and thus improve the functional and structural reliability of semiconductor device 500.

[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, comprising: Substrate; Multiple memory node pads are disposed on the substrate; A capacitor structure is disposed on the storage node pad. The capacitor structure includes multiple capacitors. Each capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top. The top of the bottom electrode layer has a groove. as well as The support structure includes multiple first support layers and multiple second support layers from bottom to top, connecting two adjacent capacitors, wherein the grooves are respectively oriented towards each of the second support layers; The bottom electrode layer includes a first portion and a second portion located on the same memory node pad. The first portion is in direct contact with the support structure, and the second portion is isolated from the support structure. The groove is located on the side of the adjacent second portions that are opposite to each other.

2. The semiconductor device according to claim 1, characterized in that, The bottom electrode layer further includes an inclined surface, the bottom electrode layer having a first thickness below the inclined surface and a second thickness above the inclined surface, the first thickness being greater than the second thickness.

3. The semiconductor device according to claim 2, characterized in that, The inclined surface is located between the second support layer and the first support layer in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 2, characterized in that, The inclined surface is higher than the bottom surface of the second support layer in a direction perpendicular to the substrate.

5. The semiconductor device according to claim 1, characterized in that, The bottom electrode layer includes an upwardly extending first portion and a second portion, the groove is disposed on the second portion, and the top surface of the second portion is lower than the top surface of the second support layer.

6. The semiconductor device according to claim 5, characterized in that, The top surface of the first part is flush with the top surface of the second support layer.

7. The semiconductor device according to claim 5, characterized in that, The top surface of the first portion is lower than the top surface of the second support layer.

8. The semiconductor device according to claim 5, characterized in that, The top surface of the first portion or the top surface of the second portion is higher than the bottom surface of the second support layer.

9. The semiconductor device according to claim 5, characterized in that, Each of the first portions directly contacts each of the first support layer and each of the second support layers of the support structure.

10. The semiconductor device according to claim 1, characterized in that, Each of the bottom electrode layers has a symmetrical or asymmetrical U-shaped structure.

11. A method for fabricating a semiconductor device, characterized in that... include: Provide substrate; Multiple memory node pads are formed on the substrate; A capacitor structure is formed on the storage node pads. The capacitor structure includes multiple capacitors, each capacitor comprising, from bottom to top, a bottom electrode layer, a dielectric layer, and a top electrode layer. The top of the bottom electrode layer has a recess. A support structure is formed to connect two adjacent capacitors. The support structure includes a first support layer and a second support layer from bottom to top, wherein the grooves are respectively oriented towards each of the second support layers. The bottom electrode layer includes a first portion and a second portion located on the same memory node pad. The first portion is in direct contact with the support structure, and the second portion is isolated from the support structure. The groove is located on the side of the adjacent second portions that are opposite to each other.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the support structure also includes: A first support material layer, a second support material layer, a third support material layer, and a fourth support material layer are formed on the substrate in a sequentially stacked manner; Multiple through holes are formed, which penetrate the fourth support material layer, the third support material layer, the second support material layer, and the first support material layer; Multiple mask patterns are formed on the fourth support material layer; The mask pattern is used to remove portions of the fourth support material layer, portions of the third support material layer, portions of the second support material layer, and portions of the first support material layer. Remove the mask pattern; and The first support material layer is completely removed to form the support structure.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, Also includes: An electrode material layer is formed and covers the surface of each of the through holes; Partially remove the electrode material layer to form multiple initial bottom electrode layers; as well as The initial bottom electrode layer is etched using the mask pattern to form the bottom electrode layer.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The etching process includes lateral etching of the initial bottom electrode layer and vertical etching of the initial bottom electrode layer to form the bottom electrode layer.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The bottom electrode layer further includes an inclined surface, the bottom electrode layer having a first thickness below the inclined surface and a second thickness above the inclined surface, the first thickness being greater than the second thickness.

16. The method for fabricating a semiconductor device according to claim 13, characterized in that, The etching process is performed simultaneously with the removal of the fourth support material layer in the aforementioned portion.

17. The method for fabricating a semiconductor device according to claim 13, characterized in that, After the etching process is performed, the third support material layer, the second support material layer, and the first support material layer of the portion are removed.

18. The method for fabricating a semiconductor device according to claim 13, characterized in that, When removing the mask pattern, the remaining portion of the fourth support material layer is partially removed.

19. The method for fabricating a semiconductor device according to claim 18, characterized in that, The bottom electrode layer includes an upwardly extending first portion and a second portion, the groove being formed on the second portion, and the top surface of the first portion being lower than the top surface of the second support layer after the remaining portion of the fourth support material layer is partially removed.

20. The method for fabricating a semiconductor device according to claim 18, characterized in that, The bottom electrode layer includes an upwardly extending first portion and a second portion, the groove being formed on the second portion, and the top surface of the first portion being flush with the top surface of the second support layer after the remaining portion of the fourth support material layer is partially removed.

Images