Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a substrate; a bit line structure arranged on the surface of the substrate and extending along a first direction, a plurality of bit line structures arranged along a second direction, the first direction being perpendicular to the second direction; a semiconductor column arranged on the surface of the bit line structure and arranged in an array; a word line structure arranged on the surface of the bit line structure and insulated from the bit line structure, the word line structure being located between the semiconductor columns and extending along the second direction, a plurality of word line structures being arranged in the first direction and spaced apart from the semiconductor columns, two semiconductor columns adjacent in the first direction sharing the same word line structure, and each semiconductor column being controlled by two word line structures located on both sides of the semiconductor column in the first direction. The above technical solution arranges a word line structure between two columns of semiconductor columns, reduces the arrangement of an isolation layer, and uses two word line structures to control one column of semiconductor columns, thereby reducing the voltage applied to the word line structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the development of integrated circuit manufacturing technology, the process nodes of integrated circuits are constantly shrinking, and the feature size of semiconductor technology is constantly shrinking. Traditional planar transistors can no longer meet the needs, so fin transistors have emerged and are widely used.

[0003] Currently, DRAM typically uses finned transistors in the array region, with word lines (WL) buried inside the silicon substrate to reduce the area per transistor. Bit lines (BL) and node connections (NC) are located on the surface of the silicon substrate and lie on the same plane. However, with increasing miniaturization, trade-offs have arisen between the dimensions of the bit lines and the node connections. Furthermore, in existing technologies, each transistor is controlled by a single word line, requiring a sufficiently high voltage.

[0004] Therefore, improving transistor wiring structures and optimizing transistor switching circuits have become problems that need to be solved.

[0005] Public content

[0006] The technical problem to be solved by this disclosure is how to improve the transistor wiring structure and optimize the transistor switching circuit, and provide a semiconductor device and its fabrication method.

[0007] To address the aforementioned problems, this disclosure provides a semiconductor device, comprising: a substrate; bit line structures disposed on the surface of the substrate and extending along a first direction, wherein multiple bit line structures are arranged along a second direction, the first direction being perpendicular to the second direction; semiconductor pillars disposed on the surface of the bit line structures and arranged in an array; and word line structures disposed on the surface of the bit line structures and insulated from the bit line structures, wherein the word line structures are located between the semiconductor pillars and extending along the second direction, wherein multiple word line structures and semiconductor pillars are arranged at intervals along the first direction, wherein two adjacent semiconductor pillars in the first direction share the same word line structure, and each semiconductor pillar is jointly controlled by two word line structures located on its two sides in the first direction.

[0008] In some embodiments, the two word line structures located on either side of the semiconductor pillar in the first direction are used to apply voltages of opposite polarity.

[0009] In some embodiments, the bit line structure further includes: a bit line disposed on the substrate surface and extending along the first direction, and a plurality of the bit lines arranged along the second direction; and a bit line connection structure disposed on the bit line surface and extending along the first direction, and a plurality of the bit line connection structures arranged along the second direction.

[0010] In some embodiments, the semiconductor device further includes a first insulating layer disposed between the plurality of bit line structures.

[0011] In some embodiments, the word line structure further includes: a word line disposed on the surface of the bit line structure and insulated from the bit line structure, the word line extending along a second direction, and a plurality of word lines spaced apart along the first direction; and a gate dielectric layer disposed between the word line and the semiconductor pillar.

[0012] In some embodiments, the semiconductor device further includes: a second insulating layer disposed between the word line structure and the bit line structure, and between adjacent semiconductor pillars in a second direction; and a third insulating layer disposed on the surface of the word line structure and located at least between the semiconductor pillars.

[0013] In some embodiments, the semiconductor device further includes a node connection structure disposed at one end of the semiconductor pillar away from the bit line structure and arranged in an array.

[0014] In some embodiments, the semiconductor device further includes a fourth insulating layer disposed on the surface of the third insulating layer, at least between the node connection structures.

[0015] In some embodiments, the semiconductor device further includes a charge storage structure, the charge storage structure array being arranged on the surface of the node connection structure.

[0016] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate; forming a bit line structure on the surface of the substrate, the bit line structure extending along a first direction, and multiple bit line structures arranged along a second direction, the first direction being perpendicular to the second direction; forming an array of semiconductor pillars on the surface of the bit line structure; forming a word line structure on the surface of the bit line structure, the word line structure being insulated from the bit line structure and located between the semiconductor pillars, extending along the second direction, multiple word line structures and semiconductor pillars being arranged at intervals along the first direction, two adjacent semiconductor pillars in the first direction sharing the same word line structure, and each semiconductor pillar being jointly controlled by two word line structures located on its two sides in the first direction.

[0017] In some embodiments, the step of forming a bit line structure on the substrate surface further includes: forming a first conductive layer on the substrate surface; etching the first conductive layer to form a first trench, the first trench extending along the first direction; forming a first insulating layer in the first trench, the retained first conductive layer serving as the bit line structure.

[0018] In some embodiments, the step of forming an array of semiconductor pillars on the surface of the bit line structure further includes: forming a semiconductor layer on the surface of the bit line structure; etching the semiconductor layer to form a second trench, the second trench extending along a first direction; forming a first isolation layer in the second trench; etching the semiconductor layer and the first isolation layer to form a third trench, the third trench extending along a second direction, and the etched semiconductor layer serving as the semiconductor pillars.

[0019] In some embodiments, the step of forming a word line structure on the surface of the bit line structure further includes: forming a second isolation layer in the third trench; forming a gate dielectric layer, the gate dielectric layer covering both sides of the semiconductor pillar along the first direction; depositing a conductive material on the surface of the second isolation layer and the side of the gate dielectric layer as a word line, the gate dielectric layer and the word line together constituting the word line structure; and forming a third insulating layer on the surface of the gate dielectric layer and the word line.

[0020] In some embodiments, after the step of forming a word line structure on the surface of the bit line structure, the method includes: forming an array of node connection structures on the surface of the semiconductor pillar; and forming an array of charge storage structures on the surface of the node connection structures.

[0021] In some embodiments, the step of forming an array of node connection structures on the surface of the semiconductor pillar further includes: depositing a second conductive layer; and etching the second conductive layer to form the array of node connection structures.

[0022] In some embodiments, prior to the step of forming an array of charge storage structures on the surface of the node connection structures, a fourth insulating layer is formed in the gaps between the node connection structures.

[0023] The above technical solution employs a word-line structure between two rows of semiconductor pillars to control both rows, reducing the need for isolation layers and optimizing layout space. Simultaneously, it optimizes the transistor switching circuit by using a two-word-line structure to control one row of semiconductor pillars, achieving precise control of transistor switching. This also reduces the voltage applied to each word-line structure, minimizing damage to the chip from high voltage and extending its lifespan. Furthermore, distributing bit lines and node connection structures across different planes frees up more wiring space, allowing the dimensions of the bit line and node connection structures to be unconstrained by other structures, thus increasing the width and density of bit line wiring.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Appendix Figure 1 The diagram shown is a schematic diagram of the structure of a semiconductor device.

[0027] Appendix Figure 2 The diagram shown is a structural schematic of an embodiment of the semiconductor device described in this disclosure.

[0028] Appendix Figure 3A For the appendix Figure 2 A cross-sectional view along the AA' direction.

[0029] Appendix Figure 3B For the appendix Figure 2 A cross-sectional view along the BB' direction.

[0030] Appendix Figure 3C For the appendix Figure 2 A sectional view along the CC' direction.

[0031] Appendix Figure 4 The diagram shown is a flowchart of one embodiment of the method for fabricating the semiconductor device described in this disclosure.

[0032] Appendix Figures 5A-5O The diagram shown is a process flow chart of an embodiment of the method for fabricating the semiconductor device described in this disclosure. Detailed Implementation

[0033] The specific embodiments of the semiconductor devices and their fabrication methods provided in this disclosure will be described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this disclosure, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] Appendix Figure 1 The diagram shows a schematic of a semiconductor device. The semiconductor device includes: a substrate 10, bit lines 111, bit line connection structures 112, word lines 121, a gate dielectric layer 122, an insulating layer 13, a node connection structure 14, and a charge storage structure 15. The word lines 121 and the gate dielectric layer 122 form a word line structure, which is located inside the substrate 10. The bit lines 111 and the node connection structure 14 are located on the surface of the substrate 10 and are on the same plane. The bit line connection structure 112 is located inside the substrate 10 and on the surface of the bit lines 111 along a third direction D3. The bit line connection structure 112 and the bit lines 111 form a bit line structure and are insulated from the word line structure by the insulating layer 13. The charge storage structure 15 is located on the surface of the node connection structure 14.

[0035] This embodiment controls the switching of a transistor with a single word line, requiring a sufficiently high voltage. Therefore, this disclosure provides a semiconductor device and its fabrication method to improve the transistor wiring structure and optimize the transistor switching circuit.

[0036] Appendix Figure 2 The diagram shown is a structural schematic of an embodiment of the semiconductor device described in this disclosure, wherein the internal structures not visible on the surface are drawn with dashed lines. (See attached diagram.) Figure 3A For the appendix Figure 2 Cross-sectional view along the AA' direction. (Attached) Figure 3B For the appendix Figure 2 Cross-sectional view along the BB' direction. (Attached) Figure 3C For the appendix Figure 2 Sectional view along the CC' direction. (Refer to attached reference.) Figure 2 ~Attached Figure 3CThe semiconductor device includes: a substrate 200; bit line structures 210 disposed on the surface of the substrate 200 and extending along a first direction D1, with multiple bit line structures 210 arranged along a second direction D2, the first direction D1 being perpendicular to the second direction D2; semiconductor pillars 220 disposed on the surface of the bit line structures 210 and arranged in an array; word line structures 230 disposed on the surface of the bit line structures 210 and insulated from the bit line structures 210, the word line structures 230 being located between the semiconductor pillars 220 and extending along the second direction D2, multiple word line structures 230 and semiconductor pillars 220 being arranged at intervals along the first direction D1, two adjacent semiconductor pillars 220 in the first direction D1 sharing the same word line structure 230, and each semiconductor pillar 220 being jointly controlled by two word line structures 230 located on both sides of it in the first direction D1.

[0037] In some semiconductor devices, two word line structures are arranged between two adjacent columns of semiconductor pillars. This necessitates an isolation layer between the two word line structures to prevent them from conducting. In this embodiment, however, a single word line structure 230 is arranged between two adjacent columns of semiconductor pillars 220. This single word line structure 230 controls both columns of semiconductor pillars 220, reducing the need for an isolation layer and optimizing the layout space. Simultaneously, it optimizes the transistor switching circuit. Using two word line structures 230 positioned on either side of the same column of semiconductor pillars to control that column allows for precise control of the transistor switching. Furthermore, it reduces the voltage applied to each word line 231, minimizing damage to the chip from high voltage and extending the chip's lifespan.

[0038] The substrate 200 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the substrate 200 is made of single-crystal silicon (Si).

[0039] The semiconductor pillar 220 includes, but is not limited to, oxide semiconductor materials such as single-crystal silicon, polycrystalline silicon, and IGZO, as well as compound semiconductor materials such as InGaAs and GaN. In this embodiment, the material of the semiconductor pillar 220 is single-crystal silicon (Si).

[0040] As one embodiment, the two word line structures 230 located on both sides of the semiconductor pillar 220 in the first direction D1 are used to apply voltages of opposite polarity. One word line structure 230 on one side of the semiconductor pillar 220 carries a positive voltage, while the other word line structure carries a negative voltage. This achieves a larger voltage difference even with a relatively low voltage, thereby reducing the threshold voltage required for conduction and saving energy.

[0041] In this embodiment, the bit line structure 210 further includes: bit lines 211 disposed on the surface of the substrate 200 and extending along the first direction D1, with multiple bit lines 211 arranged along the second direction D2; and bit line connection structures 212 for connecting the bit lines 211 and the semiconductor pillars 220, disposed on the surface of the bit lines 211 and extending along the first direction D1, with multiple bit line connection structures 212 arranged along the second direction D2. In this embodiment, the material of the bit lines 211 is tungsten. In other embodiments, the material of the bit lines 211 may also be titanium nitride, metal silicide, copper, or copper-tungsten alloy. The material of the bit line connection structures 212 is polycrystalline silicon.

[0042] As one embodiment, the semiconductor device further includes a first insulating layer 201 disposed between the plurality of bit line structures 210. The first insulating layer 201 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxide layer, used to insulate each of the bit line structures 210.

[0043] In this embodiment, the word line structure 230 further includes: a word line 231 disposed on the surface of the bit line structure 210 and insulated from the bit line structure 210; the word line 231 extends along a second direction D2, and multiple word lines 231 are arranged at intervals along a first direction D1; and a gate dielectric layer 232 disposed between the word line 231 and the semiconductor pillars 220. Two rows of semiconductor pillars 220 share the same word line 231, and the gate dielectric layer 232 is disposed between the word line 231 and the semiconductor pillars 220 on both sides of the word line 231. In this embodiment, the material of the word line 231 is tungsten. In other embodiments, the material of the word line 231 may also be titanium nitride, metal silicide, copper, or a copper-tungsten alloy. The gate dielectric layer 232 is a silicon oxide layer or a high-k dielectric layer, used to insulate the word line 231 from the semiconductor pillars 220.

[0044] As one embodiment, the semiconductor device further includes: a second insulating layer 202 disposed between the word line structure 230 and the bit line structure 210, and between adjacent semiconductor pillars 220 in the second direction D2; and a third insulating layer 203 disposed on the surface of the word line structure 230 and at least located between the semiconductor pillars 220. The second insulating layer 202 may be a silicon nitride layer, a silicon oxide layer, and a silicon oxide layer, used to insulate each of the word line structures 230, insulate each of the semiconductor pillars 220 in the second direction D2, and insulate the word line structure 230 from the bit line structure 210. The third insulating layer 203 may be a silicon nitride layer, a silicon oxide layer, and a silicon oxide layer, used to insulate the word line structure 230 from subsequent film layers and to insulate each of the semiconductor pillars 220.

[0045] In this embodiment, the semiconductor device further includes a node connection structure 240, which is disposed at one end of the semiconductor pillar 220 opposite to the bit line structure 210 and arranged in an array. As one embodiment, the node connection structure 240 consists of a polysilicon layer and a metal layer located on the surface of the polysilicon layer. The metal layer can be made of tungsten, titanium nitride, metal silicide, copper, or a copper-tungsten alloy. The node connection structure 240 and the bit line structure 210 are distributed along a third direction D3 at both ends of the semiconductor pillar 220. Figure 1 In one embodiment, the bit line and node connection structure in the semiconductor device are located on the same plane as the word line. However, as chips continue to shrink, the planar structure located on the same side of the word line can no longer meet the wiring requirements. Therefore, in the appendix... Figure 2 ~Attached Figure 3C In the illustrated embodiment, by changing the relative positions of the node connection structure 240 and the bit line structure 210 to be set on different planes, the positional relationship between the node connection structure 240 and the bit line structure 210 changes from a planar positional relationship set on the same side of the word line structure to a three-dimensional positional relationship set on both sides of the word line structure. This frees up more wiring space, so that the size of the bit line 211 and the node connection structure 240 is not constrained by other structures, thereby increasing the width and density of bit line wiring.

[0046] In this embodiment, the semiconductor device further includes a fourth insulating layer 204 disposed on the surfaces of the second insulating layer 202 and the third insulating layer 203, at least between the node connection structures 240. The fourth insulating layer 204 is a silicon nitride layer, a silicon oxide layer, and a silicon oxide layer, used to insulate each of the node connection structures 240.

[0047] In this embodiment, the semiconductor device further includes a charge storage structure 250, which is arrayed on the surface of the node connection structure 240. The node connection structure 240 is used to connect the semiconductor pillar 220 and the charge storage structure 250. The charge storage structure includes, but is not limited to, a capacitor.

[0048] The above technical solution uses a word line 231 between two rows of semiconductor pillars 220 to control both rows of semiconductor pillars 220, reducing the need for isolation layers and optimizing layout space. Simultaneously, it optimizes the transistor switching circuit by using two word lines 231 to control one row of semiconductor pillars 220, achieving precise control of the transistor switching. This also reduces the voltage applied to each word line 231, minimizing damage to the chip from high voltage and extending its lifespan. Furthermore, distributing the bit lines 211 and node connection structures 240 on different planes frees up more wiring space, allowing the dimensions of the bit lines 211 and node connection structures 240 to be unconstrained by other structures, thus increasing the width and density of bit line wiring.

[0049] This disclosure also provides a method for fabricating the above-mentioned semiconductor device, with appended... Figure 4 The diagram illustrates the steps of an embodiment of the semiconductor memory structure fabrication method disclosed herein, including the following steps: Step S41, providing a substrate; Step S42, forming a bit line structure on the surface of the substrate, the bit line structure extending along a first direction, and multiple bit line structures arranged along a second direction, the first direction being perpendicular to the second direction; Step S43, forming an array of semiconductor pillars on the surface of the bit line structure; Step S44, forming a word line structure on the surface of the bit line structure, the word line structure being insulated from the bit line structure and located between the semiconductor pillars, extending along the second direction, multiple word line structures and semiconductor pillars arranged at intervals along the first direction, two adjacent semiconductor pillars in the first direction sharing the same word line structure, and each semiconductor pillar being jointly controlled by two word line structures located on both sides of it in the first direction.

[0050] Appendix Figures 5A-5O The diagram shown is a process flow chart of an embodiment of the semiconductor device fabrication method described in this disclosure. (See attached diagram.) Figure 5A ~Attached Figure 5G The attached image shows... Figure 2 Subsequent process drawings following the sectional view along the BB' direction, attached. Figure 5H ~Attached Figure 5O The attached image shows... Figure 2 Subsequent process drawings of the sectional view along the AA' direction.

[0051] Refer to step S41 and appendix Figure 5AA substrate 200 is provided. The material of the substrate 200 can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the material of the substrate 200 is single-crystal silicon (Si).

[0052] Refer to step S42 and appendix Figure 5D A bit line structure 210 is formed on the surface of the substrate 200. The bit line structure 210 extends along a first direction D1, and multiple bit line structures 210 are arranged along a second direction D2. The first direction D1 is perpendicular to the second direction D2.

[0053] As one example, see attached Figure 5B ~Attached Figure 5D As shown, this disclosure provides a method for forming a bit line structure 210 on the surface of the substrate 200, further comprising the following steps:

[0054] As attached Figure 5B As shown, a first conductive layer 501 is formed on the surface of the substrate 200. The first conductive layer 501 further includes a first metal layer 521 and a first polysilicon layer 531. In some embodiments, a metal material can be deposited on the surface of the substrate 200 using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD) to form the first metal layer 521. The metal material includes, but is not limited to, tungsten, titanium nitride, metal silicide, copper, and copper-tungsten alloys. Polysilicon can be deposited on the surface of the first metal layer 521 using processes such as CVD and ALD to form the first polysilicon layer 531.

[0055] As attached Figure 5C As shown, the first conductive layer 501 is etched to form a first trench 511, and the first trench extends along the first direction D1 of 511.

[0056] As attached Figure 5D As shown, a first insulating layer 201 is formed within the first trench 511, and the first conductive layer 501 (illustrated in...) is retained. Figure 5C The first insulating layer 201 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxide layer. In some embodiments, the method for forming the first insulating layer 201 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. After forming the first insulating layer 201, the method further includes a step of planarizing the first insulating layer 201 and the bit line structure 210. As a specific embodiment, the first metal layer 521 (illustrated in...) is... Figure 5C As bit line 211, the first polysilicon layer 531 (shown in...) Figure 5C ) as bit line connection structure 212.

[0057] After completing the above steps, you will obtain the attached document. Figure 5D The bitline structure 210 is shown.

[0058] Refer to step S43 and appendix Figure 5H Semiconductor pillars 220 are arranged in an array on the surface of the bit line structure 210.

[0059] As one example, see attached Figure 5E ~Attached Figure 5H As shown, this disclosure provides a method for forming an array of semiconductor pillars 220 on the surface of the bit line structure 210, further comprising the following steps:

[0060] As attached Figure 5E As shown, a semiconductor layer 541 is formed on the surface of the bit line structure 210. The semiconductor layer 541 includes, but is not limited to, single-crystal silicon, polycrystalline silicon, oxide semiconductor materials such as IGZO, and compound semiconductor materials such as InGaAs and GaN. In this embodiment, the material of the semiconductor layer 541 is single-crystal silicon (Si). Methods for forming the semiconductor layer 541 include, but are not limited to, self-growth of single-crystal silicon or adsorption bonding to another thin wafer.

[0061] As attached Figure 5F As shown, the semiconductor layer 541 is etched to form a second trench 512, which extends along the first direction D1.

[0062] As attached Figure 5G As shown, in the second trench 512 (illustrated in...) Figure 5F A first isolation layer 551 is formed within the semiconductor layer 541. The first isolation layer 551 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxide layer. In some embodiments, the method for forming the first isolation layer 551 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. After forming the first isolation layer 551, the method further includes the step of planarizing the first isolation layer 551 and the semiconductor layer 541.

[0063] It is worth noting that this embodiment includes... Figure 5H ~Attached Figure 5O The process drawing is along the attached Figure 2 A schematic cross-sectional view along the AA' direction. (See attached diagram) Figure 5H As shown, the semiconductor layer 541 is etched (illustrated in...). Figure 5G The first isolation layer 551 and the third trench 513 are formed, the third trench 513 extending along the second direction D2, and the etched semiconductor layer 541 (shown in the figure) Figure 5G ) serves as the semiconductor pillar 220.

[0064] After completing the above steps, you will obtain the attached document. Figure 5H Semiconductor pillar 220 is shown.

[0065] Refer to step S44 and appendix Figure 5L A word line structure 230 is formed on the surface of the bit line structure 210. The word line structure 230 is insulated from the bit line structure 210 and is located between the semiconductor pillars 220, extending along the second direction D2. Multiple word line structures 230 and semiconductor pillars 220 are arranged at intervals along the first direction D1. Two adjacent semiconductor pillars 220 in the first direction D1 share the same word line structure 230, and each semiconductor pillar 220 is jointly controlled by two word line structures 230 located on both sides of it in the first direction D1.

[0066] As one example, see attached Figure 5I ~Attached Figure 5L As shown, this disclosure provides a method for forming a word line structure 230 on the surface of the bit line structure 210, further comprising the following steps:

[0067] As attached Figure 5I As shown, a second insulating layer 552 is formed within the third trench 513, and the first insulating layer 551 and the second insulating layer 552 serve as a second insulating layer 202 (illustrated in...). Figure 5L An insulating material is deposited within the third trench 513 and partially etched to form the second isolation layer 552. The second isolation layer 552 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxide layer. In some embodiments, the method for forming the second isolation layer 552 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0068] As attached Figure 5J As shown, a gate dielectric layer 232 is formed, which covers both sides of the semiconductor pillar 220 along the first direction D1. In this embodiment, forming the gate dielectric layer further includes depositing a gate dielectric material on the surface of the second isolation layer 552 and forming the gate dielectric layer 232 by self-aligned etching. The surface of the gate dielectric layer 232 is lower than the surface of the semiconductor pillar 220 in the third direction D3. The gate dielectric material can be silicon oxide or a high-k dielectric layer. Methods for depositing the gate dielectric material include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0069] As attached Figure 5KAs shown, conductive material is deposited on the surface of the second isolation layer 552 and the sidewall of the gate dielectric layer 232 to form word lines 231. The gate dielectric layer 232 and the word lines 231 together constitute the word line structure 230. In some embodiments, metal material can be deposited on the surface of the second isolation layer 552 and the sidewall of the gate dielectric layer 232 using processes such as chemical vapor deposition and atomic layer deposition to form the word lines 231. The metal material includes, but is not limited to, tungsten, titanium nitride, metal silicide, copper, and copper-tungsten alloys.

[0070] As attached Figure 5L As shown, a third insulating layer 203 is formed on the surface of the gate dielectric layer 232 and the word line 231. The third insulating layer 203 may be a silicon nitride layer, a silicon oxide layer, or a silicon oxide layer. In some embodiments, the method for forming the third insulating layer 203 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. After forming the third insulating layer 203, a further step of planarizing the third insulating layer 203 is included.

[0071] After completing the above steps, you will obtain the attached document. Figure 5L The word line structure 230 is shown. A word line structure 230 is placed between two columns of semiconductor pillars 220. Using one word line structure 230 to control two columns of semiconductor pillars 220 reduces the need for isolation layers and optimizes layout space. Simultaneously, it optimizes the transistor switching circuit. Using two word line structures 230 to control one column of semiconductor pillars 220 achieves precise control of the transistor switching, while also reducing the voltage applied to each word line structure 230, minimizing damage to the chip from high voltage, and extending the chip's lifespan.

[0072] Continue to refer to the appendix Figure 2 After the step of forming word line structure 230 on the surface of bit line structure 210, the method includes: forming an array of node connection structures 240 on the surface of semiconductor pillar 220; and forming an array of charge storage structures 250 on the surface of node connection structures 240.

[0073] As one example, see attached Figure 5M ~Attached Figure 5N As shown, this disclosure provides a method for forming an array of node connection structures 240 on the surface of the semiconductor pillar 220, further comprising the following steps:

[0074] As attached Figure 5MAs shown, a second conductive layer 502 is deposited. The second conductive layer 502 further includes a second polysilicon layer 532 and a second metal layer 522. In some embodiments, polysilicon can be deposited on the surfaces of the semiconductor pillar 220, the second insulating layer 202, and the third insulating layer 203 using processes such as chemical vapor deposition and atomic layer deposition to form the second polysilicon layer 532. A metal material can be deposited on the surface of the second polysilicon layer 532 using processes such as chemical vapor deposition and atomic layer deposition to form the second metal layer 522. The metal material includes, but is not limited to, tungsten, titanium nitride, metal silicide, copper, and copper-tungsten alloys.

[0075] As attached Figure 5N As shown, the second conductive layer 502 is etched to form the arrayed node connection structure 240.

[0076] After completing the above steps, you will obtain the attached document. Figure 5N The node connection structure 240 is shown. By distributing the bit line structure 210 and the node connection structure 240 on different planes, more routing space is freed up, and the dimensions of the bit line structure 210 and the node connection structure 240 are not constrained by other structures, thereby increasing the width and density of bit line routing.

[0077] As one example, see attached Figure 5O As shown, prior to the step of forming an array of charge storage structures 250 on the surface of the node connection structure 240, a fourth insulating layer 204 is formed in the gaps between the node connection structures 240. The fourth insulating layer 204 may be a silicon nitride layer, a silicon carbide layer, or a silicon oxide layer. In some embodiments, the method for forming the fourth insulating layer 204 includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. After forming the fourth insulating layer 204, a further step of planarizing the fourth insulating layer 204 is included.

[0078] As one example, see attached Figure 2 As shown, an array of charge storage structures 250 are formed on the surface of the node connection structure 240. The node connection structure 240 is used to connect the semiconductor pillar 220 and the charge storage structure 250. The above units together constitute the semiconductor device disclosed herein, as shown in the attached figure. Figure 2 ~Attached Figure 3C As shown.

[0079] The above technical solution sets a word line structure between two columns of semiconductor pillars, using the same word line structure to control both columns of semiconductor pillars. This reduces the need for isolation layers and optimizes layout space. Simultaneously, it optimizes the transistor switching circuit, using two word line structures to control one column of semiconductor pillars, achieving precise control of transistor switching. This also reduces the voltage applied to each word line structure, minimizing damage to the chip from high voltage and extending chip lifespan. Furthermore, distributing bit lines and node connection structures on different planes frees up more wiring space, allowing the dimensions of the bit line and node connection structures to be unconstrained by other structures, increasing the width and density of bit line wiring.

[0080] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0081] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0082] It should be noted that the terms "comprising" and "having," and their variations, used in this disclosure are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this disclosure can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this disclosure. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to mutually.

[0083] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Bit line structures are disposed on the surface of the substrate and extend along a first direction. Multiple bit line structures are arranged along a second direction, and the first direction is perpendicular to the second direction. Semiconductor pillars are disposed on the surface of the bit line structure and arranged in an array; A word line structure is disposed on the surface of the bit line structure and is insulated from the bit line structure. The word line structure is located between the semiconductor pillars and extends along the second direction. Multiple word line structures are arranged at intervals with the semiconductor pillars along the first direction. Two adjacent semiconductor pillars in the first direction share the same word line structure, and each semiconductor pillar is jointly controlled by two word line structures located on both sides of it in the first direction.

2. The semiconductor device according to claim 1, characterized in that, The two word line structures located on either side of the semiconductor pillar in the first direction are used to apply voltages of opposite polarity.

3. The semiconductor device according to claim 1, characterized in that, The bitline structure further includes: Bit lines are disposed on the surface of the substrate and extend along the first direction, and multiple bit lines are arranged along the second direction; Bit line connection structures are disposed on the surface of the bit line and extend along the first direction, and multiple bit line connection structures are arranged along the second direction.

4. The semiconductor device according to claim 1, characterized in that, It also includes a first insulating layer disposed between the plurality of bit line structures.

5. The semiconductor device according to claim 1, characterized in that, The word line structure further includes: A word line is disposed on the surface of the bit line structure and is insulated from the bit line structure. The word line extends along a second direction, and multiple word lines are arranged at intervals along the first direction. A gate dielectric layer is disposed between the word line and the semiconductor pillar.

6. The semiconductor device according to claim 1, characterized in that, Also includes: A second insulating layer is disposed between the word line structure and the bit line structure, and between adjacent semiconductor pillars in the second direction; A third insulating layer is disposed on the surface of the word line structure and is located at least between the semiconductor pillars.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor device further includes a node connection structure, which is disposed at one end of the semiconductor pillar away from the bit line structure and arranged in an array.

8. The semiconductor device according to claim 7, characterized in that, It also includes a fourth insulating layer disposed on the surface of the third insulating layer, at least between the node connection structures.

9. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes a charge storage structure, which is arranged in an array on the surface of the node connection structure.

10. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: Provide a substrate; A bit line structure is formed on the surface of the substrate, the bit line structure extends along a first direction, and multiple bit line structures are arranged along a second direction, the first direction being perpendicular to the second direction; An array of semiconductor pillars is formed on the surface of the bit line structure; A word line structure is formed on the surface of the bit line structure. The word line structure is insulated from the bit line structure and is located between the semiconductor pillars, extending along the second direction. Multiple word line structures are arranged at intervals with the semiconductor pillars along the first direction. Two adjacent semiconductor pillars in the first direction share the same word line structure, and each semiconductor pillar is jointly controlled by two word line structures located on both sides of it in the first direction.

11. The method according to claim 10, characterized in that, The step of forming a bit line structure on the substrate surface further includes: A first conductive layer is formed on the surface of the substrate; The first conductive layer is etched to form a first trench, which extends along the first direction; a first insulating layer is formed in the first trench, and the retained first conductive layer serves as the bit line structure.

12. The method according to claim 10, characterized in that, The step of forming an array of semiconductor pillars on the surface of the bit line structure further includes: A semiconductor layer is formed on the surface of the bit line structure; The semiconductor layer is etched to form a second trench, the second trench extending along a first direction; A first isolation layer is formed within the second trench; The semiconductor layer and the first isolation layer are etched to form a third trench, which extends along a second direction, and the etched semiconductor layer serves as the semiconductor pillar.

13. The method according to claim 12, characterized in that, The step of forming a word line structure on the surface of the bit line structure further includes: A second isolation layer is formed within the third trench; A gate dielectric layer is formed, the gate dielectric layer covering both sides of the semiconductor pillar along the first direction; Conductive material is deposited on the surface of the second isolation layer and the side of the gate dielectric layer to serve as word lines. The gate dielectric layer and the word lines together constitute the word line structure. A third insulating layer is formed on the gate dielectric layer and the word line surface.

14. The method according to claim 10, characterized in that, The step of forming a word line structure on the surface of the bit line structure includes: An array of node connection structures is formed on the surface of the semiconductor pillar; An array of charge storage structures is formed on the surface of the node connection structure.

15. The method according to claim 14, characterized in that, The step of forming an array of node connection structures on the surface of the semiconductor pillar further includes: Deposit a second conductive layer; The second conductive layer is etched to form the array of node connection structures.

16. The method according to claim 14, characterized in that, The step prior to forming an array of charge storage structures on the surface of the node connection structure includes: A fourth insulating layer is formed in the gap between the node connection structures.

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