A superconducting quantum chip and a method of fabricating the same

Abstract

This invention discloses a superconducting quantum chip and its fabrication method, applicable to the field of quantum computing technology. The chip includes a substrate; the substrate has at least two through-holes extending from one surface to another, filled with superconducting material to form connection channels; a coplanar waveguide structure located on one surface of the substrate; the coplanar waveguide structure includes at least two mutually separated ends on the substrate surface, one end of the coplanar waveguide structure contacting the end of one connection channel, and the other end of the coplanar waveguide structure contacting the end of another connection channel; a superconducting layer located on the other surface of the substrate, the superconducting layer contacting the ends of at least two connection channels; and connection channels in contact with the same superconducting layer contacting the same coplanar waveguide structure. Linking the coplanar waveguide structure and the superconducting layer through connection channels within the substrate acts as an air bridge, avoiding interference between the coplanar waveguide structure and the superconducting layer, and possesses extremely high structural strength.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a superconducting quantum chip and a method for fabricating a superconducting quantum chip. Background Technology

[0002] Superconducting quantum computing is one of the most promising general-purpose quantum computing schemes, with a superconducting quantum computer exceeding 1000 qubits expected to be realized by 2023. The superconducting quantum chip is the core component of a superconducting quantum computer. As the number of qubits increases, significant crosstalk occurs when reading and controlling qubit signals through a coplanar waveguide (CPW) structure. Therefore, it is necessary to connect the separated ground planes on both sides of the CPW to achieve potential balance and reduce crosstalk. Currently, the most common approach is to use an air-bridge scheme, where numerous superconducting bridges span the CPW to connect the ground planes on both sides, eliminating the potential difference. Typically, photoresist reflow or silicon oxide is used as bridging supports. Superconducting bridges are fabricated on these supports, and then the supports are released to complete the fabrication of the air bridges.

[0003] In current methods for fabricating air bridges, the air bridge and the CPW structure are typically located on the same side surface of the chip, requiring them to be fabricated sequentially. However, if the air bridge is fabricated after the CPW and other large structures and the Josephson junction are completed, there is a risk of residual contamination and damage to the original device. For example, high-temperature processes such as photolithography baking and photoresist reflow can significantly affect the characteristics of the Josephson junction, thus altering the overall chip performance. If the air bridge is fabricated before the Josephson junction, its presence significantly interferes with the fabrication, limiting the overall device processing. Furthermore, because the air bridge forms a suspended structure with piers and a surface, its strength is relatively low, making it prone to breakage during fabrication. Therefore, providing a superconducting quantum chip that avoids interference from the air bridge with the CPW structure remains a challenge for those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a superconducting quantum chip that can avoid interference between the air bridge and the CPW structure; another purpose of this invention is to provide a method for fabricating a superconducting quantum chip that can avoid interference between the air bridge and the CPW structure.

[0005] To address the aforementioned technical problems, this invention provides a superconducting quantum chip, comprising:

[0006] The substrate includes two opposing surfaces and is provided with at least two through holes extending from one of the surfaces to the other, the through holes being filled with superconducting material to form a connection channel.

[0007] A coplanar waveguide structure located on one surface of the substrate; the coplanar waveguide structure includes at least two ends separated from each other on the surface of the substrate, one end of the coplanar waveguide structure is in contact with one end of the connecting channel, and the other end of the coplanar waveguide structure is in contact with the end of another connecting channel;

[0008] A superconducting layer located on the other surface of the substrate, the superconducting layer being in contact with the ends of at least two of the connection channels; the connection channels in contact with the same superconducting layer being in contact with the same coplanar waveguide structure.

[0009] Optionally, the axis of the connection channel is perpendicular to the surface of the substrate.

[0010] Optionally, the substrate is a silicon substrate, and the superconducting material filling the through-hole is metallic aluminum.

[0011] Optionally, the material of the coplanar waveguide structure is tantalum metal, and the superconducting layer is a tantalum superconducting layer.

[0012] This invention also provides a method for fabricating a superconducting quantum chip, comprising:

[0013] At least two blind holes extending toward the other side of the substrate are provided on one side surface of the substrate;

[0014] A superconducting material is placed inside the blind hole to form a connection channel;

[0015] The substrate is thinned from the other side surface to expose the ends of the connection channels on both opposite surfaces of the substrate, and a coplanar waveguide structure is formed on one side surface of the substrate, and a superconducting layer is formed on the other side surface of the substrate; the coplanar waveguide structure includes at least two ends separated from each other on the substrate surface, one end of the coplanar waveguide structure contacts the end of one of the connection channels, and the other end of the coplanar waveguide structure contacts the end of another connection channel; the superconducting layer contacts the ends of at least two of the connection channels; the connection channels contacted by the same superconducting layer are in contact with the same coplanar waveguide structure.

[0016] Optionally, thinning the substrate from the other side surface to expose the ends of the connection channel on both opposite surfaces of the substrate, and forming a coplanar waveguide structure on one side surface of the substrate, and forming a superconducting layer on the other side surface of the substrate, includes:

[0017] The coplanar waveguide structure or the superconducting layer is disposed on one side surface of the substrate where the blind hole is located;

[0018] After the coplanar waveguide structure or the superconducting layer is formed on the surface of the substrate, the substrate is thinned from the opposite side surface of the substrate to expose the end of the connection channel;

[0019] After thinning the substrate, the surface of the connection channel end is exposed, and the coplanar waveguide structure or the superconducting layer is disposed such that the coplanar waveguide structure and the superconducting layer are disposed opposite to the substrate.

[0020] Optionally, the coplanar waveguide structure or the superconducting layer is disposed on the side surface of the substrate where the blind hole is located, including:

[0021] The coplanar waveguide structure is disposed on one surface of the substrate on which the blind aperture is disposed;

[0022] The step of exposing the surface of the connection channel end after thinning the substrate, and setting the coplanar waveguide structure or the superconducting layer includes:

[0023] The superconducting layer is disposed on the surface of the end of the connection channel after the substrate is thinned to expose it.

[0024] Optionally, before thinning the substrate from the opposite side surface of the substrate, the method further includes:

[0025] A protective layer covering the coplanar waveguide structure is disposed on the surface of the substrate;

[0026] After setting the superconducting layer, the method further includes:

[0027] Remove the protective layer.

[0028] Optionally, before placing the superconducting material within the blind hole, the method further includes:

[0029] The blind holes are thermally oxidized to form an oxide layer;

[0030] Clean the oxide layer to smooth the inner wall of the blind hole.

[0031] Optionally, placing a superconducting material within the blind hole includes:

[0032] The blind hole is filled with molten superconducting material, and the molten superconducting material is subjected to ultrasonic treatment.

[0033] The present invention provides a superconducting quantum chip comprising: a substrate; the substrate having two opposing surfaces, the substrate having at least two through-holes extending from one surface to the other surface, the through-holes being filled with superconducting material to form connection channels; a coplanar waveguide structure located on one surface of the substrate; the coplanar waveguide structure having at least two mutually separated ends on the substrate surface, one end of the coplanar waveguide structure contacting the end of a connection channel, and the other end of the coplanar waveguide structure contacting the end of another connection channel; a superconducting layer located on the other surface of the substrate, the superconducting layer contacting the ends of at least two connection channels; and connection channels contacting the same superconducting layer and the same coplanar waveguide structure.

[0034] A coplanar waveguide structure and a superconducting layer are placed on two opposite surfaces of the substrate. The coplanar waveguide structure and the superconducting layer are linked by connecting channels within the substrate. These connecting channels, in conjunction with the superconducting layer, act as air bridges. By placing the superconducting layer and the coplanar waveguide structure on opposite surfaces, interference between them can be effectively avoided, and the surface space of the superconducting quantum chip can be fully utilized. Furthermore, since the superconducting layer is located on the substrate surface and the connecting channels are located inside the substrate, the resulting connection structure is not suspended on the substrate surface, thus effectively improving its structural strength.

[0035] The present invention also provides a method for preparing a superconducting quantum chip, which also has the above-mentioned beneficial effects, and will not be described in detail here. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of the structure of a superconducting quantum chip provided in an embodiment of the present invention;

[0038] Figures 2 to 4 This is a process flow diagram of a superconducting quantum chip fabrication method provided in an embodiment of the present invention;

[0039] Figures 5 to 18 This is a process flow diagram of a specific superconducting quantum chip fabrication method provided in an embodiment of the present invention.

[0040] In the figure: 1. Substrate, 2. Connecting channel, 21. Blind hole, 22. First mask, 23. Oxide layer, 3. Coplanar waveguide structure, 31. Superconducting film, 32. Second mask, 33. Protective layer, 4. Superconducting layer. Detailed Implementation

[0041] The core of this invention is to provide a superconducting quantum chip. In existing technologies, air bridges and CPW structures are usually located on the same side surface of the chip, thus requiring sequential fabrication of the air bridge and CPW structure. If the air bridge is fabricated after the CPW and other large structures and Josephson junctions are prepared, through photolithography, deposition, and etching processes, there is a risk of residual contamination and damage to the original device. For example, high-temperature processes such as photolithography baking and photoresist reflow can significantly affect the characteristics of the Josephson junction, thereby altering the overall chip performance. If the air bridge is fabricated before the Josephson junction is prepared, its presence significantly interferes with the Josephson junction fabrication, limiting the overall device fabrication process. Furthermore, because the air bridge forms a suspended structure through its piers and surface, its strength is relatively low, making it prone to breakage during fabrication.

[0042] The superconducting quantum chip provided by this invention features a coplanar waveguide structure and a superconducting layer disposed on two opposite surfaces of a substrate. The coplanar waveguide structure and the superconducting layer are linked by a connecting channel within the substrate. This connecting channel, in conjunction with the superconducting layer, acts as an air bridge. By placing the superconducting layer and the coplanar waveguide structure on opposite surfaces, interference between them can be effectively avoided, and the surface space of the superconducting quantum chip can be fully utilized. Furthermore, since the superconducting layer is located on the substrate surface and the connecting channel is located inside the substrate, the resulting connecting structure is not suspended on the substrate surface, thus effectively improving its structural strength.

[0043] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a superconducting quantum chip provided in an embodiment of the present invention.

[0045] See Figure 1In this embodiment of the invention, the superconducting quantum chip includes: a substrate 1; the substrate 1 includes two opposing surfaces, and the substrate 1 is provided with at least two through holes extending from one surface to the other surface, the through holes being filled with superconducting material to form connection channels 2; a coplanar waveguide structure 3 located on one surface of the substrate 1; the coplanar waveguide structure 3 includes at least two ends separated from each other on the surface of the substrate 1, one end of the coplanar waveguide structure 3 contacting one end of the connection channel 2, and the other end of the coplanar waveguide structure 3 contacting the other end of the connection channel 2; a superconducting layer 4 located on the other surface of the substrate 1, the superconducting layer 4 contacting the ends of at least two of the connection channels 2; and the connection channels 2 in contact with the same superconducting layer 4 are in contact with the same coplanar waveguide structure 3.

[0046] The substrate 1 described above can be a high-resistivity silicon substrate 1 or a sapphire substrate 1, serving as the carrier structure for the superconducting quantum chip. The substrate 1 includes two opposing surfaces. In this embodiment of the invention, different structures are specifically formed on the two opposing surfaces of the substrate 1 to create a complete superconducting quantum chip. Specifically, at least two through-holes are formed inside the substrate 1. Each through-hole extends from one of the opposing surfaces of the substrate 1 to the other. These through-holes are filled with a superconducting material, thereby forming a connection channel 2. This connection channel 2 electrically connects the structures formed on the two opposing surfaces of the substrate 1. The superconducting material filling the through-holes can specifically be aluminum (Al), indium (In), tin (Sn), titanium nitride (TiN), niobium nitride (NbN), etc. The specific material of the superconducting material is not specifically limited in this embodiment of the invention.

[0047] A coplanar waveguide structure 3 is disposed on one surface of the substrate 1. This coplanar waveguide structure 3 includes at least two ends that are separated from each other on the surface of the substrate 1. Specifically, the ends of the coplanar waveguide structure 3 are separated from each other on the surface of the substrate 1. The separated ends of the coplanar waveguide structure 3 are interconnected through the aforementioned connecting channel 2 and the superconducting layer 4, which will be described later. One end of the coplanar waveguide structure 3 is connected to the end of one connecting channel 2, and the other end of the coplanar waveguide structure 3 is connected to the end of another connecting channel 2. The specific structure of the coplanar waveguide structure 3 can be found in existing technology and will not be described in detail here.

[0048] A superconducting layer 4 is disposed on another surface of the substrate 1. This superconducting layer 4 needs to be in contact with the ends of at least two connection channels 2, and the connection channels 2 connected by one superconducting layer 4 will specifically be in contact with the same coplanar waveguide structure 3. That is, one end of the coplanar waveguide structure 3 will be connected to the conductive layer on the other side through a connection channel 2, and then connected to another connection channel 2 through the conductive layer, and then connected to the other end of the coplanar waveguide structure 3 through the connection channel 2, thereby realizing the electrical connection between the two separate ends of the coplanar waveguide structure 3.

[0049] Specifically, in this embodiment of the invention, the axis of the connecting channel 2 is typically perpendicular to the surface of the substrate 1. This minimizes the length of the connecting channel 2 within the substrate 1, reducing the difficulty of creating vias within the channel. Specifically, the substrate 1 is a silicon substrate 1, and the superconducting material filling the vias is aluminum. Because aluminum has a lower melting point than silicon, using silicon as the substrate 1 and first filling the vias with aluminum as the superconducting material facilitates the filling of the aluminum superconducting material. Specific details regarding the superconducting material configuration will be described in detail in the following embodiments of the invention, and will not be repeated here.

[0050] Furthermore, the material of the coplanar waveguide structure 3 is tantalum, and the superconducting layer 4 is a tantalum superconducting layer 4. Specifically, in this embodiment of the invention, aluminum is disposed inside the substrate 1 as the superconducting material, while tantalum is disposed on the surface of the substrate 1 as the material of the coplanar waveguide structure 3 and the superconducting layer 4. Compared to aluminum, tantalum has superior properties such as higher corrosion resistance. Therefore, in this embodiment of the invention, using aluminum to fill the interior of the substrate 1 facilitates the fabrication of the connection channel 2, while using tantalum as the material for the surface structure of the substrate 1 effectively improves the superconducting quantum chip's properties such as corrosion resistance. Of course, the specific materials of the connection channel 2, the superconducting layer 4, and the coplanar waveguide structure 3 are not specifically limited in this embodiment of the invention and depend on the specific circumstances.

[0051] The superconducting quantum chip provided in this embodiment of the invention includes: a substrate 1; the substrate 1 includes two opposing surfaces, and the substrate 1 is provided with at least two through holes extending from one surface to the other surface, the through holes being filled with superconducting material to form connection channels 2; a coplanar waveguide structure 3 located on one surface of the substrate 1; the coplanar waveguide structure 3 includes at least two mutually separated ends on the surface of the substrate 1, one end of the coplanar waveguide structure 3 being in contact with the end of one connection channel 2, and the other end of the coplanar waveguide structure 3 being in contact with the end of another connection channel 2; a superconducting layer 4 located on the other surface of the substrate 1, the superconducting layer 4 being in contact with the ends of at least two connection channels 2; the connection channels 2 in contact with the same superconducting layer 4 being in contact with the same coplanar waveguide structure 3.

[0052] A coplanar waveguide structure 3 and a superconducting layer 4 are disposed on two opposite surfaces of substrate 1. The coplanar waveguide structure 3 and the superconducting layer 4 are connected by a connecting channel 2 inside substrate 1. The connecting channel 2 and the superconducting layer 4 work together to act as an air bridge. By placing the superconducting layer 4 and the coplanar waveguide structure 3 on opposite surfaces, interference between the coplanar waveguide structure 3 and the superconducting layer 4 can be effectively avoided, and the surface space of the superconducting quantum chip can be fully utilized. At the same time, since the superconducting layer 4 is located on the surface of substrate 1 and the connecting channel 2 is located inside substrate 1, the connection structure formed by them is not suspended on the surface of substrate 1, thereby effectively improving its structural strength.

[0053] The following provides a method for fabricating a superconducting quantum chip, the details of which can be referenced in relation to the structure of the superconducting quantum chip described above.

[0054] Please refer to Figures 2 to 4 , Figures 2 to 4 This is a process flow diagram of a superconducting quantum chip fabrication method provided in an embodiment of the present invention.

[0055] See Figure 2 In this embodiment of the invention, the method for fabricating a superconducting quantum chip includes:

[0056] S101: At least two blind holes extending to the other side of the substrate are provided on one side surface of the substrate.

[0057] See Figure 3 The aforementioned blind via 21 needs to be formed on one side surface of the substrate 1 and extend to the opposite side surface of the substrate 1. The blind via 21 needs to be filled with conductive material to form the aforementioned connection channel 2. The process for forming the aforementioned blind via 21 can be a deep silicon etching process, i.e., a TSV (Through-Silicon-Via) process; it can also be formed using a laser drilling process. The specific fabrication process of the aforementioned blind via 21 is not specifically limited in this embodiment of the invention.

[0058] S102: Superconducting material is placed inside the blind hole to form a connecting channel.

[0059] See Figure 4 The specific process of setting superconducting material in blind hole 21 will be described in detail in the following embodiments of the invention, and will not be repeated here.

[0060] S103: Thinning the substrate from the other side surface of the substrate to expose the ends of the connection channel on both opposite surfaces of the substrate, and setting a coplanar waveguide structure on one side surface of the substrate and a superconducting layer on the other side surface of the substrate.

[0061] In this embodiment of the invention, the coplanar waveguide structure 3 includes at least two ends separated from each other on the surface of the substrate 1. One end of the coplanar waveguide structure 3 is in contact with the end of one of the connecting channels 2, and the other end of the coplanar waveguide structure 3 is in contact with the end of another connecting channel 2. The superconducting layer 4 is in contact with the ends of at least two of the connecting channels 2. The connecting channels 2 in contact with the same superconducting layer 4 are in contact with the same coplanar waveguide structure 3. The specific structure of the superconducting quantum chip has been described in detail in the above embodiments of the invention and will not be repeated here.

[0062] This step includes three processes: first, setting a coplanar waveguide structure 3 on one surface of substrate 1; second, thinning substrate 1 from the side without exposed blind via 21 until the end of connecting channel 2 is exposed; and third, setting a superconducting layer 4 on the other surface of substrate 1. Theoretically, there is no fixed order for these three processes; they can be performed in any order, as long as the thinning operation on substrate 1 is performed before setting the corresponding structure on the second surface of substrate 1.

[0063] In practice, the aforementioned thinning process reduces the structural strength of substrate 1. To ensure sufficient structural strength of substrate 1 during structure fabrication and achieve a high yield rate, a structure is typically first formed on the side of substrate 1 where the blind via 21 is located. This structure is either a coplanar waveguide structure 3 or a superconducting layer 4. Then, substrate 1 is thinned on the side without the blind via 21 to expose the superconducting material and form a connection channel 2. Finally, the other structure, either a coplanar waveguide structure 3 or a superconducting layer 4, is formed on the side of substrate 1 where the connection channel 2 is newly exposed, thus fabricating a superconducting quantum chip. Specifically, this step may include: setting the coplanar waveguide structure 3 or the superconducting layer 4 on one side surface of the substrate 1 where the blind via 21 is set; after setting the coplanar waveguide structure 3 or the superconducting layer 4 on the surface of the substrate 1, thinning the substrate 1 from the opposite side surface of the substrate 1 to expose the end of the connection channel 2; and setting the coplanar waveguide structure 3 or the superconducting layer 4 on the surface of the substrate 1 after thinning the substrate 1 to expose the end of the connection channel 2, such that the coplanar waveguide structure 3 and the superconducting layer 4 are set opposite to the substrate 1.

[0064] The present invention provides a method for fabricating a superconducting quantum chip. In the fabricated superconducting quantum chip, a coplanar waveguide structure 3 and a superconducting layer 4 are disposed on two opposite surfaces of a substrate 1. The coplanar waveguide structure 3 and the superconducting layer 4 are connected by a connecting channel 2 inside the substrate 1. The connecting channel 2, in conjunction with the superconducting layer 4, acts as an air bridge. By separately placing the superconducting layer 4 and the coplanar waveguide structure 3 on opposite surfaces, interference between the coplanar waveguide structure 3 and the superconducting layer 4 can be effectively avoided, and the surface space of the superconducting quantum chip can be fully utilized. Furthermore, since the superconducting layer 4 is located on the surface of the substrate 1 and the connecting channel 2 is located inside the substrate 1, the resulting connection structure is not suspended on the surface of the substrate 1, thereby effectively improving its structural strength.

[0065] The specific details of the method for fabricating a superconducting quantum chip provided by this invention will be described in detail in the following embodiments.

[0066] Please refer to Figures 5 to 18 , Figures 5 to 18 This is a process flow diagram of a specific superconducting quantum chip fabrication method provided in an embodiment of the present invention.

[0067] See Figure 5 In this embodiment of the invention, the method for fabricating a superconducting quantum chip includes:

[0068] S201: At least two blind holes extending to the other side of the substrate are provided on one side of the substrate surface.

[0069] See Figure 6 as well as Figure 7 In this step, blind holes 21 are specifically prepared by deep silicon etching process. Therefore, before this step, it is usually necessary to prepare a substrate 1. On one side surface of the substrate 1, which is usually defined as the front side of the substrate 1, a first mask 22 corresponding to the position of blind hole 21 is set. Specifically, the etching area can be defined by photolithography on the front side of the substrate 1. The size of the etching area is usually about 30μm×30μm.

[0070] In this step, a deep silicon etching process is used to etch the substrate 1 to a certain depth, typically around 300 μm, to complete the drilling of the substrate 1.

[0071] S202: Thermal oxidation of blind holes to form an oxide layer.

[0072] See Figure 8In this step, the substrate 1 with the holes drilled can be subjected to high-temperature steam thermal oxidation treatment to form an oxide layer 23 on the inner wall of the blind via 21. Specifically, this step can be performed by subjecting the silicon wafer with the holes drilled to high-temperature steam thermal oxidation treatment at 1100°C for 30 minutes to form a SiO2 oxide layer 23. The specific parameters such as the steam temperature and treatment time can be set according to actual conditions and are not specifically limited here.

[0073] S203: Clean the oxide layer to smooth the inner wall of the blind hole.

[0074] See Figure 9 In this step, the sample with the oxide layer 23 formed above can be treated with BOE (Buffered Oxide Etch) to clean away the oxide layer 23 formed above, thereby smoothing the inner wall of the blind hole 21.

[0075] S204: Fill the blind hole with superconducting molten material and then sonicate the superconducting molten material.

[0076] See Figure 10 as well as Figure 11 When, in this embodiment of the invention, it is necessary to select a superconducting metal or metal compound with a melting point lower than that of the substrate 1, such as aluminum, tin, or indium, as the superconducting material to fill the blind hole 21, the superconducting metal or metal compound with the lower melting point can be heated to a molten state to form a liquid. Then, the substrate 1 with the blind hole 21 is immersed in the molten liquid, so that the molten superconducting material fills the blind hole 21. At this time, the ultrasonic function can be further activated to allow the liquid to fully penetrate the etched blind hole 21 through ultrasonic vibration. The function of the ultrasonic treatment is to eliminate air bubbles in the blind hole 21 and ensure that the superconducting material liquid fully enters the blind hole 21. After that, the silicon wafer that has undergone the above treatment needs to be removed from the molten aluminum and cooled and solidified. Then, the excess superconducting material on the front side of the silicon wafer is removed and cleaned by a process such as CMP (Chemical Mechanical Polishing).

[0077] When using superconducting metal compounds such as TiN and NbN as the superconducting material, the superconducting material inside the blind hole 21 can be grown and filled using processes such as CVD (chemical vapor deposition), ALD (atomic layer deposition), PVD (physical vapor deposition), or electroplating. The specific filling method for the superconducting material is not specifically limited in this embodiment of the invention. After filling with the superconducting material, the surface of the substrate 1 is usually polished and ground to remove excess superconducting material and clean the surface.

[0078] S205: A coplanar waveguide structure is formed on the surface of the substrate on the side where a blind hole is formed.

[0079] Since the coplanar waveguide structure 3 is more complex than the superconducting layer 4 and has higher requirements for the strength of the substrate 1, in this embodiment of the invention, the coplanar waveguide structure 3 is prepared before the substrate 1 is thinned, and the superconducting layer 4 is prepared after the substrate 1 is thinned.

[0080] Specifically, before this step, it is usually necessary to remove the natural oxide layer generated on the sample surface after the above steps. That is, before the step, the silicon wafer that has been treated as described above can be placed in a magnetron sputtering device and the front side of the silicon wafer can be cleaned with Ar ions in a vacuum environment to remove the natural oxide layers such as aluminum oxide and silicon oxide on the surface of substrate 1.

[0081] See Figure 12 , Figure 13 as well as Figure 14 In this step, a superconducting film 31 needs to be grown on the surface of the substrate 1 on one side where the blind hole 21 is set. Specifically, a superconducting metal film Ta with a thickness of about 100 nm needs to be grown. Then, a second mask 32 corresponding to the coplanar waveguide structure 3 needs to be set on the surface of the superconducting film 31. Specifically, a photoresist coating can be performed on the front side of the substrate 1 after the above treatment to define the coplanar waveguide fabrication area. Finally, the superconducting film 31 will be etched based on the defined coplanar waveguide fabrication area to form the coplanar waveguide structure 3. This process can specifically include: using an etching process to process the above-treated wafer, and then removing the photoresist to complete the coplanar waveguide structure 3 with non-planar connection.

[0082] S206: A protective layer covering the coplanar waveguide structure is provided on the substrate surface.

[0083] See Figure 15 In order to avoid damage to the coplanar waveguide structure 3 during the subsequent thinning process of substrate 1, a protective layer 33 covering the coplanar waveguide structure 3 needs to be set on the surface of substrate 1 in this step. The protective layer 33 can be a glue layer, etc. Accordingly, this step can be: applying a homogeneous adhesive to protect the front side of the substrate 1.

[0084] S207: Thin the substrate from the opposite side surface of the substrate to expose the end of the connection channel.

[0085] See Figure 16Specifically, this step involves thinning the substrate 1 on the two opposing surfaces, specifically the surface from which the coplanar waveguide structure 3 was never located (i.e., the back surface relative to the front surface). Due to the protective layer 33, this thinning process will not damage the coplanar waveguide structure 3. This thinning process continues until the superconducting material filling the blind via 21 is exposed. Specifically, this step includes thinning and polishing from the back surface of the substrate 1 until the deep via filled with superconducting material is completely exposed and cleaned.

[0086] S208: After thinning the substrate, the surface at the end of the connection channel is exposed, and a superconducting layer is formed.

[0087] See Figure 17 Before this step, it is usually necessary to remove the natural oxide layer generated on the sample surface after the above steps. That is, before the step, the silicon wafer that has been treated as described above can be placed in a magnetron sputtering device and the front side of the silicon wafer can be cleaned with Ar ions in a vacuum environment to remove the natural oxide layers such as aluminum oxide and silicon oxide on the surface of substrate 1.

[0088] Then, in this step, a superconducting layer 4 needs to be grown on the surface of the substrate 1 after thinning to expose the ends of the connection channels 2. Specifically, it can be a superconducting metal layer Ta with a thickness of approximately 200 nm. This superconducting layer 4 needs to be in contact with the ends of at least two connection channels 2, thereby connecting the ends of the coplanar waveguide structure 3 that are previously separated. The specific thickness of the superconducting layer 4 is not specifically limited in this embodiment of the invention and depends on the specific circumstances.

[0089] S209: Remove the protective layer.

[0090] See Figure 18 In this step, the substrate 1 is usually cleaned to remove the protective layer 33 covering the coplanar waveguide structure 3 and to ensure that the substrate 1 is clean.

[0091] The method for fabricating a superconducting quantum chip provided in this embodiment of the invention involves oxidizing the inner wall of a blind hole 21 to form an oxide layer 23, and then removing the oxide layer 23. This process can smooth the inner wall of the blind hole 21, facilitating the subsequent fabrication of the connection channel 2.

[0092] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0094] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0095] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] The superconducting quantum chip and its fabrication method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A superconducting quantum chip, characterized in that, include: The substrate includes two opposing surfaces and is provided with at least two through holes extending from one of the surfaces to the other, the through holes being filled with superconducting material to form a connection channel. A coplanar waveguide structure located on one surface of the substrate; the coplanar waveguide structure includes at least two ends separated from each other on the surface of the substrate, one end of the coplanar waveguide structure is in contact with one end of the connecting channel, and the other end of the coplanar waveguide structure is in contact with the end of another connecting channel; A superconducting layer located on the other surface of the substrate, the superconducting layer being in contact with the ends of at least two of the connection channels; the connection channels in contact with the same superconducting layer being in contact with the same coplanar waveguide structure.

2. The superconducting quantum chip according to claim 1, characterized in that, The axis of the connecting channel is perpendicular to the surface of the substrate.

3. The superconducting quantum chip according to claim 2, characterized in that, The substrate is a silicon substrate, and the superconducting material filled in the through-hole is metallic aluminum.

4. The superconducting quantum chip according to claim 3, characterized in that, The material of the coplanar waveguide structure is tantalum metal, and the superconducting layer is a tantalum superconducting layer.

5. A method for fabricating a superconducting quantum chip, characterized in that, include: At least two blind holes extending toward the other side of the substrate are provided on one side surface of the substrate; A superconducting material is placed inside the blind hole to form a connection channel; The substrate is thinned from the other side surface to expose the ends of the connection channels on both opposite surfaces of the substrate, and a coplanar waveguide structure is formed on one side surface of the substrate, and a superconducting layer is formed on the other side surface of the substrate; the coplanar waveguide structure includes at least two ends separated from each other on the substrate surface, one end of the coplanar waveguide structure contacts the end of one of the connection channels, and the other end of the coplanar waveguide structure contacts the end of another connection channel; the superconducting layer contacts the ends of at least two of the connection channels; the connection channels contacted by the same superconducting layer are in contact with the same coplanar waveguide structure.

6. The method according to claim 5, characterized in that, Thinning the substrate from the other side surface to expose the ends of the connection channel on both opposite surfaces of the substrate, and forming a coplanar waveguide structure on one side surface of the substrate, and forming a superconducting layer on the other side surface of the substrate, comprises: The coplanar waveguide structure or the superconducting layer is disposed on one side surface of the substrate where the blind hole is located; After the coplanar waveguide structure or the superconducting layer is formed on the surface of the substrate, the substrate is thinned from the opposite side surface of the substrate to expose the end of the connection channel; After thinning the substrate, the surface of the connection channel end is exposed, and the coplanar waveguide structure or the superconducting layer is disposed such that the coplanar waveguide structure and the superconducting layer are disposed opposite to the substrate.

7. The method according to claim 6, characterized in that, The coplanar waveguide structure or the superconducting layer is disposed on one side surface of the substrate where the blind hole is located, including: The coplanar waveguide structure is disposed on one side surface of the substrate where the blind aperture is disposed; The step of exposing the surface of the connection channel end after thinning the substrate, and setting the coplanar waveguide structure or the superconducting layer includes: The superconducting layer is disposed on the surface of the end of the connection channel after the substrate is thinned to expose it.

8. The method according to claim 7, characterized in that, Before thinning the substrate from the opposite side surface of the substrate, the process further includes: A protective layer covering the coplanar waveguide structure is disposed on the surface of the substrate; After setting the superconducting layer, the method further includes: Remove the protective layer.

9. The method according to claim 5, characterized in that, Before placing the superconducting material within the blind hole, the method further includes: The blind holes are thermally oxidized to form an oxide layer; Clean the oxide layer to smooth the inner wall of the blind hole.

10. The method according to claim 5, characterized in that, The superconducting material disposed within the blind hole includes: The blind hole is filled with molten superconducting material, and the molten superconducting material is subjected to ultrasonic treatment.

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