Current sampling circuit for power transistor

Abstract

The application discloses a current sampling circuit of a power tube, comprising: a sampling resistor connected with the power tube; a voltage amplification circuit comprising a first input end and a second output end connected with two ends of the sampling resistor respectively, the voltage amplification circuit being used for amplifying the voltage between the two ends of the sampling resistor and outputting the amplified voltage through the first output end and the second output end; a feedback output circuit connected with the first output end and the second output end of the voltage amplification circuit, the feedback output circuit outputting a sampling current representing the current flowing through the power tube by making the voltage of the first output end equal to the voltage of the second output end; and a current bias circuit comprising a first resistor, used for providing a bias current to the voltage amplification circuit according to the first resistor, so that the voltage amplification circuit has a fixed gain with high precision and without change with process corner.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a current sampling circuit for a power transistor. Background Technology

[0002] In power supply systems, the conversion of electrical energy and the stabilization of output voltage are achieved by controlling the on and off of switching power transistors, such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors).

[0003] Because power transistors require a large current to flow through them and their operating environment is complex, many protection circuits are needed to protect them. Therefore, in many applications, it is usually necessary to detect the current of the power transistor so that it can operate safely and / or be used for other functions.

[0004] Traditional sampling methods use a sampling resistor and an operational amplifier to sample the current of the power transistor. The sampling resistor is located in the current path of the power transistor, and the operational amplifier operates in a negative feedback loop. To reduce losses in the power transistor's current path, the sampling resistor is typically very small, resulting in a very small voltage drop across it. This places high demands on the offset and gain of the operational amplifier. Figure 1 The transistors Mp1 and Mn1 in the system require a Vgs voltage to operate normally. Therefore, the application of this sampling method is greatly limited under low-voltage operating conditions, which reduces the overall performance of the system. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a current sampling circuit for a power transistor, the sampling range of which is not limited by the input voltage and output voltage, ensuring that the circuit can work normally in the full voltage range, thereby improving the overall performance of the system.

[0006] According to an embodiment of the present invention, a current sampling circuit for a power transistor is provided, comprising: a sampling resistor connected to the power transistor; a voltage amplification circuit including a first input terminal and a second output terminal respectively connected to the two ends of the sampling resistor, the voltage amplification circuit being used to amplify the voltage across the sampling resistor and output the amplified voltage through the first output terminal and the second output terminal; and a feedback output circuit connected to the first output terminal and the second output terminal of the voltage amplification circuit, the feedback output circuit outputting a sampling current characterizing the current flowing through the power transistor by making the voltage at the first output terminal equal to the voltage at the second output terminal. The current sampling circuit further comprises: a current biasing circuit including a first resistor, used to provide a bias current to the voltage amplification circuit according to the first resistor, so that the voltage amplification circuit has a gain negatively correlated with the resistance value of the first resistor.

[0007] Optionally, the current bias circuit further includes a first to a fourth transistor, wherein the first resistor, the first transistor, and the third transistor are connected sequentially between the power supply voltage and ground, and the second transistor and the fourth transistor are connected sequentially between the power supply voltage and ground. The first transistor and the second transistor form a current mirror, and the third transistor and the fourth transistor form a current mirror.

[0008] Optionally, the first transistor and the second transistor are P-type metal-oxide-semiconductor field-effect transistors, and the third transistor and the fourth transistor are N-type metal-oxide-semiconductor field-effect transistors.

[0009] Optionally, the voltage amplification circuit includes: a fifth transistor, the first terminal of which is connected to the power supply voltage, and the control terminal of which is connected to the common terminal of the second transistor and the fourth transistor, wherein the fifth transistor obtains the bias current by mirroring; a sixth transistor and a seventh transistor, the first terminals of which are both connected to the second terminal of the fifth transistor, wherein the control terminal of the sixth transistor is the first input terminal connected to one end of the sampling resistor, and its second terminal is the first output terminal; the control terminal of the seventh transistor is the second input terminal connected to the other end of the sampling resistor, and its second terminal is the second output terminal; a first load resistor, the first terminal of which is connected to the second terminal of the sixth transistor, and its second terminal is grounded; and a second load resistor, the first terminal of which is connected to the second terminal of the seventh transistor, and its second terminal is grounded.

[0010] Optionally, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type metal-oxide-semiconductor field-effect transistors.

[0011] Optionally, the feedback output circuit includes: an operational amplifier having an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein the inverting input terminal is connected to the second terminal of the sixth transistor, the non-inverting input terminal is connected to the second terminal of the seventh transistor, and an eighth transistor having a control terminal connected to the output terminal of the operational amplifier, a second terminal connected to the second terminal of the sixth transistor, and a first terminal for outputting the sampling current.

[0012] Optionally, the error amplifier operates in a negative feedback state to adjust the loop so that the voltage at the first output terminal is equal to the voltage at the second output terminal.

[0013] Optionally, the feedback output circuit further includes: a ninth transistor, the first terminal of which is connected to the power supply voltage, and the second terminal of which is connected to the first terminal of the eighth transistor; and a tenth transistor, the first terminal of which is connected to the power supply voltage, and the control terminal of which is connected to the control terminal and the second terminal of the ninth transistor, wherein the ninth transistor and the tenth transistor constitute a current mirror to output the current of the eighth transistor through the second terminal of the tenth transistor as the sampling current.

[0014] Optionally, the eighth transistor is an N-type metal-oxide-semiconductor field-effect transistor, and the ninth and tenth transistors are P-type metal-oxide-semiconductor field-effect transistors.

[0015] The current sampling circuit of the power transistor in this embodiment of the invention has the following advantages: It realizes a fixed-gain fully differential error amplifier in a simple way, and the gain does not change with the PVT (Process, Voltage, Temperature) Corner. The error amplifier samples and amplifies the voltage of the sampling resistor. The amplified voltage signal is converted into a current signal through a dual-input single-output operational amplifier to complete the current sampling. The circuit structure is simple, the accuracy is high, and it is not limited by the operating voltage range of the power transistor. It can achieve high-precision current sampling in the full voltage range of the power transistor. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0017] Figure 1 This is a schematic circuit diagram of a current sampling circuit for a power transistor in the prior art.

[0018] Figure 2 This is a schematic circuit diagram of a current sampling circuit for a power transistor according to an embodiment of the present invention. Detailed Implementation

[0019] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0020] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0021] In this application, the transistor can be a P-type MOSFET (P-Metal-Oxide-Semiconductor Field-Effect Transistor) or an N-type MOSFET (N-Metal-Oxide-Semiconductor Field-Effect Transistor). The first terminal, second terminal, and control terminal of the P-type MOSFET are the source, drain, and gate, respectively, while the first terminal, second terminal, and control terminal of the N-type MOSFET are the drain, source, and gate, respectively.

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This is a schematic circuit diagram of a current sampling circuit for a power transistor, based on existing technology. Figure 1As shown, the first and second terminals of the power transistor P1 under test are connected to the input voltage Vin and the output voltage Vout, respectively. The drive module 101 is connected to the control terminal of the power transistor P1 under test to provide it with a gate drive signal Vgate. The current sampling circuit 100 includes sampling resistors Rs1 and Rs2, sampling transistor Mp1, operational amplifier OP1, and transistors Mn1 and Mn2. The sampling resistor Rs1 is connected in the current path of the power transistor P1 under test, with its first terminal connected to the second terminal of the power transistor P1 under test and its second terminal connected to the output voltage Vout. The first terminal of the sampling resistor Rs2 is connected to the common terminal of the power transistor P1 under test and the sampling resistor Rs1, and its second terminal is connected to the operational amplifier OP1. The operational amplifier OP1 has an inverting input terminal, a non-inverting input terminal, and an output terminal. Its inverting input terminal is connected to the second terminal of the sampling resistor Rs2, its non-inverting input terminal is connected to the second terminal of the sampling resistor Rs1, and its output terminal is connected to the control terminal of the sampling transistor Mp1. The first terminal of sampling transistor Mp1 is connected to the second terminal of sampling resistor Rs2, and its second terminal is connected to the first terminal of transistor Mn1. The control terminals of transistors Mn1 and Mn2 are connected to each other and to the first terminal of transistor Mn1, while their second terminals are both connected to ground. Transistors Mn1 and Mn2 form a current mirror, outputting a sampling current Is at the first terminal of transistor Mn2. Operational amplifier OP1 operates in a negative feedback loop, ensuring that the voltage difference across sampling resistor Rs2 equals the voltage difference across sampling resistor Rs1. The resulting sampling current Is = K × Iload × (Rs1 / Rs2), where K is the scaling factor of the current mirror, and Iload is the current flowing through the power transistor.

[0024] Existing power transistor current sampling circuits have the following drawbacks: To reduce the switching path losses of power transistor P1, the sampling resistor Rs1 is typically very small, resulting in a small voltage drop across it. This places high demands on the offset and gain of operational amplifier OP1. Furthermore, both transistors Mp1 and Mn1 require a gate-source voltage Vgs. Therefore, the application of this circuit is significantly limited under low-voltage operating conditions, potentially leading to a failure to effectively protect power transistor P1 in a timely manner, thus affecting the overall system performance.

[0025] Figure 2 This is a schematic circuit diagram of a current sampling circuit for a power transistor according to an embodiment of the present invention. Figure 2 In this circuit, power transistor P1 is the main output transistor of the chip, connected between the input and output terminals. Power transistor P1, for example, is an N-type MOSFET. Its first terminal is connected to the chip's input terminal to receive the input voltage Vin, and its second terminal is connected to the chip's output terminal to provide the output voltage Vout to subsequent circuits. The gate drive signal Vgate is used to control the on and off states of power transistor P1, thereby controlling the power transfer between the chip's input and output terminals.

[0026] The drive module 101 is used to provide the gate drive signal Vgate to the power transistor P1. For example, the drive module 101 is implemented by a charge pump, which provides sufficient drive signal to the power transistor P1 according to the input voltage Vin to control the turn-on and turn-off process of the power transistor P1.

[0027] The current sampling circuit 200 includes a sampling resistor Rs, a current bias circuit 201, a voltage amplifier circuit 202, and a feedback output circuit 203. The current bias circuit 201 provides a bias current Id to the voltage amplifier circuit 202. The voltage amplifier circuit 202 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. Its first input terminal is connected to the first end of the sampling resistor Rs, and its second input terminal is connected to the second end of the sampling resistor Rs. The voltage amplifier circuit 202 amplifies the voltage across the sampling resistor Rs and outputs the amplified voltage through the first and second output terminals. The feedback output circuit 203 is connected to the first and second output terminals of the voltage amplifier circuit 202. The feedback output circuit outputs a sampling current Is representing the current flowing through the power transistor by making the voltage at the first and second output terminals equal.

[0028] The current bias circuit 201 includes a resistor R0, transistors Mp1 and Mp2, and transistors Mn1 and Mn2. Resistor R0, transistors Mp1 and Mn1 are sequentially connected between the power supply voltage Vdd and ground Gnd, and transistors Mp2 and Mn2 are sequentially connected between the power supply voltage Vdd and ground Gnd. Transistors Mp1 and Mp2 form a current mirror, and transistors Mn1 and Mn2 also form a current mirror. The current bias circuit 201 obtains the bias current Id generated by resistor R0 and transistor Mp1 using the following formula:

[0029]

[0030] Where up is the carrier (hole) mobility, Cox is the gate oxide capacitance, and K is the scaling factor of transistors Mp1 and Mp2, the voltage amplifier circuit 202 includes transistors Mp3 to Mp5, and load resistors RL1 and RL2. The first terminal of transistor Mp3 is connected to the power supply voltage Vdd, and its control terminal is connected to the common terminal of transistors Mp2 and Mn2. Transistor Mp3 obtains the bias current Id through mirroring. Transistors Mp4 and Mp5 form the input pair of voltage amplifier circuit 202, and the first terminals of both transistors Mp4 and Mp5 are connected to the second terminal of transistor Mp3. The control terminal of transistor Mp4 is the first input terminal of voltage amplifier circuit 202, connected to the first terminal of sampling resistor Rs, and its second terminal is the first output terminal of voltage amplifier circuit 202. The control terminal of transistor Mp5 is the second input terminal of voltage amplifier circuit 202, connected to the second terminal of sampling resistor Rs, and its second terminal is the second output terminal of voltage amplifier circuit 202. The first terminal of load resistor RL1 is connected to the second terminal of transistor Mp4, and its second terminal is connected to ground Gnd. The first terminal of load resistor RL2 is connected to the second terminal of transistor Mp5, and its second terminal is connected to ground Gnd.

[0031] In this embodiment, the transconductance gm of the voltage amplifier circuit 202 is obtained by the following formula:

[0032]

[0033] Substituting formula (1) into formula (2) yields the following result:

[0034]

[0035] Assuming the load resistors RL1 = RL2 = RL in the voltage amplifier circuit 202, then according to formula (3), the gain Av of the voltage amplifier circuit 202 can be obtained as follows:

[0036]

[0037] As can be seen from formula (4), the gain of the voltage amplifier circuit 202 in this embodiment is negatively correlated with the resistance value of resistor R0. Since the matching accuracy of resistors is higher in integrated circuit technology and the process coefficient is the same, a high-precision fixed gain that does not change with the PVT (Process, Voltage, Temperature) corner can be obtained according to the above formula (4). In addition, the circuit structure of the voltage amplifier circuit 202 is simpler, and its offset voltage can be easily reduced. Therefore, when the voltage across the sampling resistor Rs is as low as 0V, the voltage amplifier circuit 202 can still work normally and will not be limited by low-voltage operating conditions.

[0038] Furthermore, the feedback output circuit includes an operational amplifier OP1 and a transistor Mn3. Operational amplifier OP1 has an inverting input, a non-inverting input, and an output. Its inverting input is connected to the second terminal of transistor Mp4, its non-inverting input is connected to the second terminal of transistor Mp5, and its output is connected to the control terminal of transistor Mn3. The second terminal of transistor Mn3 is connected to the second terminal of transistor Mp4, and its first terminal is used to output the sampling current. Operational amplifier OP1 operates in a negative feedback loop. Through loop adjustment, the voltage at the second terminal of transistor Mp4 is made equal to the voltage at the second terminal of transistor Mp5 (i.e., the voltage at the first output terminal is equal to the voltage at the second output terminal). Then, the feedback loop formed by operational amplifier OP1 controls transistor Mn3 to inject current Io into the load resistor RL1, thereby generating a sampling current at the first terminal of transistor Mn3.

[0039] Furthermore, the feedback output circuit 203 also includes transistors Mp6 and Mp7. The first terminals of transistors Mp6 and Mp7 are both connected to the power supply voltage Vdd. The second terminal of transistor Mp6 is connected to the first terminal of transistor Mn3. The control terminal of transistor Mp7 is connected to the control terminal and the second terminal of transistor Mp6. Transistors Mp6 and Mp7 form a current mirror to output the current in transistor Mn3 as a sampling current Is through the second terminal of transistor Mp7.

[0040] Furthermore, the voltage across the sampling resistor Rs is amplified by the voltage amplifier circuit 202, and the amplified voltage is Av*Iload*Rs. The design ensures that the operational amplifier OP1 operates in a negative feedback loop. Through loop adjustment, the voltages at the two output ports of the voltage amplifier circuit 202 are equal. Therefore, the feedback loop formed by the operational amplifier OP1 controls the transistor Mn3 to inject current Io into the load resistor RL1.

[0041]

[0042] Assuming the ratio of the current mirror formed by transistors Mp6 and Mp7 is 1:1, then the sampling current Is is:

[0043]

[0044] In the above embodiments, transistors Mp1 to Mp7 are, for example, P-type MOSFETs, and transistors Mn1 to Mn3 are, for example, N-type MOSFETs.

[0045] In summary, the current sampling circuit for the power transistor in this embodiment of the invention includes a sampling resistor, a voltage amplifier circuit, a feedback output circuit, and a current bias circuit. The voltage amplifier circuit amplifies the voltage across the sampling resistor, and the feedback output circuit obtains a sampling current characterizing the current flowing through the power transistor by making the voltages at the two output terminals of the voltage amplifier circuit equal. The current bias circuit provides a bias current to the voltage amplifier circuit based on the first resistor, thereby making the gain of the voltage amplifier circuit negatively correlated with the resistance value of the first resistor. Since resistor matching accuracy is higher in integrated circuit technology, and the process coefficients are the same, a high-precision fixed gain that does not change with PVTcorner can be obtained by controlling the resistance value of the first resistor. Furthermore, the voltage amplifier circuit has a simpler circuit structure, making it easier to reduce its offset voltage. When the voltage across the sampling resistor drops to 0V, the voltage amplifier circuit can still operate normally and is not limited by low-voltage operating conditions, which is beneficial for improving the overall performance of the system.

[0046] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "" or "") depends on whether positive or negative logic is used.

[0047] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A current sampling circuit for a power transistor, comprising: A sampling resistor is connected to the power transistor; A voltage amplifier circuit includes a first input terminal and a second input terminal connected to the two ends of the sampling resistor, respectively. The voltage amplifier circuit is used to amplify the voltage across the sampling resistor and output the amplified voltage through the first output terminal and the second output terminal. A feedback output circuit is connected to the first and second output terminals of the voltage amplifier circuit. The feedback output circuit outputs a sampling current representing the current flowing through the power transistor by making the voltage at the first output terminal equal to the voltage at the second output terminal. The current sampling circuit further includes: A current biasing circuit includes a first resistor for providing a bias current to the voltage amplifier circuit based on the first resistor, such that the voltage amplifier circuit has a gain negatively correlated with the resistance value of the first resistor. The current bias circuit further includes first to fourth transistors, with the first resistor, first transistor, and third transistor sequentially connected between the power supply voltage and ground. The second transistor and the fourth transistor are connected sequentially between the power supply voltage and ground. The first transistor and the second transistor form a current mirror, and the third transistor and the fourth transistor form a current mirror, wherein a high-precision fixed gain that does not change with the PVT corner is obtained by controlling the resistance value of the first resistor.

2. The current sampling circuit according to claim 1, wherein, The first transistor and the second transistor are P-type metal-oxide-semiconductor field-effect transistors, and the third transistor and the fourth transistor are N-type metal-oxide-semiconductor field-effect transistors.

3. The current sampling circuit according to claim 1, wherein, The voltage amplifier circuit includes: The fifth transistor has its first terminal connected to the power supply voltage and its control terminal connected to the common terminal of the second and fourth transistors. The fifth transistor obtains the bias current by mirroring. The sixth transistor and the seventh transistor are provided, with their first terminals connected to the second terminal of the fifth transistor. The control terminal of the sixth transistor is its first input terminal connected to one end of the sampling resistor, and its second terminal is its first output terminal. The control terminal of the seventh transistor is its second input terminal connected to the other end of the sampling resistor, and its second terminal is its second output terminal. A first load resistor, the first terminal of which is connected to the second terminal of the sixth transistor, and the second terminal of which is grounded; and The second load resistor has its first end connected to the second end of the seventh transistor, and its second end grounded.

4. The current sampling circuit according to claim 3, wherein, The fifth transistor, the sixth transistor, and the seventh transistor are all P-type metal-oxide-semiconductor field-effect transistors.

5. The current sampling circuit according to claim 3, wherein, The feedback output circuit includes: An operational amplifier has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is connected to the second terminal of the sixth transistor, and the non-inverting input terminal is connected to the second terminal of the seventh transistor. The eighth transistor has its control terminal connected to the output terminal of the operational amplifier, its second terminal connected to the second terminal of the sixth transistor, and its first terminal used to output the sampling current.

6. The current sampling circuit according to claim 5, wherein, The operational amplifier operates in a negative feedback state so that the voltage at the first output terminal is equal to the voltage at the second output terminal through loop adjustment.

7. The current sampling circuit according to claim 5, wherein, The feedback output circuit also includes: The ninth transistor has its first terminal connected to the power supply voltage and its second terminal connected to the first terminal of the eighth transistor; and The tenth transistor has its first terminal connected to the power supply voltage, and its control terminal connected to the control terminal and second terminal of the ninth transistor. The ninth transistor and the tenth transistor form a current mirror to output the current of the eighth transistor as the sampling current through the second terminal of the tenth transistor.

8. The current sampling circuit according to claim 7, wherein, The eighth transistor is an N-type metal-oxide-semiconductor field-effect transistor, and the ninth and tenth transistors are P-type metal-oxide-semiconductor field-effect transistors.

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