Register transfer level design memory order detection method and device, storage medium and terminal

Abstract

This invention discloses a method, apparatus, storage medium, and terminal for memory order detection in register-transfer level (RTL) designs. The method includes: acquiring signals during the simulation and verification process of the RTL design to be tested, and dynamically generating a detection model based on the signals for memory order detection; upon acquiring a storage operation submission time point signal, converting the submission data signal into local data and storing it in local space; upon acquiring a storage operation globally visible time point signal, converting the local data into globally visible data and storing it in globally visible space; upon acquiring a load operation completion time point, generating a load completion information item based on the execution completion data signal and storing the operation completion information item in the corresponding local load completion information table; and upon acquiring a load operation submission time point signal, reading the load operation completion information item for memory order detection. This invention simplifies the memory order detection process for RTL designs.

Description

Technical Field

[0001] This invention relates to the field of simulation and verification technology for multi-core processors, and in particular to a method, apparatus, storage medium, and terminal for register-transfer level design memory order detection. Background Technology

[0002] Memory access instructions are a major component of the program instruction stream, and efficient execution of these instructions is crucial for processor performance. Modern processors typically employ various mechanisms to improve memory access performance, such as speculative execution of load operations, store-forward, and multi-level caching. In multi-core environments, processors often also implement cache coherency protocols. Despite these optimizations, processors must ensure that memory access instructions adhere to the instruction set architecture's memory ordering, such as Total Store Ordering (TSO) for x86 and RISC-V Weak Memory Ordering (RVWMO) for RISC-V. In instruction set architectures, memory ordering is defined by a set of rules governing the order of load / store operations in multi-core programs. Due to timing constraints, multi-core programs generally have a large execution space, and different executions may yield different results. Memory ordering defines certain invalid execution results, and the processor's RTL implementation must ensure that these invalid results do not occur.

[0003] Currently, simulation verification remains the primary method for testing processor RTL designs. The basic idea is to input appropriate stimuli to the DUT (Design Under Test) containing the RTL, drive its execution, and collect necessary RTL signals during execution. These signals are then compared with a reference model. If a comparison error occurs, it indicates a problem in the RTL implementation; otherwise, the test is considered successful. A reliable reference model is fundamental to simulation verification. For multi-core processor designs, establishing a suitable reference model is a challenging problem when using simulation verification to check memory order. Summary of the Invention

[0004] The technical problem to be solved by this invention is that the simulation verification process of the existing register-transfer level design memory order detection method for multi-core processors requires the establishment of a reference model, which is difficult to achieve. Therefore, it increases the difficulty of implementing the register-transfer level design memory order detection method for multi-core processors.

[0005] To address the aforementioned technical problems, this invention provides a method for memory order detection in register-transfer level designs, comprising:

[0006] During the simulation and verification of the register transfer stage design under test, signals of storage and load operations at preset key time points in the processor pipeline are collected.

[0007] A detection model is dynamically generated based on the collected signals, and the memory order detection of the storage and loading operations is implemented in the detection model.

[0008] The preset key time points for the storage operation are the commit time point and the globally visible time point, and the preset key time points for the loading operation are the execution completion time point and the commit time point.

[0009] The memory order detection steps for dynamically generating a detection model based on the acquired signals and implementing the storage and loading operations in the detection model include:

[0010] After the submission data signal of the storage operation submission time point is collected, it is determined whether there is a local space corresponding to the core processor to which the storage operation belongs. If there is, local data is generated based on the submission data signal and the local data is stored in the corresponding local space. Otherwise, the local space corresponding to the core processor to which the storage operation belongs is created, and local data is generated based on the submission data signal and the local data is stored in the corresponding local space.

[0011] When a globally visible signal command is acquired at the globally visible time point of the storage operation, it is determined whether a globally visible space exists. If it exists, globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. Otherwise, a globally visible space is created, and globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space.

[0012] After the globally visible data is stored in the globally visible space, a memory order check is performed on the corresponding storage operation, and the local data corresponding to the globally visible data is deleted.

[0013] When the execution completion data signal of the loading operation is collected at the time point of execution completion, it is determined whether there is a local loading completion information table corresponding to the core processor to which the loading operation belongs. If it exists, a loading completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. Otherwise, a local loading completion information table corresponding to the core processor to which the current loading operation belongs is created, and a loading completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table.

[0014] When the submission signal instruction of the loading operation submission time point is collected, the loading operation completion information item corresponding to the current loading operation is read from the local loading completion information table corresponding to the current loading operation for memory order detection, and the corresponding loading operation completion information item is deleted from the corresponding local loading completion information table.

[0015] The detection model includes at least one of the local space, the globally visible space, and the local load completion information table.

[0016] Preferably, the register transfer stage to be tested is designed as the entire register transfer stage design of a multi-core processor or as a register transfer stage design related to memory access.

[0017] Preferably, the local space includes a storage operation local information linked list and a storage operation local byte data linked list group, and each of the storage operation local byte data linked lists corresponds to a byte address;

[0018] Generating local data based on the submitted data signal and storing the local data in the corresponding local space includes:

[0019] Obtain the byte address from the submitted data signal, generate the local information item based on the byte address and the local number, and insert the local information item from the head into the storage operation local information necklace table;

[0020] Based on the submission data information in the submission data signal, a local byte data item is generated for each address in the submission data signal, and all the local byte data items are inserted into the storage operation local byte data linked list corresponding to the byte address.

[0021] Preferably, the globally visible space includes a storage operation global information necklace table and a storage operation global byte data linked list group. Each storage operation global byte data linked list corresponds to a byte address, and the global information item in the storage operation global information necklace table serves as the head node, which is sequentially linked with the corresponding global byte data items arranged in a preset order in the storage operation global byte data linked list group to form a doubly linked list.

[0022] Generating globally visible data based on the local data corresponding to the current storage operation includes:

[0023] Obtain the byte address from the local information item, generate a global information item based on the byte address and the global number, and then insert the global information item into the storage operation global information necklace table;

[0024] Global byte data items are generated based on the local byte data items, and all the global byte data items are inserted into the corresponding global byte data linked list of the storage operation.

[0025] Using the global information item as the head node, the global information item and all corresponding global byte data items are linked in a preset order.

[0026] Preferably, performing memory order detection for the corresponding storage operation includes:

[0027] Check whether the local information item of the current storage operation is located at the end of the storage operation local information necklace table in the local space to which the storage operation belongs. If it is, it means that the memory order of the current storage operation is normal; otherwise, it means that the memory order of the current storage operation is violated.

[0028] Preferably, generating a loading operation completion information item based on the execution completion data signal includes:

[0029] Based on the byte address, execution completion data information, and read data nature in the execution completion data signal, a loading operation completion information item is generated;

[0030] The data type read includes local data and global data. When the data type read is global data, the loading operation completion information item also includes a detection data item. The detection data item contains the head local byte data item in the byte data linked list corresponding to all byte addresses in the execution completion data signal in the local space to which the loading operation belongs.

[0031] Preferably, reading the load operation completion information item corresponding to the current load operation from the local load completion information table corresponding to the current load operation for memory order detection includes:

[0032] If the data read from the loading operation completion information item is global data, then the detection data item is searched in the global visible space. If it is found, it means that the memory order of the current loading operation is normal; otherwise, it means that the memory order of the current loading operation is violated.

[0033] If the read data of the load operation completion information item is local data, then the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the storage operation local byte data linked list corresponding to the same byte address in the local space of the core processor to which the current load operation belongs. If all matches are successful, it indicates that the memory order of the current load operation is normal. Otherwise, the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the storage operation local byte data linked list corresponding to the same byte address in the globally visible space. If all matches are successful, it indicates that the memory order of the current load operation is normal. Otherwise, it indicates that the memory order of the current load operation is violated.

[0034] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0035] The memory order detection method for register-transfer level (RTL) designs provided in this invention collects signals at preset key time points during the simulation and verification of the RTL design under test, including storage and load operations. A detection model is then dynamically generated based on the collected signals, and memory order detection is performed within this model. Furthermore, this invention establishes local and globally visible spaces in the detection model for data storage based on storage operations, and establishes a local load completion information table in the detection model based on load operations. Dynamic updates of the data in the detection model are achieved through a specific data storage method, and memory order violations are detected based on rules governing the order relationships between storage and load operations, simplifying the memory order detection process for RTL designs.

[0036] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0037] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0038] Figure 1 A flowchart illustrating the memory order detection method of the register transfer level design according to Embodiment 1 of the present invention is shown;

[0039] Figure 2 This diagram illustrates the key points of the load operation pipeline lifecycle in the register transfer stage design of Embodiment 1 of the present invention.

[0040] Figure 3 This diagram illustrates the key points of the storage operation pipeline lifecycle in Embodiment 1 of the present invention.

[0041] Figure 4 This illustrates the intentional representation of the rule that storage operations cannot be exchanged with other storage operations according to Embodiment 1 of the present invention;

[0042] Figure 5 This illustration shows a schematic representation of the rule that allows load operations in the same core processor to exchange order with older memory operations in different locations, according to Embodiment 1 of the present invention.

[0043] Figure 6 This illustrates the intent of the rule that the order in which storage operations are observed by other core processors must be consistent, as illustrated in Embodiment 1 of the present invention.

[0044] Figure 7 A schematic diagram of the local spatial structure of the detection model according to Embodiment 1 of the present invention is shown;

[0045] Figure 8 This diagram illustrates the globally visible unidirectional linked list structure of the detection model according to Embodiment 1 of the present invention.

[0046] Figure 9 This diagram illustrates the globally visible doubly linked list structure of the detection model according to Embodiment 1 of the present invention.

[0047] Figure 10 This diagram illustrates the structure of the local loading completion information table according to Embodiment 1 of the present invention.

[0048] Figure 11 A schematic diagram of the memory order detection device structure of the register transfer stage design according to Embodiment 2 of the present invention is shown;

[0049] Figure 12 A schematic diagram of the terminal structure of Embodiment 4 of the present invention is shown. Detailed Implementation

[0050] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that, as long as there is no conflict, the various embodiments and features in the various embodiments of the present invention can be combined with each other, and the resulting technical solutions are all within the protection scope of the present invention.

[0051] A typical out-of-order processor core design consists of three main parts: the sequential front end, the out-of-order execution engine, and memory access. The processor core can support either Reduced Instruction Set Computing (RISC) or Complex Instruction Set Computing (CISC). In the sequential front end of the processor core, the branch prediction unit works with the instruction cache, instruction translation buffer, and instruction fetch unit to generate instruction stream data according to a specific window size. The decoding unit is responsible for parsing instructions from the instruction data and translating each instruction into one or more micro-operations, which are then sent to the out-of-order execution engine.

[0052] The processor core's out-of-order execution engine includes a renaming / allocation unit, a scheduler unit, a commit unit, a physical register unit, and an execution unit. The scheduler unit can have different designs; for example, each execution port may have dedicated reservation stations, or a separate design may be used, including an integer scheduler and a floating-point scheduler for scheduling integer and floating-point micro-operations respectively, or a unified scheduler design may be used, where all execution ports share a single scheduler. The physical register unit contains one or more physical register files. Different physical registers store different types of data, such as integer data, floating-point data, packed integer data, packed floating-point data, etc. A typical design may contain only an integer physical register file and a floating-point physical register file. The integer physical register file stores integer data, while the floating-point physical register file can store floating-point data, packed integer data, and packed floating-point data. The execution unit may include multiple execution ports, each containing one or more execution units. The execution unit can perform different types of operations, such as arithmetic operations, floating-point operations, vector integer / floating-point operations, memory address counting, etc. Some specific operations can only be executed on specific ports, while other operations can be executed on multiple ports. In a typical design, ports might be divided into three main categories: integer ports, floating-point ports, and memory access ports. Integer ports can only perform integer operations, floating-point ports can perform floating-point and vector integer / vector floating-point operations, and memory access ports can only perform operations such as address calculation and data movement. In another design, ports might only be divided into arithmetic ports and memory access ports, where arithmetic ports can perform integer, floating-point, vector integer, and vector floating-point operations.

[0053] The processor core's memory access section includes a load / store buffer, a data translation buffer, a data cache, a L2 translation buffer, and a L2 cache. The load / store buffer records the execution status of load and store operations, enabling functions such as speculative execution of load operations, forward propagation of stored data, emission of post-commit store operations, and memory order checks. The load / store buffer can have various designs, such as including dedicated load and store buffers, with the store buffer further divided into a store address buffer and a store data buffer; or using a unified load and store address buffer, while having a separate dedicated store data buffer.

[0054] Example 1

[0055] To address the aforementioned technical problems in the prior art, embodiments of the present invention provide a register-transfer-level design memory order detection method.

[0056] Figure 1 This diagram illustrates a flowchart of a register-transfer-level memory order detection method according to Embodiment 1 of the present invention; see reference. Figure 1 As shown, the register transfer level design memory order detection method of this invention includes the following steps.

[0057] Step S101: Collect signals from preset key time points in the processor pipeline during the simulation verification process of the register transfer stage design under test.

[0058] Specifically, the Register Transfer Level (RTL) design under test is encapsulated within the Device Under Test (DUT), and the DUT is driven to execute using appropriate stimuli. It should be noted that the RTL design under test can be the entire RTL design of a multi-core processor or a RTL design related to memory access. When the RTL design under test includes the entire RTL design of a multi-core processor, its stimuli can use a true multi-core program instruction flow; however, when the RTL design under test only includes RTL designs related to memory access, its stimuli require the construction of micro-operation sequences.

[0059] This invention is applicable to out-of-order processor cores, and out-of-order processor cores can support simultaneous multithreading technology, so that such a physical processor core can be regarded as two logical processor cores.

[0060] The signals for load and store operations are acquired at preset critical time points in the processor pipeline. Although the specific signals may differ in different designs, the key points for the execution of load and store operations are similar across different designs.

[0061] This invention relates to two key points in the lifecycle of a loading operation pipeline: the preset key time points for the loading operation are the execution completion time point and the submission time point. Figure 2 This diagram illustrates key points in the lifecycle of the load operation pipeline in the register transfer stage design of Embodiment 1 of the present invention; Reference Figure 2 As shown, after a load operation enters the execution phase, its execution can be canceled or blocked for various reasons, such as a data transformation buffer miss or a data cache miss. It needs to be rescheduled for execution once the conditions are met; therefore, a load operation may need to be executed multiple times until it is finally completed. Once the load operation is complete and written back, the commit unit needs to confirm that the load operation is not on an incorrect execution path (e.g., a branch prediction error) and that the execution of the load operation and its preceding micro-operations has not encountered any anomalies before committing the load operation. The completion and commit of the load operation signifies the end of the load operation pipeline lifecycle.

[0062] This invention relates to two key points in the lifecycle of a storage operation pipeline: the preset key time points for storage operations are the commit time point and the globally visible time point. Figure 3 This diagram illustrates key points in the lifecycle of the storage operation pipeline according to Embodiment 1 of the present invention; see reference. Figure 3 As shown, the execution of a storage operation is typically divided into two parts: the execution of the storage address operation and the execution of the storage data operation. The former mainly completes the calculation of the linear address and the translation from the linear address to the physical address, while the latter mainly completes the preparation of the storage data. After both parts are completed, the commit unit confirms that the storage operation is not on an incorrect execution path and that the execution of the two micro-operations of the storage operation and the preceding micro-operations has not encountered any anomalies before committing the storage operation. After the storage operation is committed, it still needs to undergo the process of writing data to the cache system so that it can be observed by other cores. Figure 3 The point at which the process becomes globally visible marks the completion of this process. Global visibility signifies the end of the storage operation pipeline's lifecycle.

[0063] During the simulation and verification of the register transfer stage design under test, the commit data signal at the commit time point and the global visibility signal instruction at the global visibility time point of each memory operation in the processor pipeline are collected sequentially to serve as the data basis for dynamically generating the detection model. Similarly, during the simulation and verification of the register transfer stage design under test, the execution completion data signal at the execution completion time point and the commit signal instruction at the commit time point of each load operation in the processor pipeline are also collected sequentially to serve as the data basis for dynamically generating the detection model.

[0064] Step S102: Dynamically generate a detection model based on the collected signals, and implement memory order detection for storage and loading operations in the detection model.

[0065] One of the core components of this invention is the detection model. The detection model includes at least one of the following: local space, globally visible space, and local load completion information table.

[0066] Figure 7 A schematic diagram of the local space structure of the detection model according to Embodiment 1 of the present invention is shown; the local space includes a storage operation local information chain table and a storage operation local byte data chain table group, wherein each storage operation local byte data chain table corresponds to a byte address.

[0067] Upon acquiring the commit data signal at the time of the storage operation commit, the system determines whether a local space corresponding to the core processor to which the current storage operation belongs exists in the current detection model. If it does, local data is generated based on the commit data signal and stored in the corresponding local space. Otherwise, a local space corresponding to the core processor to which the storage operation belongs is created, local data is generated based on the commit data signal, and stored in the corresponding local space. It should be noted that during the construction of the detection model, a local space is created for each core processor to record the byte address of the storage operation commit data signal, the commit data information, and the order of committed storage operations within the same core processor. Only one globally visible space is created in the detection model, shared by all core processors under test, to record the byte address and data information of globally visible storage operations, as well as the global order of globally visible storage operations across all cores.

[0068] Furthermore, generating local data based on the commit data signal and storing the local data in the corresponding local space includes: obtaining the byte address from the commit data signal, generating a local information item based on the byte address and local number, and inserting the local information item into the storage operation local information linked list from the head. The local number is generated in the local space. Then, based on the commit data information in the commit data signal, a local byte data item is generated for each byte address written in the current storage operation, and all local byte data items are inserted into the storage operation local byte data linked list corresponding to the byte address. It should be noted that, in addition to the local number and address information, the local information item may also include information that helps determine the global visibility of the storage operation.

[0069] Figure 8 This diagram illustrates a globally visible unidirectional linked list structure of the detection model according to Embodiment 1 of the present invention; see reference. Figure 8 As shown, the globally visible space includes a global information chain table for storage operations and a group of global byte data chains for storage operations. Each global byte data chain for storage operations corresponds to a byte address. Figure 9 This diagram illustrates a doubly linked list structure in the globally visible space of the detection model according to Embodiment 1 of the present invention; Reference Figure 9As shown, the global information necklace list and the global byte data list for storage operations also have another connection: they form a doubly linked list. The global information item in the global information necklace list serves as the head node, and is sequentially linked to the corresponding global byte data items in the global byte data list arranged in a preset order to form the doubly linked list. Furthermore, the preset order can be in ascending order of byte address.

[0070] When a globally visible signal command is acquired at a globally visible time point of a storage operation, it is necessary to determine whether a globally visible space exists in the current detection model. If it exists, globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. Otherwise, a globally visible space is created, and globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space.

[0071] Furthermore, generating globally visible data based on the local data corresponding to the current storage operation includes: obtaining the byte address from the local information item, generating a global information item based on the byte address and global number, and then inserting the global information item into the storage operation global information chain table. The global number is generated from the global visible space. Then, global byte data items are generated based on the local byte data items, and all global byte data items are inserted into the corresponding storage operation global byte data chain table. A bidirectional link is established between the storage operation global information chain table and the global byte data items. That is, with the global information item as the head node, the global information item and all corresponding global byte data items are linked in a preset order.

[0072] It should be noted that the global byte data item includes an observable vector. The bit width of the observable vector is related to the number of core processors to be tested. The initial value is all 1s, indicating that the data of this byte can be observed by all core processors. As the register-transfer stage design is executed, when it can be determined that the global byte data can no longer be read by a certain core processor, the value of the corresponding bit in the observable vector for that core processor can be set to 0. When all bits in the observable vector are 0, the global byte data item can be deleted. Similarly, when all global byte data items for a certain memory operation cannot be observed, the information item for the memory operation can also be deleted. After the globally visible data is stored in the globally visible space, memory order checks can be performed on the corresponding memory operation, and the local data corresponding to the globally visible data can be deleted.

[0073] In addition, the reference model introduces a local load completion information table for each core processor. Figure 10 This diagram illustrates the structure of the local loading completion information table according to Embodiment 1 of the present invention. (Refer to...) Figure 1 As shown, the local load completion information table includes multiple load completion information items.

[0074] Specifically, when the execution completion data signal of the loading operation is collected, it is determined whether there is a local loading completion information table corresponding to the core processor to which the loading operation belongs. If it exists, a loading completion information item is generated based on the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. Otherwise, a local loading completion information table corresponding to the core processor to which the current loading operation belongs is created, and a loading completion information item is generated based on the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table.

[0075] Furthermore, generating a load operation completion information item based on the execution completion data signal includes: generating the load operation completion information item based on the byte address in the execution completion data signal, the execution completion data information, and the nature of the read data. The nature of the read data can be local data, such as data from an older but not globally visible memory operation in the local processor that was read through the memory-forward mechanism; at the same time, the nature of the read data can also be globally visible data, such as data read directly from the cache. When the nature of the read data is global data, the load operation completion information item also includes a detection data item, which contains the head local byte data item in the byte data linked list corresponding to all byte addresses in the execution completion data signal in the local space to which the load operation belongs.

[0076] When a commit signal command for the time point of the load operation is collected, the corresponding load operation completion information item is read from the local load completion information table corresponding to the current load operation for memory order detection, and the corresponding load operation completion information item is deleted from the corresponding local load completion information table.

[0077] Furthermore, the specific process of checking the memory order of store and load operations is as follows. The instruction architecture memory ordering rules involved in this invention are described in dedicated chapters in the manuals of various instruction set architectures, typically manifesting as several rules concerning the order between load and store operations. Here, we use the x86 instruction architecture's memory ordering as an example, listing three of these rules. Figure 4 , Figure 5 and Figure 6Tables 1, 2, and 3 illustrate the rules. Table 1 emphasizes that memory operations within the same processor core must maintain the order specified by the program; Table 3 emphasizes that memory operations across different processor cores must maintain a consistent order from the perspective of all other processor cores; Table 2 emphasizes that within the same processor core, load operations can skip older memory operations. The rule in Table 2 relates to the load-execution optimization mechanism commonly used in processor microarchitecture design, and this rule is applicable to different instruction set architectures.

[0078] Memory order checks for storage operations can be performed when the operation is globally visible. Taking the rules mentioned in Table 1 as an example, when a storage operation is globally visible, it is necessary to check whether older storage operations on the same core processor are already globally visible. At this time, it is only necessary to check whether the local information entry of the current storage operation is located at the end of the storage operation local information necklace table in the local space to which the storage operation belongs. If so, it means that the memory order of the current storage operation is normal; otherwise, it means that the memory order of the current storage operation is violated.

[0079] The memory order check for the load operation needs to be performed when the load operation is submitted. Taking the rules mentioned in Tables 2 and 3 as examples, the memory order check needs to be performed based on the local load completion information table. If the data read from the load operation completion information item is global data, then the detection data item is searched in the global visible space. If it is found, it means that the memory order of the current load operation is normal; otherwise, it means that the memory order of the current load operation is violated. The detection data item includes the head local byte data item in the byte data linked list corresponding to all byte addresses in the execution completion data signal in the local space to which the load operation belongs.

[0080] If the data read from the load operation completion information item is local data, then the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the local byte data linked list of the storage operation corresponding to the same byte address in the local space of the core processor to which the current load operation belongs. If all matches are successful, it means that the memory order of the current load operation is normal; otherwise, the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the local byte data linked list of the storage operation corresponding to the same byte address in the globally visible space. If all matches are successful, it means that the memory order of the current load operation is normal; otherwise, it means that the memory order of the current load operation is violated.

[0081] The memory order detection method for register-transfer level (RTL) designs provided in this invention collects signals at preset key time points during the simulation and verification of the register-transfer level design under test, and then dynamically generates a detection model based on the collected signals, implementing memory order detection within the detection model. Furthermore, this invention establishes local and globally visible spaces in the detection model for data storage based on storage operations, and establishes a local load completion information table in the detection model based on load operations. Dynamic updates of data in the detection model are achieved through a specific data storage method, and memory order violations are detected based on rules governing the order relationships between storage and load operations, simplifying the memory order detection process for RTL designs.

[0082] Example 2

[0083] To address the aforementioned technical problems in the prior art, this invention also provides a register-transfer-level memory order detection device.

[0084] Figure 11 A schematic diagram of the memory order detection device structure of the register transfer stage design according to Embodiment 2 of the present invention is shown; Reference Figure 11 As shown, the register transfer level design memory order detection device of this invention includes a signal acquisition module and a memory order detection module.

[0085] The signal acquisition module is used to acquire signals from preset key time points in the processor pipeline during the simulation and verification of the register transfer stage design under test.

[0086] The memory order detection module is used to dynamically generate a detection model based on the acquired signals, and to implement memory order detection for storage and loading operations in the detection model.

[0087] The preset key time points for storage operations are the commit time point and the globally visible time point, while the preset key time points for loading operations are the execution completion time point and the commit time point.

[0088] The memory order detection steps, which dynamically generate a detection model based on the acquired signals and implement storage and loading operations within the detection model, include:

[0089] After the commit data signal of the storage operation commit time point is collected, it is determined whether there is a local space corresponding to the core processor to which the storage operation belongs. If it exists, local data is generated based on the commit data signal and stored in the corresponding local space. Otherwise, the local space corresponding to the core processor to which the storage operation belongs is created, local data is generated based on the commit data signal and stored in the corresponding local space.

[0090] When a globally visible signal command is acquired at the globally visible time point of a storage operation, it is determined whether a globally visible space exists. If it exists, globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. Otherwise, a globally visible space is created, and globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space.

[0091] Once the globally visible data is stored in the globally visible space, a memory order check is performed on the corresponding storage operation, and the local data corresponding to the globally visible data is deleted.

[0092] When the execution completion data signal of the loading operation is collected, it is determined whether there is a local loading completion information table corresponding to the core processor to which the loading operation belongs. If it exists, a loading completion information item is generated based on the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. Otherwise, a local loading completion information table corresponding to the core processor to which the current loading operation belongs is created, and a loading completion information item is generated based on the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table.

[0093] When the commit signal command of the loading operation commit time point is collected, the loading operation completion information item corresponding to the current loading operation is read from the local loading completion information table corresponding to the current loading operation for memory order detection, and the corresponding loading operation completion information item is deleted from the corresponding local loading completion information table.

[0094] The detection model includes at least one of the following: local space, globally visible space, and local load completion information table.

[0095] The register-transfer-level (RTL) design memory order detection device provided in this invention collects signals at preset key time points during the simulation and verification of the register-transfer-level design under test, including storage and load operations. It then dynamically generates a detection model based on the collected signals and performs memory order detection within the model. Furthermore, this invention establishes local and globally visible spaces in the detection model for data storage based on storage operations, and establishes a local load completion information table in the detection model based on load operations. This dynamic updating of data in the detection model is achieved through a specific data storage method, and memory order violations are detected based on rules governing the order relationships between storage and load operations, simplifying the register-transfer-level design memory order detection process.

[0096] Example 3

[0097] To address the aforementioned technical problems in the prior art, this embodiment of the invention also provides a storage medium storing a computer program that, when executed by a processor, can implement all the steps in the register transfer level design memory order detection method in Embodiment 1.

[0098] The specific steps of the register-transfer level design memory order detection method and the beneficial effects obtained by applying the readable storage medium provided in this embodiment are the same as in Embodiment 1, and will not be repeated here.

[0099] It should be noted that storage media include various media that can store program code, such as ROM, RAM, magnetic disks, or optical disks.

[0100] Example 4

[0101] To address the aforementioned technical problems in the prior art, this invention also provides a terminal.

[0102] Figure 12 A schematic diagram of the terminal structure of Embodiment 4 of the present invention is shown, with reference to... Figure 12 In this embodiment, the terminal includes a processor and a memory that are interconnected. The memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory, so that when the terminal is executed, it can implement all the steps of the memory order detection method of the register transfer level design in Embodiment 1.

[0103] The specific steps of the register-transfer level design memory order detection method and the beneficial effects obtained by the terminal provided by the embodiment of the present invention are the same as those in Embodiment 1, and will not be repeated here.

[0104] It should be noted that the memory may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Similarly, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0105] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed herein; however, the scope of protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A method for memory order detection in a register-transfer level design, comprising: During the simulation and verification of the register transfer stage design under test, signals of storage and load operations at preset key time points in the processor pipeline are collected. A detection model is dynamically generated based on the collected signals, and the memory order detection of the storage and loading operations is implemented in the detection model. The preset key time points for the storage operation are the commit time point and the globally visible time point, and the preset key time points for the loading operation are the execution completion time point and the commit time point. The memory order detection steps for dynamically generating a detection model based on the acquired signals and implementing the storage and loading operations in the detection model include: After the submission data signal of the storage operation submission time point is collected, it is determined whether there is a local space corresponding to the core processor to which the storage operation belongs. If there is, local data is generated based on the submission data signal and the local data is stored in the corresponding local space. Otherwise, the local space corresponding to the core processor to which the storage operation belongs is created, and local data is generated based on the submission data signal and the local data is stored in the corresponding local space. When a globally visible signal command is acquired at the globally visible time point of the storage operation, it is determined whether a globally visible space exists. If it exists, globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. Otherwise, a globally visible space is created, and globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. After the globally visible data is stored in the globally visible space, a memory order check is performed on the corresponding storage operation, and the local data corresponding to the globally visible data is deleted. When the execution completion data signal of the loading operation is collected at the time point of execution completion, it is determined whether there is a local loading completion information table corresponding to the core processor to which the loading operation belongs. If it exists, a loading operation completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. Otherwise, a local loading completion information table corresponding to the core processor to which the current loading operation belongs is created, and a loading operation completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. When the submission signal instruction of the loading operation submission time point is collected, the loading operation completion information item corresponding to the current loading operation is read from the local loading completion information table corresponding to the current loading operation for memory order detection, and the corresponding loading operation completion information item is deleted from the corresponding local loading completion information table. The detection model includes at least one of the local space, the globally visible space, and the local load completion information table.

2. The detection method according to claim 1, characterized in that, The register transfer stage to be tested is designed as either the entire register transfer stage design for a multi-core processor or a register transfer stage design related to memory access.

3. The detection method according to claim 1, characterized in that, The local space includes a storage operation local information linked list and a storage operation local byte data linked list group, and each of the storage operation local byte data linked lists corresponds to a byte address; Generating local data based on the submitted data signal and storing the local data in the corresponding local space includes: Obtain the byte address from the submitted data signal, generate the local information item based on the byte address and the local number, and insert the local information item from the head into the storage operation local information necklace table; Based on the submission data information in the submission data signal, a local byte data item is generated for each address in the submission data signal, and all the local byte data items are inserted into the local byte data linked list of the storage operation corresponding to the byte address.

4. The detection method according to claim 3, characterized in that, The globally visible space includes a storage operation global information necklace table and a storage operation global byte data linked list group. Each storage operation global byte data linked list corresponds to a byte address, and the global information item in the storage operation global information necklace table serves as the head node, which is sequentially linked with the corresponding global byte data items arranged in a preset order in the storage operation global byte data linked list group to form a doubly linked list. Generating globally visible data based on the local data corresponding to the current storage operation includes: Obtain the byte address from the local information item, generate a global information item based on the byte address and the global number, and insert the global information item into the storage operation global information necklace table; Global byte data items are generated based on the local byte data items, and all the global byte data items are inserted into the corresponding global byte data linked list of the storage operation. Using the global information item as the head node, the global information item and all corresponding global byte data items are linked in a preset order.

5. The detection method according to claim 1, characterized in that, Performing memory order detection for the corresponding storage operation includes: Check whether the local information item of the current storage operation is located at the end of the storage operation local information necklace table in the local space to which the storage operation belongs. If it is, it means that the memory order of the current storage operation is normal; otherwise, it means that the memory order of the current storage operation is violated.

6. The detection method according to claim 1, characterized in that, The loading operation completion information item generated based on the execution completion data signal includes: Based on the byte address, execution completion data information, and read data nature in the execution completion data signal, a loading operation completion information item is generated; The data type read includes local data and global data. When the data type read is global data, the loading operation completion information item also includes a detection data item. The detection data item contains the head local byte data item in the byte data linked list corresponding to all byte addresses in the execution completion data signal in the local space to which the loading operation belongs.

7. The detection method according to claim 6, characterized in that, Reading the load operation completion information item corresponding to the current load operation from the local load completion information table and performing memory order detection includes: If the data read from the loading operation completion information item is global data, then the detection data item is searched in the global visible space. If it is found, it indicates that the memory order of the current loading operation is normal; otherwise, it indicates that the memory order of the current loading operation is violated. If the read data of the load operation completion information item is local data, then the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the storage operation local byte data linked list corresponding to the same byte address in the local space of the core processor to which the current load operation belongs. If all matches are successful, it indicates that the memory order of the current load operation is normal. Otherwise, the execution completion data information corresponding to all byte addresses in the load operation completion information item is matched with the head local byte data item of the storage operation local byte data linked list corresponding to the same byte address in the globally visible space. If all matches are successful, it indicates that the memory order of the current load operation is normal. Otherwise, it indicates that the memory order of the current load operation is violated.

8. A register-transfer-level memory order detection device, characterized in that, Includes a signal acquisition module and a memory sequence detection module. The signal acquisition module is used to acquire signals of storage and loading operations at preset key time points in the processor pipeline during the simulation and verification of the register transfer stage design under test. The memory order detection module is used to dynamically generate a detection model based on the collected signals, and to implement memory order detection of the storage operation and the load operation in the detection model; The preset key time points for the storage operation are the commit time point and the globally visible time point, and the preset key time points for the loading operation are the execution completion time point and the commit time point. The memory order detection steps for dynamically generating a detection model based on the acquired signals and implementing the storage and loading operations in the detection model include: After the submission data signal of the storage operation submission time point is collected, it is determined whether there is a local space corresponding to the core processor to which the storage operation belongs. If there is, local data is generated based on the submission data signal and the local data is stored in the corresponding local space. Otherwise, the local space corresponding to the core processor to which the storage operation belongs is created, and local data is generated based on the submission data signal and the local data is stored in the corresponding local space. When a globally visible signal command is acquired at the globally visible time point of the storage operation, it is determined whether a globally visible space exists. If it exists, globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. Otherwise, a globally visible space is created, and globally visible data is generated based on the local data corresponding to the current storage operation, and the globally visible data is stored in the globally visible space. After the globally visible data is stored in the globally visible space, a memory order check is performed on the corresponding storage operation, and the local data corresponding to the globally visible data is deleted. When the execution completion data signal of the loading operation is collected at the time point of execution completion, it is determined whether there is a local loading completion information table corresponding to the core processor to which the loading operation belongs. If it exists, a loading operation completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. Otherwise, a local loading completion information table corresponding to the core processor to which the current loading operation belongs is created, and a loading operation completion information item is generated according to the execution completion data signal and the operation completion information item is stored in the corresponding local loading completion information table. When the submission signal instruction of the loading operation submission time point is collected, the loading operation completion information item corresponding to the current loading operation is read from the local loading completion information table corresponding to the current loading operation for memory order detection, and the corresponding loading operation completion information item is deleted from the corresponding local loading completion information table. The detection model includes at least one of the local space, the globally visible space, and the local load completion information table.

9. A storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements any one of the register transfer level design memory order detection methods in claims 1 to 7.

10. A terminal, characterized in that, include: A processor and a memory, wherein the memory and the processor are communicatively connected; The memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to enable the terminal to perform the register transfer level design memory order detection method as claimed in any one of claims 1 to 7.

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