Super junction VDMOS device and manufacturing method thereof

Abstract

The present invention provides a superjunction VDMOS device and a manufacturing method thereof, which are applied in the semiconductor field. In the manufacturing method of the superjunction VDMOS device provided by the present invention, the thickness of a second epitaxial layer located above the drift region for forming a P-boyd body region is increased, or before forming the second epitaxial layer, the thickness of the top portion of the first epitaxial layer forming the drift region is inverted into a barrier layer by ion implantation, thereby separating the P-boyd body region from the P-type column in the drift region so that the two are not connected. This prevents the continued diffusion of the P-boyd body depletion layer, which causes the overshoot problem caused by the direct extraction of holes in the drift region through the P-boyd body region when the superjunction VDMOS is in the reverse off state. In other words, the overshoot phenomenon of the superjunction VDMOS device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a super junction VDMOS device and a manufacturing method thereof. Background Art

[0002] For conventional VDMOS, as the breakdown voltage increases, the resistivity and thickness of the epitaxial layer need to increase, resulting in a large on-resistance. The relationship between on-resistance and breakdown voltage is: R∝BV 2.5 This is commonly referred to as the "silicon limit." Therefore, to reduce on-resistance or break through the silicon limit, the current mainstream technology is superjunction technology. Superjunction VDMOS is a very important power device in the medium and high voltage fields. Its basic structure consists of alternating P-type pillars (P-pillar) and N-type pillars (N-pillar) forming a drift region. It follows the basic principle of charge balance and breaks through the limitations of traditional structures (Ron-BV) under the silicon limit, reducing on-resistance. This reduced resistance, accompanied by enhanced current saturation capability, makes superjunction VDMOS particularly attractive for PWM and motor control applications.

[0003] However, similar to traditional VDMOS devices, super-junction VDMOS devices also have a large parasitic body diode. When reverse bias occurs in peripheral circuit applications, that is, when the source is connected to a high potential, the drain is connected to a low potential, and the gate is connected to zero potential, this parasitic body diode will start to operate. This operating mode is usually called the reverse conduction state of super-junction VDMOS. As a result, when the super-junction VDMOS device is turned off, its current rise rate (di / dt) is too large, which is the overshoot problem of the super-junction VDMOS device.

[0004] To address this issue, the existing technology is to adjust the gate-drain capacitance Cgd by changing it. Specifically, it is achieved by adjusting the manufacturing process of the P column and / or N column in the drift region to adjust the concentration distribution of the P column and / or N column to adjust the lateral depletion rate of the super junction VDMOS, which will affect the upper limit of the breakdown voltage BV and the sensitivity of the entire device to the concentration of the P column and / or N column. Summary of the Invention

[0005] The object of the present invention is to provide a super junction VDMOS device and a manufacturing method thereof, so as to improve the overshoot phenomenon of the super junction VDMOS device.

[0006] In a first aspect, to solve the above technical problems, the present invention provides a method for manufacturing a super junction VDMOS device, the manufacturing method comprising:

[0007] Providing a substrate having a first conductivity type, and forming a first epitaxial layer having the first conductivity type on a surface of the substrate;

[0008] Preparing a drift region consisting of alternating P-type columns and N-type columns in the first epitaxial layer;

[0009] forming a second epitaxial layer having a first conductivity type on a surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process, so that the formed P-boyd body region is not connected to the P-type pillar in the drift region;

[0010] The substrate including the second epitaxial layer is subjected to subsequent processing to form an electrical structure including a source, a drain and a gate.

[0011] Furthermore, the first conductivity type may be N-type.

[0012] Furthermore, the step of forming a second epitaxial layer having the first conductivity type on the surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process so that the formed P-boyd body region is not connected to the P-type pillar in the drift region may include:

[0013] forming a third epitaxial layer of the first conductivity type with a thicker preset thickness on the surface of the first epitaxial layer, and using the third epitaxial layer as the second epitaxial layer;

[0014] A P-boyd body region is formed in the third epitaxial layer by an ion implantation process or a diffusion process. The depth of the P-boyd body region in a direction perpendicular to the substrate is less than the thickness of the third epitaxial layer.

[0015] Furthermore, the preset thickness of the third epitaxial layer ranges from 4 μm to 12 μm.

[0016] Furthermore, the doping concentration of the third epitaxial layer is lower than the doping concentration of the first epitaxial layer, and the implantation dosage of N-type doping ions in the third epitaxial layer and the first epitaxial layer is the same.

[0017] Furthermore, the step of forming a second epitaxial layer having the first conductivity type on the surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process so that the formed P-boyd body region is not connected to the P-type pillar in the drift region may include:

[0018] forming a barrier layer on the surface of the first epitaxial layer by an oxidation process;

[0019] performing an ion implantation process on the first epitaxial layer on which the barrier layer is formed, and allowing the implanted ions to diffuse through the barrier layer to a top portion of the first epitaxial layer, so as to form an inversion blocking layer of a certain thickness on a top portion of the first epitaxial layer;

[0020] removing the blocking layer, and forming a fourth epitaxial layer having the first conductivity type on the surface of the inversion blocking layer, and using the fourth epitaxial layer as the second epitaxial layer;

[0021] A P-boyd body region is formed in the fourth epitaxial layer by an ion implantation process or a diffusion process, wherein a depth of the P-boyd body region in a direction perpendicular to the substrate is less than or equal to a thickness of the fourth epitaxial layer.

[0022] Furthermore, the ions implanted in the ion implantation process performed on the first epitaxial layer on which the barrier layer is formed are N-type ions, and the N-type ions are phosphorus ions.

[0023] Furthermore, the implantation energy of the ion implantation process performed on the first epitaxial layer formed with the barrier layer may be 200K to 500K, and the implantation dose may be 1E12 to 1E14.

[0024] Furthermore, the thickness of the fourth epitaxial layer may range from 2 μm to 8 μm.

[0025] In a second aspect, based on the method for preparing a super junction VDMOS device as described above, the present invention further provides a super junction VDMOS device formed using the method for preparing a semiconductor device.

[0026] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0027] In the manufacturing method of the super junction VDMOS device provided by the present invention, the thickness of the second epitaxial layer located above the drift region for forming the P-boyd body region is thickened or before forming the second epitaxial layer, the thickness of the top part of the first epitaxial layer forming the drift region is inverted into a barrier layer by ion implantation, thereby separating the P-boyd body region from the P-type column in the drift region so that the two are not connected, thereby preventing the continued diffusion of the depletion layer of the P-boyd body region, which causes the overshoot problem caused by the direct extraction of holes in the drift region through the P-boyd body region when the super junction VDMOS is in the reverse off state, that is, improving the overshoot phenomenon of the super junction VDMOS device.

[0028] Moreover, the manufacturing method of the super-junction VDMOS device provided by the present invention is simple and fast, and there is no need to adjust the doping concentration of the P-type column or the N-type column in the drift region. Therefore, existing products and processes can be directly transplanted with the solution provided by the present invention to see improvement effects, and there is no effect on the upper limit of the breakdown voltage BV and the sensitivity of the super-junction VDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a flow chart of a method for manufacturing a super junction VDMOS device provided by the present invention;

[0030] Figure 2a to Figure 2f 1 is a schematic structural diagram of a super junction VDMOS device during the manufacturing process according to one embodiment of the present invention;

[0031] The accompanying drawings are numerals as follows:

[0032] 100 - a substrate having a first conductivity type; 110 - a first epitaxial layer;

[0033] 120a-third epitaxial layer; 120b-fourth epitaxial layer;

[0034] P-pillar / 1-P type pillar; N-pillar / 2-N type pillar;

[0035] 130-blocking layer; 111-inversion blocking layer;

[0036] Source-source; Drain-drain;

[0037] Gate-gate; 3-P-boyd body region. DETAILED DESCRIPTION

[0038] As described in the background technology, similar to traditional VDMOS devices, super-junction VDMOS devices also have a large parasitic body diode. When reverse bias occurs in peripheral circuit applications, that is, when the source is connected to a high potential, the drain is connected to a low potential, and the gate is connected to zero potential, this parasitic body diode will start to operate. This operating mode is usually called the reverse conduction state of super-junction VDMOS.

[0039] Specifically, when the potential difference between the P-body / N-drift region exceeds the built-in potential of a conventional PN junction (approximately 0.7V), the P-body and P-pillar emit holes into the drift region. At this point, the substrate (N+sub) is at a low potential, and the holes flow toward the drain under the action of the electric field. To maintain electrical neutrality in the drift region, the N+ substrate also begins to emit electrons into the drift region. The holes and electrons create a conductivity modulation effect within the drift region, causing the resistance in the drift region to drop rapidly, resulting in a very low reverse conduction voltage drop. Due to the introduction of the superjunction P-pillar region, the emission efficiency is enhanced when hole injection occurs. This means that when the superjunction device is reverse-conducting, the number of holes injected into the N-pillar drift region, i.e., the N-pillar region, is far greater than the number of holes injected into the N-pillar drift region in a conventional VDMOS. Consequently, when the superjunction VDMOS device is turned off, its current rise rate (di / dt) is excessively large, which is the overshoot problem in the superjunction VDMOS device.

[0040] The reverse recovery process of a superjunction VDMOS is essentially the turn-off process of the body diode. When the diode transitions from reverse conduction to reverse cutoff, it first releases the residual carriers (Qrr) stored in the drift region. This process requires a period of time known as the discharge time, also known as the reverse recovery time (Trr). During this period, current flows in the reverse direction through the diode. Holes are repelled into the P-body well by the high-voltage electric field at the drain and eventually flow out of the source. Electrons are attracted to the N+sub substrate by the high-voltage electric field at the drain and eventually flow out of the drain. This process continues until all holes in the drift region are completely extracted. Because the number of hole-electron pairs injected into the superjunction N-pillar of the device during reverse conduction is far greater than that of conventional VDMOS, the superjunction VDMOS consumes more energy during reverse recovery to extract the excess carriers.

[0041] To address this issue, the existing technology is to adjust the gate-drain capacitance Cgd by changing it. Specifically, it is achieved by adjusting the manufacturing process of the P column and / or N column in the drift region to adjust the concentration distribution of the P column and / or N column to adjust the lateral depletion rate of the super junction VDMOS, which will affect the upper limit of the breakdown voltage BV and the sensitivity of the entire device to the concentration of the P column and / or N column.

[0042] To this end, the present invention provides a super junction VDMOS device and a manufacturing method thereof, so as to improve the overshoot phenomenon of the super junction VDMOS device.

[0043] refer to Figure 1 , Figure 1 A flow chart of a method for manufacturing a superjunction VDMOS device provided in an embodiment of the present invention. Specifically, the method for manufacturing a superjunction VDMOS device includes the following steps:

[0044] In step S100 , a substrate having a first conductivity type is provided, and a first epitaxial layer having the first conductivity type is formed on a surface of the substrate.

[0045] Step S200 , preparing a drift region consisting of alternating P-type columns and N-type columns in the first epitaxial layer.

[0046] Step S300, forming a second epitaxial layer having a first conductivity type on the surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer through an ion implantation process or a diffusion process, so that the formed P-boyd body region is not connected to the P-type column in the drift region.

[0047] Step S400 , performing subsequent processes on the substrate including the second epitaxial layer to form an electrical structure including a source, a drain, and a gate.

[0048] That is, in the manufacturing method of the super junction VDMOS device provided by the present invention, the thickness of the second epitaxial layer located above the drift region for forming the P-boyd body region is thickened or before forming the second epitaxial layer, the thickness of the top part of the first epitaxial layer forming the drift region is inverted into a barrier layer by ion implantation, thereby separating the P-boyd body region from the P-type column in the drift region so that the two are not connected, thereby preventing the continued diffusion of the depletion layer of the P-boyd body region, which causes the overshoot problem caused by the direct extraction of holes in the drift region through the P-boyd body region when the super junction VDMOS is in the reverse off state, that is, improving the overshoot phenomenon of the super junction VDMOS device.

[0049] The following is combined with Figures 2a to 2f The following further describes the method for manufacturing the superjunction VDMOS device proposed in the present invention in detail. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0050] Figure 2a to Figure 2f FIG1 is a schematic structural diagram of a super junction VDMOS device during the manufacturing process according to an embodiment of the present invention.

[0051] In step S100, refer to Figure 2aAs shown, a substrate 100 having a first conductivity type is provided. Substrate 100 is used to provide an operating platform for subsequent VDMOS device generation processes. Substrate 100 is a semiconductor substrate, and its material is selected from single crystal silicon, polycrystalline silicon, or amorphous silicon. Substrate 100 may also be selected from compounds such as silicon, germanium, gallium arsenide, or germanium-silicon. The material of substrate 100 may also be a material suitable for process requirements or ease of integration. Furthermore, substrate 100 is an N-type heavily doped semiconductor substrate. Subsequently, a first epitaxial layer 110 of a predetermined thickness is formed on the surface of substrate 100 through an epitaxial growth process to form a drift region in subsequent steps.

[0052] In this embodiment, after providing the substrate 100, N-type ion implantation can be performed on the substrate 100 to form an N-type heavily doped semiconductor substrate, and then an epitaxial process is used to form a first epitaxial layer 110 with the same doping ion type as the substrate 100 on the surface of the heavily doped substrate 100.

[0053] In step S200, continue to refer to Figure 2a As shown, a drift region consisting of alternating P-type pillars (P-pillars) 1 and N-type pillars (N-pillars) 2 is prepared in the first epitaxial layer 110 .

[0054] In this embodiment, after forming the first N-type doped epitaxial layer 110 in step S100, one or more grooves can be etched in the first epitaxial layer 110 using a photolithography and / or etching process. Then, the grooves are filled to form a plurality of P-type pillars (P-pillars) 1. The P-type pillars (P-pillars) 1 and the N-type pillars (N-pillars) 2 are alternately distributed to form a drift region, as shown in FIG. Figure 2a shown.

[0055] In step S300, a second epitaxial layer having a first conductivity type is formed on the surface of the first epitaxial layer 110, and a P-boyd body region is formed in the second epitaxial layer through an ion implantation process or a diffusion process, so that the formed P-boyd body region is not connected to the P-type pillar 1 (P-pillar) in the drift region.

[0056] In this embodiment, through research, the present invention researchers discovered that the cause of the overshoot phenomenon in the superjunction VDMOS device is specifically that the P-boyd body region formed in the prior art is connected to the P-pillar located in the drift region. As a result, when the superjunction VDMOS device is turned off, holes and / or electrons in the drift region are directly extracted by the P-boyd body region, resulting in an excessively large current rise rate (di / dt), which is the problem of overshoot in the superjunction VDMOS device. Based on this, the present invention researchers proposed that the P-boyd body region can be separated from the P-pillar 1 in the drift region so that the two are not connected. As a result, the holes in the P-pillar 1 in the drift region cannot be directly extracted through the P-boyd body region. As a result, charge storage is formed on the epitaxial layer (the second epitaxial layer or the inversion blocking layer located on top of the first epitaxial layer 110), and a phenomenon similar to conductivity modulation occurs in this section of the epitaxial layer. When the device is reversely turned off, the holes and electrons in this charge storage layer will be slowly drawn away, thereby improving the overshoot phenomenon of the super junction VDMOS device.

[0057] Optionally, in the present invention, researchers of the present invention propose two implementation methods for realizing that the P-boyd body region is not connected to the P-pillar (P-pillar) 1 in the drift region.

[0058] Method 1: The researchers of the present invention proposed that when the depth of the P-boyd body region is certain, the purpose of disconnecting the P-boyd body region from the P-pillar 1 in the drift region can be achieved by thickening the second epitaxial layer formed on the surface of the first epitaxial layer 110.

[0059] Specifically, such as Figure 2b As shown, after preparing a drift region consisting of alternating P-type pillars (P-pillars) 1 and N-type pillars (N-pillars) 2 in the first epitaxial layer 110 in step S200, a third epitaxial layer 120a of the first conductivity type with a thickened preset thickness can be directly formed on the surface of the first epitaxial layer 110, and the third epitaxial layer 120a can be used as the second epitaxial layer. Figure 2c As shown, an electrical structure including a P-boyd body region 3, a source Sourse, a drain Drain and a gate Gate is formed in the third epitaxial layer 120a through an ion implantation process or a diffusion process.

[0060] The depth of the P-boyd body region 3 in a direction perpendicular to the substrate 100 is less than the thickness of the third epitaxial layer 120a. Specifically, the preset thickness of the third epitaxial layer 120a can range from 4 μm to 12 μm. Furthermore, the doping concentration of the third epitaxial layer 120a is lower than the doping concentration of the first epitaxial layer 110. The purpose of using a third epitaxial layer 120a with a lower doping concentration is to enable the depletion layer of the P-boyd body region and the third epitaxial layer 120a to expand as quickly as possible during reverse withstand voltage, contacting the P-type pillar at the bottom, and continuing the depletion layer expansion to form the superjunction structure provided by the present invention. The N-type dopant ions implanted in the third epitaxial layer 120a and the first epitaxial layer 110 are the same, while the doping concentration of the P-boyd body region is lower than 3E14 cm-3.

[0061] Method 2: The researchers of the present invention proposed that in the case where the depth of the P-boyd body region is variable, an inversion barrier layer of a certain thickness can be formed on the top of the first epitaxial layer 110 by ion implantation to achieve the purpose of disconnecting the P-boyd body region from the P-pillar in the drift region.

[0062] Specifically, such as Figure 2d As shown, after preparing a drift region consisting of alternating P-type pillars (P-pillar) 1 and N-type pillars (N-pillar) 2 in the first epitaxial layer 110 in step S200, a barrier layer 130 is formed on the surface of the first epitaxial layer 110 by an oxidation process. The material of the barrier layer 130 can be silicon dioxide. Then, as shown in FIG. Figure 2e As shown, the first epitaxial layer 110 having the barrier layer 130 is subjected to an ion implantation process, and the implanted ions are diffused through the barrier layer 130 to the top of the first epitaxial layer 110 to form an inversion blocking layer 111 of a certain thickness on the top of the first epitaxial layer 110; thereafter, as shown Figure 2f As shown, the barrier layer 130 is then removed, and a fourth epitaxial layer 120b having the first conductivity type is formed on the surface of the inversion blocking layer 111, and the fourth epitaxial layer 120b serves as the second epitaxial layer. Finally, an electrical structure including a P-boyd body region 3, a source electrode Source, a drain electrode Drain, and a gate electrode Gate is formed in the fourth epitaxial layer 120b through an ion implantation process or a diffusion process. The doping type of the inversion blocking layer 111 is the same as that of the first epitaxial layer 110, that is, it is an N-type inversion blocking layer.

[0063] The depth of the P-boyd body region 3 formed in the second method in a direction perpendicular to the substrate 100 is less than or equal to the thickness of the fourth epitaxial layer 120 b. The thickness of the fourth epitaxial layer 120 b can range from 2 μm to 8 μm. That is, when the second method is used, the thickness of the fourth epitaxial layer 120 b formed is a conventional thickness and is not thickened.

[0064] Furthermore, the type of ions implanted in the ion implantation process for the first epitaxial layer 110 on which the barrier layer 130 is formed may be N-type ions, and the N-type ions may be phosphorus ions; and the implantation energy of the ion implantation process for the first epitaxial layer 110 on which the barrier layer 130 is formed may be 200K to 500K, and the implantation dose may be 1E12 to 1E14.

[0065] It is understood that in the second embodiment of the present invention, the barrier layer 130 is first formed, and the purpose of forming the inversion blocking layer 111 is to prevent the high-energy N-type implanted ions from excessively diffusing in the first epitaxial layer 110 formed with the barrier layer 130 during the ion implantation process, thereby causing the implanted N-type ions to diffuse through the drift region into the substrate 100, thereby causing device failure. However, if the implantation dose and implantation energy of the ion implantation process can be well controlled, the second embodiment provided by the present invention can also not form the barrier layer 130, but directly perform ion implantation on the first epitaxial layer 110 to form the inversion blocking layer 111 on top of the first epitaxial layer 110. This is not specifically limited by the present invention.

[0066] From the above content, it can be seen that the present invention thickens the thickness of the second epitaxial layer located above the drift region for forming the P-boyd body region (the third epitaxial layer 120a) or, before forming the second epitaxial layer, first inverts the thickness of the top part of the first epitaxial layer forming the drift region into a barrier layer 111 by ion implantation, thereby separating the P-boyd body region from the P-type column in the drift region so that the two are not connected, preventing the continued diffusion of the depletion layer of the P-boyd body region, resulting in the overshoot problem caused by the direct extraction of holes in the drift region through the P-boyd body region when the super-junction VDMOS is in the reverse off state, that is, improving the overshoot phenomenon of the super-junction VDMOS device.

[0067] In step S400, refer to Figure 2c or Figure 2f As shown, the substrate 100 including the second epitaxial layer is subjected to subsequent processes to form an electrical structure including a source electrode, a drain electrode, and a gate electrode.

[0068] In this embodiment, since the innovation of the present invention mainly lies in the two implementation methods described above, the invention step of performing subsequent processing on the substrate 100 including the second epitaxial layer to form an electrical structure including a source electrode, a drain electrode, and a gate electrode can adopt the existing conventional method for forming a VDMOS device, and the present invention will not describe this in detail.

[0069] Based on the above-mentioned method for preparing a superjunction VDMOS device, the present invention further provides a superjunction VDMOS device. The specific formation method adopts the above-disclosed method for preparing a superjunction VDMOS device, which will not be repeated here.

[0070] To sum up, in the manufacturing method of the super junction VDMOS device provided by the present invention, the thickness of the second epitaxial layer located above the drift region for forming the P-boyd body region is thickened or before forming the second epitaxial layer, the thickness of the top part of the first epitaxial layer forming the drift region is inverted into a barrier layer by ion implantation, thereby separating the P-boyd body region from the P-type column in the drift region so that the two are not connected, thereby preventing the continued diffusion of the depletion layer of the P-boyd body region, resulting in the overshoot problem caused by the direct extraction of holes in the drift region through the P-boyd body region when the super junction VDMOS is in the reverse off state, that is, improving the overshoot phenomenon of the super junction VDMOS device.

[0071] Moreover, the manufacturing method of the super-junction VDMOS device provided by the present invention is simple and fast, and there is no need to adjust the doping concentration of the P-type column or the N-type column in the drift region. Therefore, existing products and processes can be directly transplanted with the solution provided by the present invention to see improvement effects, and there is no effect on the upper limit of the breakdown voltage BV and the sensitivity of the super-junction VDMOS device.

[0072] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of protection of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the present invention.

[0073] In addition, it should be understood that, although the terms "first", "second", etc. may be used herein to describe different elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of exemplary embodiments of the present invention, the first element, component, region, layer or part discussed below may also be referred to as the second element, component, region, layer or part.

[0074] For ease of description, spatially relative terms such as "below," "above," "below," "above," "upper," and "lower" may be used herein to describe the spatial positional relationship of an element or feature to other elements or features as shown in the figures. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawings is inverted, an element described as "below other elements or features" or "below other elements or features" will be subsequently positioned as "above other elements or features" or "above other elements or features." Thus, the exemplary term "below" may include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0075] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0076] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a super junction VDMOS device, characterized in that: include: Providing a substrate having a first conductivity type, and forming a first epitaxial layer having the first conductivity type on a surface of the substrate; Preparing a drift region consisting of alternating P-type columns and N-type columns in the first epitaxial layer; forming a second epitaxial layer having a first conductivity type on a surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process, so that the formed P-boyd body region is not connected to the P-type pillar in the drift region; performing subsequent processes on the substrate including the second epitaxial layer to form an electrical structure including a source, a drain, and a gate; The step of forming a second epitaxial layer having a first conductivity type on a surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process so that the formed P-boyd body region is not connected to the P-type pillar in the drift region includes: forming a barrier layer on the surface of the first epitaxial layer by an oxidation process; performing an ion implantation process on the first epitaxial layer on which the barrier layer is formed, and allowing the implanted ions to diffuse through the barrier layer to a top portion of the first epitaxial layer, so as to form an inversion blocking layer of a certain thickness on a top portion of the first epitaxial layer; removing the blocking layer, and forming a fourth epitaxial layer having the first conductivity type on the surface of the inversion blocking layer, and using the fourth epitaxial layer as the second epitaxial layer; A P-boyd body region is formed in the fourth epitaxial layer by an ion implantation process or a diffusion process, wherein a depth of the P-boyd body region in a direction perpendicular to the substrate is less than or equal to a thickness of the fourth epitaxial layer.

2. The manufacturing method according to claim 1, characterized in that The first conductivity type is N type.

3. The manufacturing method according to claim 1, wherein: The step of forming a second epitaxial layer having a first conductivity type on a surface of the first epitaxial layer, and forming a P-boyd body region in the second epitaxial layer by an ion implantation process or a diffusion process, so that the formed P-boyd body region is not connected to the P-type pillar in the drift region, comprises: forming a third epitaxial layer of the first conductivity type with a thicker preset thickness on the surface of the first epitaxial layer, and using the third epitaxial layer as the second epitaxial layer; A P-boyd body region is formed in the third epitaxial layer by an ion implantation process or a diffusion process. The depth of the P-boyd body region in a direction perpendicular to the substrate is less than the thickness of the third epitaxial layer.

4. The manufacturing method according to claim 3, wherein: The preset thickness of the third epitaxial layer ranges from 4 μm to 12 μm.

5. The manufacturing method according to claim 4, wherein: The doping concentration of the third epitaxial layer is lower than the doping concentration of the first epitaxial layer, and the implantation dosage of N-type doping ions in the third epitaxial layer and the first epitaxial layer is the same.

6. The manufacturing method according to claim 1, wherein: The ions implanted in the ion implantation process performed on the first epitaxial layer having the barrier layer formed thereon are N-type ions, and the N-type ions are phosphorus ions.

7. The manufacturing method according to claim 6, wherein: The ion implantation process performed on the first epitaxial layer formed with the barrier layer has an implantation energy of 200K to 500K and an implantation dose of 1E12 to 1E14.

8. The manufacturing method according to claim 1, wherein: The thickness of the fourth epitaxial layer ranges from 2 μm to 8 μm.

9. A super junction VDMOS device, characterized in that: The super junction VDMOS device is manufactured using the manufacturing method of any one of claims 1 to 8.

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