Metal grid array and its preparation method, thin film sensor and its preparation method

Abstract

The present disclosure provides a metal grid array and a preparation method thereof, a thin film sensor and a preparation method thereof, and belongs to the technical field of electronic devices. The preparation method of the metal grid array disclosed in the present disclosure includes: providing a substrate; forming a first metal layer on the substrate as a seed layer; forming a first interlayer dielectric layer on the side of the seed layer away from the substrate; the first interlayer dielectric layer includes a plurality of first groove structures and a plurality of second groove structures located in a working area and cross-arranged; performing an electroplating process on the seed layer to form a first metal wire located in the first groove structure and a second metal wire located in the second groove structure; the first metal wire and the second metal wire in each working area are cross-arranged to form a plurality of metal grids.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of electronic devices, and particularly relates to a metal grid array and a method for preparing the same, a thin film sensor and a method for preparing the same. Background Art

[0002] Currently, the line width of the micro-nano processing technology commonly used in the glass-based semiconductor industry is about 2-3 μm. However, some thin film display and sensor devices have higher requirements for the line width of micro-nano processing, such as transparent antennas or radio frequency devices. The former mainly uses narrow line width metal grids as signal transmitting and receiving units, while the latter applies a narrower channel length in radio frequency devices to achieve a higher cut-off frequency. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a metal grid array and a method for preparing the same, a thin film sensor and a method for preparing the same.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for preparing a metal grid array. The metal grid array includes a plurality of working areas and a plurality of redundant areas; the working areas and the redundant areas are alternately arranged in both a first direction and a second direction; wherein, the preparation method includes:

[0005] Providing a substrate;

[0006] Forming a first metal layer on the substrate as a seed layer;

[0007] Forming a first interlayer dielectric layer on a side of the seed layer facing away from the substrate; the first interlayer dielectric layer includes a plurality of first groove structures and a plurality of second groove structures that are located in the working areas and cross each other;

[0008] Performing an electroplating process on the seed layer to form first metal lines located in the first groove structures and second metal lines located in the second groove structures; the first metal lines and the second metal lines in each of the working areas cross each other to form a plurality of metal grids.

[0009] Optionally, the first interlayer dielectric layer further includes a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant areas and have cross-set extending directions, and a plurality of dividing blocks located at cross positions of the extending directions of the third groove structures and the fourth groove structures; the dividing blocks divide both the third groove structures and the fourth groove structures into a plurality of groove portions;

[0010] When performing the electroplating process on the seed layer to form first metal lines located in the first groove structures and second metal lines located in the second groove structures, it further includes:

[0011] Form a third metal line located in the third groove structure and a fourth metal line located in the fourth groove structure; the third metal line and the fourth metal line are arranged to be disconnected at their crossing positions; the extending directions of the third metal lines and the fourth metal lines in each of the redundant regions are arranged to cross each other to form a plurality of redundant metal grids.

[0012] Optionally, the step of forming the first interlayer dielectric layer includes:

[0013] Form, by a hard mask exposure process and an inductively coupled plasma etching process, a plurality of first groove structures and a plurality of second groove structures that are located in the working area and cross each other on the first interlayer dielectric layer; and / or form a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have extending directions that cross each other.

[0014] Optionally, the step of forming the first interlayer dielectric layer includes:

[0015] Form, by a nanoimprint process and an inductively coupled plasma etching process, a plurality of first groove structures and a plurality of second groove structures that are located in the working area and cross each other on the interlayer dielectric layer; and / or form a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have extending directions that cross each other.

[0016] Optionally, the step of forming a seed layer on the substrate includes:

[0017] Deposit a first metal layer on one side of the substrate, and the first metal layer covers the substrate;

[0018] After performing an electroplating process on the seed layer to form a first metal line located in the first groove structure and a second metal line located in the second groove structure, further include:

[0019] Strip the substrate;

[0020] Remove the seed layer material outside the first groove structure and the second groove structure located in the first interlayer dielectric layer.

[0021] Optionally, the step of forming a seed layer on the substrate includes:

[0022] Deposit a first metal layer on one side of the substrate, and form a plurality of metal patterns through a patterning process;

[0023] Form a first interlayer dielectric layer on the side of the seed layer facing away from the substrate; in the step of the first interlayer dielectric layer including a plurality of first groove structures and a plurality of second groove structures that are located in the working area and cross each other, both the first groove structures and the second groove structures are correspondingly arranged with the metal patterns.

[0024] Optionally, after providing a substrate, it further includes:

[0025] Forming a second metal layer on one side of the substrate;

[0026] Forming a first metal layer on the substrate as a seed layer specifically includes:

[0027] Forming a first metal layer on the side of the second metal layer facing away from the substrate, and the orthographic projection of the first metal layer on the substrate coincides with the orthographic projection of the second metal layer on the substrate.

[0028] Optionally, before the step of forming a second metal layer on one side of the substrate, it further includes:

[0029] Forming a separation layer on the substrate, and the separation layer covers the substrate.

[0030] Optionally, after forming a plurality of the metal grids, it further includes:

[0031] Forming a flexible film on the side of the first interlayer dielectric layer facing away from the substrate.

[0032] Optionally, after forming a plurality of the redundant metal grids, it further includes:

[0033] Forming a flexible film on the side of the first interlayer dielectric layer facing away from the substrate.

[0034] In a second aspect, an embodiment of the present disclosure provides a metal grid array, the metal grid array includes a plurality of working areas and a plurality of redundant areas; the working areas and the redundant areas are alternately arranged in both the first direction and the second direction; wherein, the metal grid array includes:

[0035] A substrate;

[0036] A first metal layer disposed on the substrate;

[0037] A first interlayer dielectric layer disposed on the side of the first metal layer facing away from the substrate, the first interlayer dielectric layer includes a plurality of first groove structures and a plurality of second groove structures located in the working areas and arranged crosswise;

[0038] And a plurality of metal grids, each metal grid includes a first metal wire disposed in a plurality of the first groove structures and a second metal wire disposed in a plurality of the second groove structures.

[0039] Optionally, the first interlayer dielectric layer further includes a plurality of third groove structures and a plurality of fourth groove structures located in the redundant area and arranged with intersecting extending directions, and a plurality of dividing blocks located at the intersection positions of the extending directions of the third groove structures and the fourth groove structures; the dividing blocks divide both the third groove structures and the fourth groove structures into a plurality of groove portions;

[0040] The metal mesh array further includes:

[0041] A plurality of redundant metal meshes, each of the redundant metal meshes including third metal lines disposed in a plurality of the third groove structures and fourth metal lines disposed in a plurality of the fourth groove structures.

[0042] In a third aspect, an embodiment of the present disclosure provides a method for manufacturing a thin film sensor, including the method for manufacturing the above-mentioned metal mesh array.

[0043] In a fourth aspect, an embodiment of the present disclosure provides a thin film sensor, including the above-mentioned metal mesh array. Description of the Drawings

[0044] Figure 1 Is a schematic structural diagram of an exemplary thin film sensor;

[0045] Figure 2 Is Figure 1 A schematic cross-sectional structural diagram of the thin film sensor shown along the A-A' direction;

[0046] Figure 3 Is a schematic structural diagram of a metal mesh array provided by an embodiment of the present disclosure;

[0047] Figure 4 Is a flowchart of a method for manufacturing a metal mesh array provided by an embodiment of the present disclosure;

[0048] Figure 5 Is a top view of an intermediate product formed in step S13 of the method for manufacturing the metal mesh array according to an embodiment of the present disclosure;

[0049] Figure 6 Is a top view of an intermediate product formed in step S14 of the method for manufacturing the metal mesh array according to an embodiment of the present disclosure;

[0050] Figure 7 Is Figure 3 A flowchart of another method for manufacturing the metal mesh array shown;

[0051] Figure 8 Is Figure 3 A flowchart of yet another method for manufacturing the metal mesh array shown;

[0052] Figure 9 Another structural schematic diagram of the metal mesh array provided by an embodiment of the present disclosure;

[0053] Figure 10 A flowchart of another preparation method of the metal mesh array provided by an embodiment of the present disclosure;

[0054] Figure 11 A top view of an intermediate product formed in the redundant area in step S93 of the preparation method of the metal mesh array according to an embodiment of the present disclosure;

[0055] Figure 12 A top view of an intermediate product formed in the redundant area in step S94 of the preparation method of the metal mesh array according to an embodiment of the present disclosure;

[0056] Figure 13 A flowchart of a preparation method of a metal mesh provided by an embodiment of the present disclosure;

[0057] Figure 14 A flowchart of another preparation method of a metal mesh provided by an embodiment of the present disclosure;

[0058] Figure 15 A flowchart of yet another preparation method of a metal mesh provided by an embodiment of the present disclosure. Detailed implementation manners

[0059] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0060] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meanings understood by those of ordinary skill in the art belonging to the field of the present disclosure. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "one" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "include" or "comprise" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0061] Figure 1 A structural schematic diagram of an exemplary thin film sensor; Figure 2 For Figure 1Schematic cross-sectional structure diagram of the thin film sensor shown in the direction of A-A', as Figure 1 and Figure 2 shown. The thin film sensor includes: a substrate 1, the substrate 1 having a first surface and a second surface disposed opposite to each other, namely an upper surface and a lower surface; a first conductive layer 2 and a second conductive layer 3 respectively located on the first surface and the second surface of the substrate 1. Taking the thin film sensor as a transparent antenna as an example, wherein, the first conductive layer 2 can be a radiation layer, and the second conductive layer 3 can be a ground layer. Among them, the radiation layer can be used as a receiving unit of the antenna structure or for the transmitting unit of the antenna structure.

[0062] In order to ensure that the first conductive layer 2 and the second conductive layer 3 have good light transmittance, the first conductive layer 2 and the second conductive layer 3 need to be patterned. For example, the first conductive layer 2 can be composed of grid lines made of a metal material, and the second conductive layer 3 can also be composed of grid lines made of a metal material. It can be understood that the first conductive layer 2 and the second conductive layer 3 can also be composed of other patterned structures, for example, block electrodes with patterns such as rhombus and triangle, which will not be listed one by one here. From Figure 1 it can be seen that on the two surfaces of the substrate 1, the first conductive layer 2 and the second conductive layer 3, that is, the grid lines, are not provided on the entire surface. For any grid line, it is composed of electrically connected metal grids. Due to the material and formation process of the metal grids, the line width of the metal grids is relatively wide, seriously affecting the light transmittance of the thin film sensor, thereby affecting the user experience.

[0063] It should also be noted here that the above-mentioned metal grids are not limited to being applied in the antenna structure, and can also be used in the touch panel as touch electrodes. Of course, the metal grids can also be used in various metal wires, which will not be listed one by one here.

[0064] In order to solve the above technical problems, in an embodiment of the present disclosure, a metal grid array, a preparation method thereof, and a thin film sensor are provided. In the embodiment of the present disclosure, only taking the application of the metal grid array in the antenna as a receiving unit and / or a transmitting unit of the antenna as an example, but it should be understood that this does not constitute a limitation on the protection scope of the embodiment of the present disclosure.

[0065] Figure 3 Schematic structure diagram of a metal grid array according to an embodiment of the present disclosure, as Figure 3 shown. The embodiment of the present disclosure provides a metal grid array, the metal grid array including a plurality of working areas AA and a plurality of redundant areas BB, and metal grids 1000 are arranged in the working areas AA. The working areas AA and the redundant areas BB are alternately arranged in both the first direction and the second direction, that is, the metal grids 100 in the working areas AA of the metal grid array are spaced along the row direction and also spaced along the column direction.

[0066] The working area AA refers to the area where the metal grid array is in working state, and the redundant area BB refers to the non-working area where no metal grid 1000 is set. That is, in the working area AA, the grid lines in the metal grid 1000 are continuous, and there are no breakpoints at the intersection of the grid lines.

[0067] Figure 4 is a flow chart of a method for preparing a metal grid array, such as Figure 4 As shown, the present disclosure provides a method for preparing a metal grid array, which is used to prepare Figure 3 The metal grid array shown, the preparation method of the metal grid array comprises the following steps:

[0068] S11, providing a base substrate 100.

[0069] The material of the base substrate 100 may be a flexible material or a rigid material. This embodiment is described by taking the base substrate 100 as a rigid material as an example. The rigid material may include but is not limited to glass, sapphire, and quartz.

[0070] S12, forming a first metal layer 101 on the base substrate 100 as a seed layer.

[0071] The first metal layer 101 can be formed on the base substrate 100 by evaporation or sputtering and used as a seed layer to prepare for the subsequent electroplating process. The material of the first metal layer 101 can be selected according to the situation, for example, the material of the first metal layer 101 can be one or more of copper, titanium, aluminum, and silver.

[0072] S13, forming a first interlayer dielectric layer 102 on the side of the seed layer 101 away from the substrate 100, the first interlayer dielectric layer including a plurality of first groove structures 201 and a plurality of second groove structures 202 (such as Figure 5 shown).

[0073] The material of the first interlayer dielectric layer 102 includes but is not limited to organic materials or inorganic materials. For example, organic materials include but are not limited to polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For example, inorganic materials include but are not limited to silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx) and the like.

[0074] Among them, when the material of the first interlayer dielectric layer 102 is an organic material, a coating or spin coating process can be used to form the first interlayer dielectric layer 102 on the side of the seed layer 101 facing away from the substrate 100. When the material of the first interlayer dielectric layer 102 is an inorganic material, a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method or a sputtering method can be used to form the first interlayer dielectric layer 102 on the side of the seed layer 101 facing away from the substrate 100.

[0075] Among them, in this step, a plurality of first groove structures 201 and a plurality of second groove structures 202 arranged crosswise can be formed by a patterning process. In an embodiment, the "patterning process" refers to the step of forming a structure with a specific pattern, which can be a lithography process. The lithography process includes one or more steps such as forming a material layer, coating a photoresist, exposing, developing, etching, and photoresist stripping; of course, the "patterning process" can also be other processes such as an imprinting process or an inkjet printing process.

[0076] It should be noted that in this embodiment, the number of layers of the first interlayer dielectric layer 102 can be one layer or multiple layers. This embodiment is described by taking the number of layers of the first interlayer dielectric layer 102 as one layer as an example.

[0077] S14. Perform an electroplating process on the seed layer 101 to form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202. The first metal wires 301 and the second metal wires 302 in each working area AA are arranged crosswise to form a plurality of metal meshes 1000.

[0078] Among them, the seed layer is electroplated by a wire electroplating process to form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202. The first metal wires 301 and the second metal wires 302 in each working area are arranged crosswise to form a plurality of metal meshes 1000 (the metal mesh structure is as Figure 6 shown).

[0079] The "wire electroplating process" is to arrange electroplating leads in the first groove structure 201 and the second groove structure 202 on the seed layer 101. During the electroplating process, metal is deposited at a high speed in the groove structure. As time increases, the metal on the side walls of the groove structure gradually thickens until the groove structure is completely filled. Finally, the formed multiple metal wires are arranged crosswise to form a plurality of metal meshes.

[0080] In this embodiment, a first interlayer dielectric layer 102 is formed on the side of the seed layer 101 facing away from the substrate. A plurality of first groove structures 201 and a plurality of second groove structures 202 are formed on the first interlayer dielectric layer 102 through a patterning process, and a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202 are formed through a wire electroplating process, thereby forming a plurality of metal meshes 1000. Compared with the prior art, the steps of metal etching can be reduced, which helps to increase the uniformity of the line width of the metal wire and the yield rate of the metal wire.

[0081] In some embodiments, S13. A first interlayer dielectric layer 102 is formed on the side of the seed layer 101 facing away from the substrate 100. The step of the first interlayer dielectric layer 102 including a plurality of first groove structures 201 and a plurality of second groove structures 202 that are located in the working area AA and cross each other specifically includes:

[0082] S131. A first interlayer dielectric layer 102 is formed on the side of the seed layer 101 facing away from the substrate 100.

[0083] Among them, the formation method of the first interlayer dielectric layer is the same as that of the first interlayer dielectric layer in step S13, and will not be elaborated here.

[0084] S132. A plurality of first groove structures 201 and a plurality of second groove structures 202 that are cross - arranged are formed on the first interlayer dielectric layer 102 through a hard mask exposure process (Hard Mask) and an inductively coupled plasma etching process.

[0085] Among them, the hard mask (Hard Mask) is an inorganic thin - film material generated by CVD (Chemical Vapor Deposition, CVD). Its main components usually include TiN, SiOx, SiNx, etc. The hard mask is mainly used in multiple lithography processes. First, the multiple photoresist images are transferred to the hard mask, and then the final pattern is etched and transferred to the substrate through the hard mask.

[0086] In this embodiment, for example, a hard mask layer (such as SiOx, SiNx, Metal, ITO) is deposited on the first interlayer dielectric layer; a photoresist material (PR / BARC) is spin - coated on the hard mask layer; the patterns of the first groove structure and the second groove structure are transferred to the hard mask layer through exposure and development; after stripping the residual photoresist, through an inductively coupled plasma etching process (ICP), the patterns of the first groove structure and the second groove structure on the hard mask are etched onto the first interlayer dielectric layer.

[0087] In this embodiment, a groove structure is formed on the first interlayer dielectric layer through the Hard Mask + ICP process, which can ensure that the groove structure on the first interlayer dielectric layer is perpendicular to the surface of the substrate, contributing to the uniform line width of the subsequent formed metal grid and enabling an ultra-narrow line width of the formed metal line. Among them, the line width of the metal grid refers to the width of the metal line formed by the metal material in the first groove structure or the second groove structure, and the width of this metal line is equal to or approximately equal to the groove width of the first groove structure or the second groove structure. The line width of the metal grid formed in the embodiment of the present disclosure can be below 1.5 μm.

[0088] In some embodiments, step S13 of forming the first interlayer dielectric layer 102 on the side of the seed layer 101 facing away from the substrate 100, where the first interlayer dielectric layer 102 includes a plurality of first groove structures 201 and a plurality of second groove structures 202 that are located in the working area AA and cross each other, specifically includes:

[0089] Forming a plurality of first groove structures 201 and a plurality of second groove structures 202 that cross each other on the interlayer dielectric layer 102 through a nanoimprint process and an inductively coupled plasma etching process.

[0090] In this embodiment, by using a nanoimprint process and an inductively coupled plasma etching process to form a groove structure on the first interlayer dielectric layer, it can ensure that the groove structure on the first interlayer dielectric layer is perpendicular to the surface of the substrate, contributing to the uniform line width of the subsequent formed metal grid and enabling an ultra-narrow line width of the formed metal line.

[0091] Figure 7 For Figure 3 a flowchart of another preparation method of the metal grid array shown in Figure 7 shown, the preparation method of the metal grid array specifically includes:

[0092] S71: Provide a substrate 100.

[0093] Among them, the step of S71 is the same as the step of S11 and will not be elaborated here.

[0094] S72: Form a separation layer 1001 on the side of the separation layer 1001 facing away from the substrate 100, and the separation layer 1001 covers the substrate 100.

[0095] Among them, the separation layer 1001 can be formed on the substrate 100 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering.

[0096] S73: Form a second metal layer 1002 on the side of the separation layer 1001 facing away from the substrate 100.

[0097] Wherein, the second metal layer 1002 can be formed on the side of the separation layer 1001 facing away from the substrate 100 by evaporation or sputtering.

[0098] S74. A first metal layer 101 is formed on the side of the second metal layer 1002 facing away from the substrate 100. The orthographic projection of the first metal layer 101 on the substrate 100 coincides with the orthographic projection of the second metal layer 1002 on the substrate 100. The materials of the first metal layer 101 and the second metal layer 1002 are different. For example, the material of the first metal layer 101 is copper, and the material of the second metal layer 1002 is titanium.

[0099] Wherein, the first metal layer 101 can be formed on the side of the second metal layer 1002 facing away from the substrate 100 by evaporation or sputtering, and the first metal layer 101 serves as a seed layer for electroplating.

[0100] S75. A first interlayer dielectric layer 102 is formed on the side of the first metal layer 101 facing away from the substrate 100. The first interlayer dielectric layer 102 includes a plurality of first groove structures 201 and a plurality of second groove structures 202 arranged crosswise.

[0101] Wherein, the step of S75 is the same as the step of S13 and will not be elaborated here. It can be understood that the groove structure can be formed on the first interlayer dielectric layer by using the HardMask + ICP process, or the groove structure can be formed on the first interlayer dielectric layer by using the nanoimprint process and the inductively coupled plasma etching process. The specific process will not be elaborated here.

[0102] S76. An electroplating process is performed on the first metal layer 101 to form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202. The first metal wire 301 and the second metal wire 302 are arranged crosswise to form a metal grid 1000.

[0103] Wherein, the step of S76 is the same as the step of S14 and will not be elaborated here.

[0104] S77. After the separation layer 1001 is peeled off, the second metal layer 1002 is etched away, and the material of the first metal layer 101 located outside the first groove structure 201 and the second groove structure 202 is etched away to obtain a plurality of metal grids.

[0105] Wherein, the separation layer 1001 and the substrate 100 can be peeled off by laser irradiation, and the first metal layer 101 and the second metal layer 1002 are removed by dry etching or wet etching.

[0106] In this embodiment, the first metal line located in the first groove structure and the second metal line located in the second groove structure are formed by a wire electroplating process, which increases the uniformity of the line width of the metal line and the yield rate of the metal line. In addition, the groove structure is formed on the first interlayer dielectric layer by the HardMask+ICP process or the nanoimprint process, which can ensure that the groove structure on the first interlayer dielectric layer is perpendicular to the surface of the substrate, contribute to the uniformity of the line width of the subsequent formed metal grid, and enable the formation of an ultra-narrow line width of the metal line. Moreover, by providing the second metal layer, the adhesion of the first metal layer can be further increased.

[0107] Figure 8 For Figure 3 a flowchart of another preparation method of the metal grid array shown in Figure 8 shown, the preparation method of the metal grid array specifically includes:

[0108] S81. Provide a substrate 100.

[0109] Among them, the step of S81 is the same as the step of S71, which will not be elaborated here.

[0110] S82. Form a separation layer 1001 on the substrate 100, and the separation layer 1001 covers the substrate 100.

[0111] Among them, the step of S82 is the same as the step of S72, which will not be elaborated here.

[0112] S83. Form a second metal layer 1002 on the side of the separation layer 1001 facing away from the substrate 100.

[0113] Among them, the step of S83 is the same as the step of S73, which will not be elaborated here.

[0114] S84. Form a first metal layer 101 on the side of the second metal layer 1002 facing away from the substrate 100.

[0115] Among them, the first metal layer 101 can be formed on the side of the second metal layer 1002 facing away from the substrate 100 by evaporation or sputtering, and the first metal layer 101 serves as a seed layer for electroplating.

[0116] S85. Form a plurality of metal patterns 1010 through a patterning process.

[0117] Among them, a plurality of metal patterns 1010 are formed through photoresist coating, development, exposure, and etching processes.

[0118] S86. On the side of the layer where multiple metal patterns 101 are located, which is away from the substrate 100, form a first interlayer dielectric layer 102. After that, form multiple first groove structures 201 and multiple second groove structures 202 that are cross - arranged on the first interlayer dielectric layer 102. Among them, the groove structures are arranged in one - to - one correspondence with the metal patterns.

[0119] Among them, the Hard Mask + ICP process can be used to form the first groove structure 201 and the second groove structure 202 that are arranged in correspondence with the metal pattern 1010 on the first interlayer dielectric layer 102, or the nano - imprint process and inductively coupled plasma etching process can be used to form the first groove structure 201 and the second groove structure 202 that are arranged in one - to - one correspondence with the metal pattern 1010 on the first interlayer dielectric layer 102.

[0120] S87. Form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202 through an electroplating process. The first metal wire and the second metal wire are cross - arranged to form a metal grid.

[0121] Among them, the wire electroplating process can be used to form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202.

[0122] S88. Peel off the separation layer 1001 and etch away the second metal layer 1002 to obtain multiple metal grids 1000.

[0123] Among them, the separation layer 1001 and the substrate 100 can be peeled off by laser irradiation to obtain a metal grid array.

[0124] In this embodiment, forming a first metal wire located in the first groove structure and a second metal wire located in the second groove structure through the wire electroplating process helps to increase the uniformity of the wire width of the metal wire and the yield rate of the metal wire, and can reduce the etching steps of the first metal layer. In addition, forming groove structures on the first interlayer dielectric layer through the Hard Mask + ICP process or the nano - imprint process can ensure that the groove structures on the first interlayer dielectric layer are perpendicular to the surface of the substrate, which helps to make the wire width of the subsequent formed metal grid uniform, and can achieve an ultra - narrow wire width of the formed metal wire. Moreover, by setting the second metal layer, the adhesion of the first metal layer can be increased.

[0125] In some embodiments, after Figure 7 the S77 step shown, or Figure 8 after the S88 step shown, the method for preparing a metal grid array may further include:

[0126] Form a flexible film on the side of the first interlayer dielectric layer that is away from the substrate.

[0127] Among them, the thin film can be attached to the first interlayer dielectric layer 102 through a transparent optical adhesive (OCA adhesive). The flexible thin film material can be at least one of a cyclic olefin polymer (COP) thin film, polyimide (PI), or polyethylene terephthalate (PET).

[0128] In this embodiment, by forming a metal grid array on a rigid substrate, and then attaching the metal grid array with the rigid substrate peeled off to the flexible thin film, the attachment area of the flexible thin film can be increased.

[0129] Figure 9 For another structural schematic diagram of the metal grid array according to an embodiment of the present disclosure, as Figure 9 shown, the embodiment of the present disclosure provides a metal grid array. The metal grid array includes a plurality of working areas AA and a plurality of redundant areas BB. Metal grids 1000 are provided in the working areas AA, and redundant grids 2000 are provided in the redundant areas BB. The working areas AA and the redundant areas BB are alternately arranged in both the first direction and the second direction, that is, the metal grids 100 in the working areas AA of the metal grid array are spaced along the row direction and also spaced along the column direction. Similarly, the redundant metal grids 2000 in the redundant areas BB are spaced along the row direction and also spaced along the column direction.

[0130] Among them, the working area AA means that the metal grid array is in a working state in this area, and the redundant area BB means that the metal grid array is in a non-working state in this area. That is, the grid lines in the metal grids 1000 in the working area AA are continuous, and there are no breakpoints at the grid line intersection positions. In the redundant area BB, the grid lines in the redundant metal grids 2000 are discontinuous, and there are breakpoints at the grid line intersection positions.

[0131] Figure 10 For a flowchart of a preparation method of a metal grid array, as Figure 10 shown, the embodiment of the present disclosure provides a preparation method of a metal grid array, which is used to prepare the metal grid array as Figure 9 shown. The preparation method of the metal grid array includes the following steps:

[0132] S91. Provide a substrate 100.

[0133] Among them, in some examples, the material of the substrate 100 can be a flexible material or a rigid material. In this embodiment, the case where the material of the substrate 100 is a rigid material is taken as an example for illustration. Among them, the rigid material can include but is not limited to glass, sapphire, and quartz, etc.

[0134] S92. Form a first metal layer 101 on the substrate 100 as a seed layer.

[0135] Among them, the first metal layer 101 can be formed on the substrate 100 by evaporation or sputtering and used as a seed layer to prepare for the subsequent electroplating process. The material of the first metal layer 101 can be selected according to the situation. For example, the material of the first metal layer 101 can be one or more of copper, titanium, aluminum, and silver.

[0136] S93. A first interlayer dielectric layer 102 is formed on the side of the seed layer 101 facing away from the substrate 100. The first interlayer dielectric layer 102 includes a plurality of first groove structures 201 and a plurality of second groove structures 202 that are located in the working area AA and cross each other (as Figure 5 shown). The first interlayer dielectric layer 102 further includes a plurality of third groove structures 203 and a plurality of fourth groove structures 204 that are located in the redundant area BB and cross each other in the extending direction, and a plurality of dividing blocks (205) located at the cross position of the extending direction of the third groove structure 203 and the extending direction of the fourth groove structure 204. The dividing blocks divide both the third groove structure 203 and the fourth groove structure 204 into a plurality of groove portions (2031, 2041), (as Figure 11 shown).

[0137] Among them, the material of the first interlayer dielectric layer 102 includes but is not limited to organic materials or inorganic materials. For example, organic materials include but are not limited to resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, and silicone. For example, inorganic materials include but are not limited to silicon oxides (SiOx), silicon nitrides (SiNx), hafnium oxides (HfOx), silicon oxynitrides (SiON), and aluminum oxides (AlOx).

[0138] Among them, when the material of the first interlayer dielectric layer 102 is an organic material, the first interlayer dielectric layer 102 can be formed on the side of the seed layer 101 facing away from the substrate 100 by a coating or spin coating process group. When the material of the first interlayer dielectric layer 102 is an inorganic material, the first interlayer dielectric layer 102 can be formed on the side of the seed layer 101 facing away from the substrate 100 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering.

[0139] Among them, in this step, a plurality of first groove structures 201, a plurality of second groove structures 202, a plurality of third groove structures 203, a plurality of fourth groove structures 204 that are cross - arranged, and a plurality of partition blocks 205 located at the cross - position of the extending directions of the third groove structure 203 and the fourth groove structure 204 can be formed through a single lithography process. In this embodiment, the "lithography process" refers to the step of forming a structure with a specific pattern, which can be a lithography process. The lithography process includes one or more steps such as forming a material layer, coating a photoresist, exposing, developing, etching, and photoresist stripping; of course, the "lithography process" can also be other processes such as an imprint process, an ink - jet printing process, etc.

[0140] It should be noted that in this embodiment, the number of the first inter - layer dielectric layers can be one layer or multiple layers. This embodiment takes the number of the first inter - layer dielectric layers being one layer as an example for illustration.

[0141] S94. Perform an electroplating process on the seed layer 101 to form a first metal line 301 located in the first groove structure 201 and a second metal line 302 located in the second groove structure 202. The first metal lines 301 and the second metal lines 301 in each working area are cross - arranged to form a plurality of metal meshes 1000. At the same time, a third metal line 303 located in the third groove structure 203 and a fourth metal line 304 located in the fourth groove structure 204 are also formed. The third metal line 303 and the fourth metal line 304 are arranged to be disconnected at their cross - position. The extending directions of the third metal lines 303 and the fourth metal lines 304 in each redundant area BB are cross - arranged to form a plurality of redundant metal meshes 2000.

[0142] Among them, the seed layer is electroplated by a wire electroplating process to form a first metal line 301 located in the first groove structure 201 and a second metal line 302 located in the second groove structure 202. The first metal lines 301 and the second metal lines 302 in each working area AA are cross - arranged to form a plurality of metal meshes 1000 (the formed metal mesh structure is as Figure 6 shown). And at the same time, a third metal line 303 located in the third groove structure 203 and a fourth metal line 304 located in the fourth groove structure 204 are formed. The third metal line 303 and the fourth metal line 304 are arranged to be disconnected at their cross - position. The extending directions of the third metal lines 303 and the fourth metal lines 304 in each redundant area BB are cross - arranged to form a plurality of redundant metal meshes 2000 (the formed redundant metal mesh structure is as Figure 12 shown).

[0143] In this embodiment, a first metal wire 301 located in the first groove structure 201, a second metal wire 302 located in the second groove structure 202, a third metal wire 303 located in the third groove structure 203, and a fourth metal wire 304 located in the fourth groove structure 204 are formed by a wire electroplating process, which helps to increase the uniformity of the line width of the metal wires and the metal wire yield.

[0144] In some embodiments, the steps of forming a plurality of third groove structures 203 and a plurality of fourth groove structures 204 located in the redundant area BB and having their extension directions intersecting each other, and a plurality of segmentation blocks 205 located at the intersection of the extension direction of the third groove structure 203 and the extension direction of the fourth groove structure 204 on the first interlayer dielectric layer 102 specifically include:

[0145] A plurality of third groove structures 203 and a plurality of fourth groove structures 204, and a partition block 205, which are located in the redundant area BB and are arranged in an intersecting extension direction, are formed on the first interlayer dielectric layer 102 by a hard mask exposure process and an inductively coupled plasma etching process. Alternatively, a plurality of third groove structures 203 and a plurality of fourth groove structures 204, and a partition block 205, which are located in the redundant area BB and are arranged in an intersecting extension direction, are formed on the first interlayer dielectric layer 102 by a nanoimprint process and an inductively coupled plasma etching process.

[0146] In this embodiment, a groove structure is formed on the first interlayer dielectric layer through a hard mask exposure process (or a nanoimprint process) and an inductively coupled plasma etching process, which can ensure that the groove structure on the first interlayer dielectric layer is perpendicular to the surface of the substrate, which helps to ensure that the line width of the subsequently formed metal grid is uniform and can achieve an ultra-narrow line width of the formed metal line.

[0147] In some embodiments, after forming the plurality of redundant metal grids and the plurality of metal grids, the method further includes: forming a flexible film on a side of the first interlayer dielectric layer facing away from the substrate.

[0148] In this embodiment, a metal grid array is formed on a rigid substrate, and then the metal grid array with the rigid substrate peeled off is attached to the flexible film, thereby increasing the attachment area of the flexible film.

[0149] In order to more fully understand the present invention, several embodiments of the preparation method of the metal grid in the metal array are given below for illustration:

[0150] Example 1

[0151] Figure 13 is a flow chart of a method for preparing a metal grid, such as Figure 13 As shown, the preparation method comprises:

[0152] S131. Provide a substrate, the material of the substrate is glass, form a separation layer DBL on the glass substrate, form a copper thin film layer Cu on the side of the separation layer DBL facing away from the glass substrate, and form a first interlayer dielectric layer on the side of the copper thin film layer Cu facing away from the glass substrate. Among them, the first interlayer dielectric layer is a double-sided structure, including an OC (transparent optical glue) layer and a SiN layer. Then, coat a photoresist PR on the SiN layer.

[0153] S132. Form a plurality of first groove structures 201 and a plurality of second groove structures 202 that penetrate the OC layer and the SiN layer through a lithography process.

[0154] S133. Perform an electroplating process on the copper thin film layer to form a first metal wire 301 located in the first groove structure 201 and a second metal wire 302 located in the second groove structure 202, that is, form a metal grid structure.

[0155] After forming the metal grid structure, it may further include:

[0156] S134. Attach a COP film to the side of the SiN layer facing away from the glass substrate.

[0157] S135. Use laser irradiation to peel off the separation layer DBL.

[0158] S136. Dry-etch the copper thin film layer Cu.

[0159] After S136, a second substrate can also be attached to the side of the OC layer facing away from the COP film. Among them, the second substrate can be a mobile phone panel, etc.

[0160] Embodiment 2

[0161] Figure 14 It is a flowchart of another method for preparing a metal grid, as Figure 14 shown, the preparation method includes:

[0162] S141. Provide a glass substrate Glass, form a separation layer DBL on the glass substrate, form a copper thin film layer Cu on the side of the separation layer DBL facing away from the glass substrate, and form a plurality of metal patterns 200 on the copper thin film layer Cu through a lithography process. Form a first interlayer dielectric layer on the side of the plurality of metal patterns 200 facing away from the glass substrate Glass. Among them, the first interlayer dielectric layer is a double-sided structure, including an OC (transparent optical glue) layer and a SiN layer. After that, coat a photoresist PR on the SiN layer.

[0163] S142. Form a plurality of first groove structures 201 and a plurality of second groove structures 201 that penetrate the OC layer and the SiN layer through a lithography process, where the groove structures are correspondingly arranged with the metal patterns.

[0164] S143. Electroplate the copper thin film layer Cu to form the first metal line 301 located in the first groove structure 201 and the second metal line 302 located in the second groove structure 202, that is, form a metal grid structure.

[0165] After forming the metal grid structure, it may further include:

[0166] S144. Attach a COP thin film to the side of the SiN layer facing away from the glass substrate.

[0167] S145. Use laser irradiation to strip the separation layer DBL.

[0168] After S145, a second substrate may also be attached to the side of the OC layer facing away from the COP thin film, where the second substrate may be a mobile phone panel or the like.

[0169] Embodiment 3

[0170] Figure 15 It is a flowchart of another method for preparing a metal grid, as Figure 15 shown, the preparation method includes:

[0171] S151. Provide a glass substrate Glass, form a separation layer DBL on the glass substrate Glass, form a copper thin film layer Cu on the side of the separation layer DBL facing away from the glass substrate, and coat a photoresist PR on the side of the copper thin film layer facing away from the glass substrate. Form a plurality of first groove structures 201 and a plurality of second groove structures 202 penetrating through the photoresist layer through exposure and development.

[0172] S152. Perform an electroplating process on the copper thin film layer to form the first metal line 301 located in the first groove structure 201 and the second metal line 302 located in the second groove structure 202.

[0173] S153. Cover a layer of OC layer (i.e., an interlayer dielectric layer) on the first metal line 301 and the second metal line 302.

[0174] S154. Attach a COP thin film to the side of the OC layer facing away from the glass substrate.

[0175] S155. Use laser irradiation to strip the separation layer DBL.

[0176] S156. Dry-etch the copper thin film layer Cu.

[0177] After S156, a second substrate may also be attached to the side of the OC layer facing away from the COP thin film, where the second substrate may be a mobile phone panel or the like.

[0178] It should be noted that the preparation of the redundant metal grid only requires changing the mask in the above embodiment, and no further examples will be given here.

[0179] The present disclosure provides a metal grid array, such as Figure 3 , Figure 5 and Figure 6 As shown, the metal grid array includes a plurality of working areas AA and a plurality of redundant areas BB, and the working areas AA and the redundant areas BB are alternately arranged in a first direction and a second direction. The metal grid array includes a substrate 100, a first metal layer 101, a first interlayer dielectric layer 102 and a plurality of metal grids 1000.

[0180] Specifically, the first metal layer 101 is disposed on the base substrate 100, the first interlayer dielectric layer 102 is disposed on the side of the first metal layer 101 away from the base substrate 100, and the first interlayer dielectric layer 102 includes a plurality of first groove structures 201 and a plurality of second groove structures 202 that are located in the working area AA and are cross-arranged. Each metal grid 1000 includes a first metal wire 301 disposed in the plurality of first groove structures 201 and a second metal wire 302 in the plurality of second groove structures 202.

[0181] The present disclosure also provides a metal grid array, such as Figure 9 , Figure 11 and Figure 12 As shown, the metal grid array includes a plurality of working areas AA and a plurality of redundant areas BB, and the working areas AA and the redundant areas BB are alternately arranged in a first direction and a second direction. The metal grid array includes a substrate 100, a first metal layer 101, a first interlayer dielectric layer 102, a plurality of metal grids 1000 and a plurality of redundant metal grids 2000.

[0182] Specifically, the first metal layer 101 is disposed on the base substrate 100, the first interlayer dielectric layer 102 is disposed on the side of the first metal layer 101 away from the base substrate 100, and the first interlayer dielectric layer 102 includes a plurality of first groove structures 201 and a plurality of second groove structures 202 located in the working area AA and arranged crosswise. The first interlayer dielectric layer 102 also includes a plurality of third groove structures 203 and a plurality of fourth groove structures 204 located in the redundant area BB and arranged crosswise in the extension direction, and a plurality of segmentation blocks 205 located at the intersection of the extension direction of the third groove structure 203 and the extension direction of the fourth groove structure 204, and the segmentation 205 segments the third groove structure 203 and the fourth groove structure 204 into a plurality of groove portions (2031, 2041).

[0183] Among them, one metal grid 1000 in the multiple metal grids includes a first metal wire 301 disposed in multiple first groove structures 201 and a second metal wire 302 disposed in multiple second groove structures 202. One redundant metal grid 2000 in the multiple redundant metal grids includes a third metal wire 303 disposed in multiple third groove structures 203 and a fourth metal wire 304 disposed in multiple fourth groove structures 204.

[0184] An embodiment of the present disclosure also provides a method for manufacturing a thin film sensor, and this method may include the method for manufacturing the above metal grid array.

[0185] Since the method for manufacturing the thin film sensor in the embodiment of the present disclosure includes the method for manufacturing the above metal grid array, the transmittance of the thin film sensor formed by this method is high, and after applying this thin film sensor to a display device, the influence on the optical effect of the display device is significantly reduced.

[0186] An embodiment of the present disclosure also provides a thin film sensor, which can be manufactured by the above method. This thin film sensor includes, but is not limited to, a transparent antenna. The metal grid in the thin film sensor in the embodiment of the present disclosure is manufactured by the above method, so the width of this metal wire is not greater than 2 μm, for example, less than 1.5 μm.

[0187] The thin film sensor may include an antenna. The antenna in the embodiment of the present disclosure can also be used in the glass window systems of automobiles, trains (including high-speed rails), airplanes, buildings, etc. This antenna can be fixed on the inner side of the glass window (the side close to the interior). Since the optical transmittance of the antenna is relatively high, its influence on the transmittance of the glass window is not significant while realizing the communication function, and this type of antenna will also become a trend of beautifying the antenna. Among them, the glass window in the embodiment of the present disclosure includes, but is not limited to, double-layer glass, and the types of glass windows can also be single-layer glass, laminated glass, thin glass, thick glass, etc.

[0188] In some examples, the antenna device provided by the embodiment of the present disclosure further includes a transceiver unit, a radio frequency transceiver, a signal amplifier, a power amplifier, and a filtering unit. The antenna in the antenna device can be used as a transmitting antenna or a receiving antenna. Among them, the transceiver unit may include a baseband and a receiving end. The baseband provides signals of at least one frequency band, for example, provides 2G signals, 3G signals, 4G signals, 5G signals, etc., and sends the signals of at least one frequency band to the radio frequency transceiver. After the antenna in the antenna device receives a signal, it can be transmitted to the receiving end in the transceiver unit after being processed by the filtering unit, the power amplifier, the signal amplifier, and the radio frequency transceiver. The receiving end can be, for example, an intelligent gateway, etc.

[0189] Further, the radio frequency transceiver is connected to the transceiver unit, and is used to modulate the signal sent by the transceiver unit, or to demodulate the signal received by the antenna and then transmit it to the transceiver unit. Specifically, the radio frequency transceiver may include a transmitting circuit, a receiving circuit, a modulating circuit, and a demodulating circuit. After the transmitting circuit receives various types of signals provided by the baseband, the modulating circuit can modulate the various types of signals provided by the baseband and then send them to the antenna. The antenna receives the signal and transmits it to the receiving circuit of the radio frequency transceiver. The receiving circuit transmits the signal to the demodulating circuit, and the demodulating circuit demodulates the signal and then transmits it to the receiving end.

[0190] Further, the radio frequency transceiver is connected to a signal amplifier and a power amplifier. The signal amplifier and the power amplifier are further connected to a filtering unit, and the filtering unit is connected to at least one antenna. During the process of the antenna device transmitting a signal, the signal amplifier is used to improve the signal-to-noise ratio of the signal output by the radio frequency transceiver and then transmit it to the filtering unit; the power amplifier is used to amplify the power of the signal output by the radio frequency transceiver and then transmit it to the filtering unit; the filtering unit may specifically include a duplexer and a filtering circuit. The filtering unit combines the signals output by the signal amplifier and the power amplifier and filters out the clutter and then transmits them to the antenna, and the antenna radiates the signal. During the process of the antenna device receiving a signal, after the antenna receives the signal, it transmits it to the filtering unit. The filtering unit filters out the clutter of the signal received by the antenna and then transmits it to the signal amplifier and the power amplifier. The signal amplifier increases the gain of the signal received by the antenna to increase the signal-to-noise ratio of the signal; the power amplifier amplifies the power of the signal received by the antenna. The signal received by the antenna is processed by the power amplifier and the signal amplifier and then transmitted to the radio frequency transceiver, and the radio frequency transceiver then transmits it to the transceiver unit.

[0191] In some examples, the signal amplifier may include various types of signal amplifiers, such as a low-noise amplifier, which is not limited herein.

[0192] In some examples, the antenna device provided by the embodiments of the present disclosure further includes a power management unit, and the power management unit is connected to the power amplifier to provide a voltage for amplifying the signal to the power amplifier.

[0193] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A method for preparing a metal grid array, the metal grid array including a plurality of working areas and a plurality of redundant areas; the working areas and the redundant areas are alternately arranged in both a first direction and a second direction; wherein, The preparation method includes: Providing a substrate; Forming a first metal layer on the substrate as a seed layer; Forming a first interlayer dielectric layer on a side of the seed layer facing away from the substrate; the first interlayer dielectric layer includes a plurality of first groove structures and a plurality of second groove structures that are located in the working area and cross each other; Performing an electroplating process on the seed layer to form first metal lines located in the first groove structures and second metal lines located in the second groove structures; the first metal lines and the second metal lines in each working area cross each other to form a plurality of metal grids; Removing the substrate; Removing the seed layer material outside the first groove structures and the second groove structures in the first interlayer dielectric layer and retaining the first interlayer dielectric layer; The step of forming the first interlayer dielectric layer includes: Forming, by a combination of a hard mask exposure process and an inductively coupled plasma etching process, or a combination of a nanoimprint process and an inductively coupled plasma etching process, a plurality of the first groove structures and a plurality of the second groove structures that are located in the working area and cross each other on the first interlayer dielectric layer.

2. The preparation method of the metal mesh array according to claim 1, wherein, The first interlayer dielectric layer further includes a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have cross-set extending directions, and a plurality of dividing blocks located at the cross position of the extending direction of the third groove structures and the extending direction of the fourth groove structures; the dividing blocks divide both the third groove structures and the fourth groove structures into a plurality of groove portions; When performing the electroplating process on the seed layer to form the first metal lines located in the first groove structures and the second metal lines located in the second groove structures, it further includes: Forming third metal lines located in the third groove structures and fourth metal lines located in the fourth groove structures; the third metal lines and the fourth metal lines are disconnected at their cross positions; the extending directions of the third metal lines and the fourth metal lines in each redundant area cross each other to form a plurality of redundant metal grids.

3. The manufacturing method of the metal mesh array according to claim 2, wherein, The step of forming the first interlayer dielectric layer further includes: Forming, by a hard mask exposure process and an inductively coupled plasma etching process, a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have cross-set extending directions on the first interlayer dielectric layer.

4. The manufacturing method of the metal mesh array according to claim 2, wherein, The step of forming the first interlayer dielectric layer further includes: Forming, by a nanoimprint process and an inductively coupled plasma etching process, a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have cross-set extending directions on the first interlayer dielectric layer.

5. The manufacturing method of the metal mesh array according to claim 1, wherein, The step of forming a seed layer on the substrate includes: Depositing a first metal layer on one side of the substrate, the first metal layer covering the substrate.

6. The manufacturing method of the metal mesh array according to claim 1, wherein, The step of forming a seed layer on the substrate includes: Depositing a first metal layer on one side of the substrate and forming a plurality of metal patterns through a patterning process; Form a first interlayer dielectric layer on a side of the seed layer facing away from the substrate; in the step of forming the first interlayer dielectric layer including a plurality of first groove structures and a plurality of second groove structures that are located in the working area and intersect with each other, both the first groove structures and the second groove structures are arranged corresponding to the metal pattern.

7. The method for preparing a metal grid array according to claim 1, wherein, After providing a substrate, it further includes: Form a second metal layer on one side of the substrate; Specifically, forming a first metal layer on the substrate as a seed layer includes: Form a first metal layer on a side of the second metal layer facing away from the substrate, and a positive projection of the first metal layer on the substrate coincides with a positive projection of the second metal layer on the substrate.

8. The manufacturing method of the metal mesh array according to claim 7, wherein, Before the step of forming a second metal layer on one side of the substrate, it further includes: Form a separation layer on the substrate, and the separation layer covers the substrate.

9. The manufacturing method of the metal mesh array according to claim 1, wherein, After forming a plurality of the metal meshes, it further includes: Form a flexible film on a side of the first interlayer dielectric layer facing away from the substrate.

10. The manufacturing method of the metal mesh array according to claim 2, wherein, After forming a plurality of the redundant metal meshes, it further includes: Form a flexible film on a side of the first interlayer dielectric layer facing away from the substrate.

11. A metal grid array, the metal grid array comprising a plurality of working areas and a plurality of redundant areas; the working areas and the redundant areas are alternately arranged in both a first direction and a second direction; wherein, The metal mesh array includes: A substrate; A first metal layer provided on the substrate; A first interlayer dielectric layer provided on a side of the first metal layer facing away from the substrate, and the first interlayer dielectric layer includes a plurality of first groove structures and a plurality of second groove structures that are located in the working area and intersect with each other; And a plurality of metal meshes, each of the metal meshes includes a first metal wire provided in a plurality of the first groove structures and a second metal wire provided in a plurality of the second groove structures.

12. The metal mesh array according to claim 11, wherein, The first interlayer dielectric layer further includes a plurality of third groove structures and a plurality of fourth groove structures that are located in the redundant area and have intersecting extending directions, and a plurality of dividing blocks located at an intersection position of the extending direction of the third groove structures and the extending direction of the fourth groove structures; The dividing blocks divide both the third groove structures and the fourth groove structures into a plurality of groove portions; The metal mesh array further includes: A plurality of redundant metal meshes, each of the redundant metal meshes includes a third metal wire provided in a plurality of the third groove structures and a fourth metal wire provided in a plurality of the fourth groove structures.

13. A method for preparing a thin film sensor, wherein, It includes a preparation method of the metal mesh array according to any one of claims 1-10.

14. A thin film sensor, wherein, It includes the metal mesh array according to claim 11 or 12.

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