A test circuit and test method for an e-ink screen panel

Abstract

This invention relates to a testing circuit and method for e-ink screen panels, including first and second fast detection circuits and first and second detection circuits, which are composed of numerous thin-film transistors. The invention also provides a corresponding detection method. Before attaching the electronic paper film, a specific timing voltage is applied to the detection signal input terminal, and a voltage detection device can then determine whether the panel has any open or short circuit abnormalities. This method is not only accurate but also highly efficient for testing medium to large-sized display areas.

Description

Technical Field

[0001] This invention relates to the field of electronic paper displays, and more specifically, to a test circuit and test method for an e-ink screen panel. Background Technology

[0002] When we need to read e-books, we might choose an e-ink reader as our reading tool. Due to its low power consumption, diverse functions, and low power consumption, e-ink displays are widely used in price tags, advertising, and education. However, during the manufacturing process, e-ink display panels often fail to function properly due to missed detection of open or short circuits in the data lines or scan lines, resulting in substandard products. Therefore, a testing solution is needed to address the continuity of the display panel's data lines and scan lines.

[0003] In existing technical solutions, a fast detection circuit is provided for detecting the continuity of data lines and scan lines in medium and large-sized panels. This circuit contains multiple thin-film transistors and is connected to the data lines and scan lines. By inputting signals, the continuity of the data lines and scan lines can be detected to a certain extent.

[0004] However, using the above circuit, any abnormality can only be detected after the electronic paper film has been applied. This not only reduces production efficiency, but also requires the electronic paper film to be removed to correct any abnormality after it has been applied, rendering the electronic paper film unusable. Furthermore, if a short circuit occurs, it can damage the internal detection circuit of the electronic paper. Summary of the Invention

[0005] The purpose of this invention is to overcome the defects of the prior art and to provide a simple, widely applicable e-ink screen panel test circuit and test method that can be tested before the electronic paper film is applied.

[0006] The present invention provides a testing circuit for an e-ink screen panel, the technical solution of which is as follows:

[0007] An e-ink screen panel testing circuit includes a first input terminal, a second input terminal, a third input terminal, a first thin-film transistor (TFT) fast detection circuit, and a second TFT fast detection circuit. The first TFT fast detection circuit includes a plurality of first TFTs connected in parallel. The gate of each first TFT is electrically connected to the third input terminal, the source of each first TFT is electrically connected to the first input terminal, and the drain of each first TFT is electrically connected to a first end of a scan line. The second TFT fast detection circuit includes a plurality of second TFTs. The gate of each second TFT is electrically connected to the third input terminal, the source of each second TFT is electrically connected to the second input terminal, and the drain of each second TFT is electrically connected to a first end of a data line. The circuit also includes a first test circuit for testing the open and short circuit conditions of the scan line and the data line.

[0008] The first test circuit includes a first sub-circuit and a second sub-circuit;

[0009] The first sub-circuit includes a plurality of third thin-film transistors connected in series. The gate of each third thin-film transistor is electrically connected to the second end of a scan line or the second end of a data line. The source of the first third thin-film transistor is electrically connected to the fourth input terminal, and the drain of the last thin-film transistor is electrically connected to the second output terminal.

[0010] The second sub-circuit includes several thin-film transistor groups, each of which is electrically connected to the fifth input terminal, the scan line and the data line, and the first output terminal.

[0011] Compared with the prior art, the technical solution provided by this invention application can bring at least the following beneficial effects: By connecting the second end of the scanning lines and data lines of the e-ink display area to the test circuit, the detection of short circuits and open circuits of the scanning lines and data lines can be achieved under the coordination of numerous thin-film transistors in the test circuit. This not only enables the determination of whether there is an open circuit or short circuit in the panel after applying a specific timing voltage to the detection input terminal before attaching the electronic paper film, thereby reducing waste and cost, but also, in medium and large-sized panels, due to the combined operation of numerous thin-film transistors to achieve signal transmission, only a multimeter is needed to determine the corresponding situation during testing, thus significantly improving testing efficiency.

[0012] Preferably, the thin-film transistor group includes a first type of thin-film transistor combination and a second type of thin-film transistor combination. The first type of thin-film transistor combination includes a first type 1 thin-film transistor and a first type 2 thin-film transistor. The source of the first type 1 thin-film transistor is electrically connected to the fifth input terminal. The gate of the first type 1 thin-film transistor is electrically connected to the second terminal of a data line. The drain of the first type 1 thin-film transistor is electrically connected to the source of the first type 2 thin-film transistor. The gate of the first type 2 thin-film transistor is electrically connected to the second terminal of a scan line. The drain of the first type 2 thin-film transistor is electrically connected to the first output terminal.

[0013] The second type of thin-film transistor assembly includes a second type 1 thin-film transistor, a second type 2 thin-film transistor, and a second type 3 thin-film transistor. The source of the second type 1 thin-film transistor is electrically connected to the drain of the second type 2 thin-film transistor. The gate of the second type 1 thin-film transistor is electrically connected to the second end of a data line. The drain of the second type 1 thin-film transistor is electrically connected to the source of the second type 2 thin-film transistor. The source of the second type 2 thin-film transistor is also electrically connected to the fifth input terminal. The gate of the second type 2 thin-film transistor is electrically connected to the second end of a data line. The drain of the second type 2 thin-film transistor is electrically connected to the source of the second type 3 thin-film transistor. The gate of the second type 3 thin-film transistor is electrically connected to the second end of a scan line. The drain of the second type 3 thin-film transistor is electrically connected to the first output terminal.

[0014] This part of the circuit uses two types of thin-film transistor (TFT) groups, determined by the distribution of scan lines and data lines. When there are two data lines without a scan line in between, the second type of transistor group can be connected. With the cooperation of these two types of transistor groups, signals are effectively transmitted, achieving accurate detection.

[0015] Preferably, the first test circuit is located at the top of the display area; being located at the top of the display area saves a lot of space, and short-circuit and open-circuit signals can be tested even before the display film is covered.

[0016] Preferably, this circuit also includes a second test circuit for testing the continuity of the via data line passing through the replacement hole. The second test circuit includes several fourth thin-film transistors connected in series. The source of the first fourth thin-film transistor is electrically connected to the fourth input terminal, and the drain of the last fourth thin-film transistor is electrically connected to the third output terminal. The gate of each fourth thin-film transistor is electrically connected to the second end of the via data line. The via data line is a part of the data line passing through the replacement hole. This circuit design can prevent oversight in the detection of this type of data line, and the circuit further enhances the test accuracy.

[0017] Preferably, the second test circuit is located on one side of the via data line in the display area; with this arrangement, the display area space is saved and other operations are not affected during testing.

[0018] This technical solution also includes a test method for the ink screen panel test circuit, and the specific technical solution is as follows;

[0019] A test method for the ink screen panel test circuit, applicable to the first test circuit in the ink screen panel test circuit, includes an open circuit test method for the scan line or data line, a short circuit test method for the scan line, and a short circuit test method for the data line;

[0020] The open circuit test method for the scan line or data line includes the following steps:

[0021] A1. Input a high level H1 to the first input terminal, a high level H2 to the second input terminal, and a high level H2 to the third input terminal, where H1 < H2;

[0022] A2. Input a high level H1 or a low level L to the fourth input terminal, and input a high level H1, a low level L, or a ground signal to the fifth input terminal (55);

[0023] A3. Detect the first output terminal or the second output terminal by using a voltage detection device. When the fourth input terminal inputs a high level H1, if the first output terminal or the second output terminal outputs a high level signal H1, it means that both the data line and the scan line are normal. If the first output terminal or the second output terminal outputs a ground signal, it means that there is an open circuit in the scan line or the data line. When the fourth input terminal inputs a low level L, if the first output terminal or the second output terminal outputs a low level signal L, it means that both the data line and the scan line are normal. If the first output terminal or the second output terminal outputs a ground signal, it means that there is an open circuit in the scan line or the data line;

[0024] The short circuit test method for the scan line includes the following steps:

[0025] B1. Input a low level L to the first input terminal, a high level H2 to the second input terminal, and a high level H1 to the third input terminal, where H2 < H1;

[0026] B2. Input a high level H2, a low level L, or a ground signal to the fourth input terminal, and input a high level H2 or a low level L to the fifth input terminal;

[0027] B3. By using a voltage detection device to measure the first or second output terminal, when the fifth input terminal is high-level (H2), if the first or second output terminal outputs a ground signal, it indicates that the scan lines are all normal; if the first or second output terminal outputs a high-level signal (H2), it indicates that there is a short circuit in the scan lines. When the fifth input terminal is low-level (L), if the first or second output terminal outputs a ground signal, it indicates that the scan lines are all normal; if the first or second output terminal outputs a low-level signal (L), it indicates that there is a short circuit in the scan lines.

[0028] The data cable short-circuit test method includes the following steps:

[0029] C1. Input a low level H2 to the first input terminal, a high level L to the second input terminal, and a high level H1 to the third input terminal, where H2

[0030] C2. Input a high level H2 or a low level L or a ground signal to the fourth input terminal, and input a high level H2 or a low level L to the fifth input terminal.

[0031] C3. By using a voltage detection device to measure the first or second output terminal, when the fifth input terminal is high-level (H2), if the first or second output terminal outputs a ground signal, it indicates that the data lines are normal; if the first or second output terminal outputs a high-level signal (H2), it indicates that the data lines are short-circuited. When the fifth input terminal is low-level (L), if the first or second output terminal outputs a ground signal, it indicates that the data lines are normal; if the first or second output terminal outputs a low-level signal (L), it indicates that the data lines are short-circuited.

[0032] This method makes specific operational arrangements based on the three functions of the test circuit. The operation is simple. After inputting the signal, you only need to use a multimeter to test the continuity of the scan line and data line according to the pattern. The test efficiency and accuracy are relatively high.

[0033] Preferably, this method also includes a method for detecting open circuits in via data lines passing through replacement holes in e-ink panel test circuits, comprising the following steps:

[0034] Step 1: Input a low level L to the first input terminal, a high level H2 to the second input terminal, and a high level H1 to the third input terminal, where H1 > H2;

[0035] Step 2: Input a low level L to the fourth input terminal and a low level L to the fifth input terminal;

[0036] ​Step 3: Measure the voltage signal at the third output terminal using a voltage detection device. If a low-level signal is detected, it indicates that the data line through the cable replacement hole is normal. If a ground signal is detected, it indicates that there is an open circuit in the data line through the cable replacement hole.

[0037] This method is designed to detect open circuits in via data lines. It is also very simple to operate. After inputting the level signal according to the rules, the open circuit of the via data line can be detected by using a multimeter. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall structure of the electronic paper display area of ​​the panel detection circuit of the present invention;

[0039] Figure 2 This is a structural diagram of the first and second thin-film transistor fast detection circuits for existing medium and large-sized display panels;

[0040] Figure 3 This is a structural diagram of the first test circuit of the present invention;

[0041] Figure 4 This is a structural diagram of the second test circuit of the present invention;

[0042] Figure 5 This is the circuit breaker detection timing sequence in an embodiment of the present invention;

[0043] Figure 6 This is the timing sequence for the data line short-circuit test in this embodiment of the invention;

[0044] Figure 7 This is the timing sequence for the scan line short-circuit test in an embodiment of the present invention;

[0045] Figure 8 This is the timing sequence for testing the open circuit of the via data line in an embodiment of the present invention.

[0046] In the diagram, the numbers represent: 1. First thin-film transistor fast detection circuit; 2. Second thin-film transistor fast detection circuit; 3. Display area; 31. Scan line; 32. Data line; 321. Through-hole data line; 33. Replacement hole; 4. First test circuit; 41. First sub-circuit; 42. Second sub-circuit; 421. First type of thin-film transistor combination; 421-1. First type of thin-film transistor No. 1; 421-2. First type of thin-film transistor No. 1; 422. Second type of thin-film transistor combination; 422-1. Second type of thin-film transistor No. 1; 422-2. Second type of thin-film transistor No. 2; 422-3. Second type of thin-film transistor No. 3; 5. Second test circuit; 51. First input terminal; 52. Second input terminal; 53. Third input terminal; 54. Fourth input terminal; 55. Fifth input terminal; 61. First output terminal; 62. Second output terminal; 63. Third output terminal. Detailed Implementation

[0047] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0048] Combination Figure 1 —2. This embodiment first provides a detailed introduction to the technical solution of an e-ink screen panel test circuit.

[0049] An embodiment of the present invention provides an e-ink screen panel testing circuit, including a first input terminal 51, a second input terminal 52, a third input terminal 53, a first thin-film transistor fast detection circuit 1, and a second thin-film transistor fast detection circuit 2. The first thin-film transistor fast detection circuit 1 includes a plurality of first thin-film transistors connected in parallel. The gate of each first thin-film transistor is electrically connected to the third input terminal 53, the source of each first thin-film transistor is electrically connected to the first input terminal 51, and the drain of each first thin-film transistor is electrically connected to the first end of a scan line 31. The second thin-film transistor fast detection circuit 2 includes a plurality of second thin-film transistors. The gate of each second thin-film transistor is electrically connected to the third input terminal 53, the source of each second thin-film transistor is electrically connected to the second input terminal 52, and the drain of each second thin-film transistor is electrically connected to the first end of a data line 32.

[0050] The two circuits mentioned above are typically located at the lower end of the display area and are responsible for transmitting input signals to the scan lines or data lines. To a large extent, these two circuits function as switches. They can also be used to detect short circuits and open circuits in the data lines and scan lines, but this is very inefficient and requires a protective film to be applied for conversion.

[0051] The first input terminal 51 is connected to the scan line through the first fast detection circuit, so it can also be called the scan line signal input terminal (gate pad). The second input terminal 52 is connected to the data line through the second fast detection circuit, so it can also be called the data line signal input terminal (data pad). The third input terminal 53 is a control terminal used to control the turning on or off of each thin-film transistor, so it can also be called the switch signal input terminal (switch pad).

[0052] The key point of this invention is that it also includes a first test circuit 4 for testing open and short circuit conditions of scan line 31 and data line 32.

[0053] The first test circuit 4 includes a first sub-circuit 41 and a second sub-circuit 42;

[0054] The first sub-circuit 41 includes a plurality of third thin-film transistors connected in series. The gate of each third thin-film transistor is electrically connected to the second end of a scan line 31 or the second end of a data line 32. The source of the first third thin-film transistor is electrically connected to the fourth input terminal 54, and the drain of the last thin-film transistor is electrically connected to the second output terminal 62.

[0055] The second sub-circuit 42 includes several thin-film transistor groups, each of which is electrically connected to the fifth input terminal 55, each of which is electrically connected to the scan line 31 and the data line 32, and each of which is electrically connected to the first output terminal 61.

[0056] Specifically, the thin-film transistor group includes a first type of thin-film transistor combination 421 and a second type of thin-film transistor combination 422. The first type of thin-film transistor combination 421 includes a first type 1 thin-film transistor 421-1 and a first type 2 thin-film transistor 421-2. The source of the first type 1 thin-film transistor 421-1 is electrically connected to the fifth input terminal 55. The gate of the first type 1 thin-film transistor 421-1 is electrically connected to the second end of a data line 32. The drain of the first type 1 thin-film transistor 421-1 is electrically connected to the source of the first type 2 thin-film transistor 421-2. The gate of the first type 2 thin-film transistor 421-2 is electrically connected to the second end of a scan line 31. The drain of the first type 2 thin-film transistor 421-2 is electrically connected to the first output terminal 61.

[0057] The second type of thin-film transistor assembly 422 includes a second type 1 thin-film transistor 422-1, a second type 2 thin-film transistor 422-2, and a second type 3 thin-film transistor 422-3. The source of the second type 1 thin-film transistor 422-1 is electrically connected to the drain of the second type 2 thin-film transistor 422-2. The gate of the second type 1 thin-film transistor 422-1 is electrically connected to the second terminal of a data line 32. The drain of the second type 1 thin-film transistor 422-1 is electrically connected to the second type 2 thin-film transistor 422-2. The source of the second type 2 thin film transistor 422-2 is electrically connected to the fifth input terminal 55. The gate of the second type 2 thin film transistor 422-2 is electrically connected to the second end of a data line 32. The drain of the second type 2 thin film transistor 422-2 is electrically connected to the source of the second type 3 thin film transistor 422-3. The gate of the second type 3 thin film transistor 422-3 is electrically connected to the second end of a scan line 31. The drain of the second type 3 thin film transistor 422-3 is electrically connected to the first output terminal 61.

[0058] The via data line test circuit in this technical solution further includes a second test circuit 5 for testing the continuity of the via data line 321 passing through the wiring change hole 33. The second test circuit 5 includes a number of fourth thin-film transistors connected in series. The source electrode of the first fourth thin-film transistor is electrically connected to the fourth input terminal 54, and the drain electrode of the last fourth thin-film transistor is electrically connected to the third output terminal 63. The gate electrode of each fourth thin-film transistor is electrically connected to the second end of the via data line 321. The via data line is the data line 32 passing through the wiring change hole 33. Since there can be at most one wiring change hole 33 in each row in the display area, the presence of the wiring change hole may affect the determination of the open circuit condition of the via data line 321. Therefore, for safety reasons, the second test circuit is designed.

[0059] In this embodiment, the first test circuit is located at the top of the display area 3. The second test circuit is located on one side of the via data line 321 in the display area 3. In this embodiment, the scan lines are arranged in sequence, shown as G1, G2, etc., and the data lines are also arranged in sequence, shown as D1, D2, etc.

[0060] For the first test circuit 4 of this embodiment, this embodiment also provides a method for testing an ink screen panel test circuit, including a method for testing the open circuit of the scan line 31 or the data line 32, a method for testing the short circuit of the scan line 31, and a method for testing the short circuit of the data line 32.

[0061] Among them, the method for testing the open circuit of the scan line 31 or the data line 32 includes the following steps:

[0062] Step 1: Input a high level H1 to the first input terminal 51, input a high level H2 to the second input terminal 52, and input a high level H2 to the third input terminal 53, where H1 < H2;

[0063] Step 2: Input a high level H1 or a low level L to the fourth input terminal 54, and input a high level H1, a low level L, or a ground signal to the fifth input terminal 55;

[0064] Step 3: Detect the first output terminal 61 or the second output terminal 62 by using a multimeter. When the fourth input terminal 54 inputs a high level H1, if the first output terminal 61 or the second output terminal 62 outputs a high level signal H1, it means that both the data line 32 and the scan line 31 are normal. If the first output terminal 61 or the second output terminal 62 outputs a ground signal, it means that there is an open circuit in the scan line 31 or the data line 32. When the fourth input terminal 54 inputs a low level L, if the first output terminal 61 or the second output terminal 62 outputs a low level signal L, it means that both the data line 32 and the scan line 31 are normal. If the first output terminal 61 or the second output terminal 62 outputs a ground signal, it means that there is an open circuit in the scan line 31 or the data line 32;

[0065] Among them, the method for testing the short circuit of the scan line 31 includes the following steps:

[0066] Step 1: Input a low level L to the first input terminal 51, a high level H2 to the second input terminal 52, and a high level H1 to the third input terminal 53, where H2...

[0067] Step 2: Input a high level H2, a low level L, or a ground signal to the fourth input terminal 54, and input a high level H2 or a low level L to the fifth input terminal 55;

[0068] Step 3: Measure the voltage at the first output terminal 61 or the second output terminal 62 using a voltage detection device. When the fifth input terminal 55 inputs a high level H2, if the first output terminal 61 or the second output terminal 62 outputs a ground signal, it indicates that the scan lines 31 are all normal. If the first output terminal 61 or the second output terminal 62 outputs a high level signal H2, it indicates that the scan lines 31 are short-circuited. When the fifth input terminal 55 inputs a low level L, if the first output terminal 61 or the second output terminal 62 outputs a ground signal, it indicates that the scan lines 31 are all normal. If the first output terminal 61 or the second output terminal 62 outputs a low level signal L, it indicates that the scan lines 31 are short-circuited.

[0069] The short-circuit test method for data cable 32 includes the following steps:

[0070] Step 1: Input a low level H2 to the first input terminal 51, a high level L to the second input terminal 52, and a high level H1 to the third input terminal 53, where H2...

[0071] Step 2: Input a high level H2, a low level L, or a ground signal to the fourth input terminal 54, and input a high level H2 or a low level L to the fifth input terminal 55;

[0072] Step 3: Measure the voltage at the first output terminal 61 or the second output terminal 62 using a voltage detection device. When the fifth input terminal 55 inputs a high level H2, if the first output terminal 61 or the second output terminal 62 outputs a ground signal, it indicates that the data line 32 is normal. If the first output terminal 61 or the second output terminal 62 outputs a high level signal H2, it indicates that the data line 32 is short-circuited. When the fifth input terminal 55 inputs a low level L, if the first output terminal 61 or the second output terminal 62 outputs a ground signal, it indicates that the data line 32 is normal. If the first output terminal 61 or the second output terminal 62 outputs a low level signal L, it indicates that the data line 32 is short-circuited.

[0073] The technical solution in this embodiment also includes a method for detecting open circuits in the via data line (312) passing through the cable replacement hole 33, comprising the following steps:

[0074] ​​Step 1: Input a low level L to the first input terminal 51, a high level H2 to the second input terminal 52, and a high level H1 to the third input terminal 53, where H1 > H2;

[0075] Step 2: Input a low level L to the fourth input terminal 54 and a low level L to the fifth input terminal 55;

[0076] Step 3: Measure the voltage signal at the third output terminal 63 using a voltage detection device. If a low-level signal is detected, it indicates that the via data line 321 through the cable replacement hole 33 is normal. If a ground signal is detected, it indicates that there is an open circuit in the via data line 321 through the cable replacement hole 33.

[0077] The specific driving timing of the above method is as follows: Figure 6 —As shown in Figure 8.

[0078] In the specific testing process, the open and short circuit conditions of the data line and scan line are first checked. If a short circuit or open circuit is detected in the data line, the open circuit detection method of the through-hole data line 321 through the replacement hole 33 is used for further judgment, thus achieving accurate judgment. Of course, it can be used flexibly in the specific implementation process.

[0079] In summary, although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An ink screen panel test circuit, comprising a first input terminal (51), a second input terminal (52), a third input terminal (53), a first thin film transistor quick detection circuit (1) and a second thin film transistor quick detection circuit (2); the first thin film transistor quick detection circuit (1) comprises a plurality of first thin film transistors connected in parallel, the gate of each first thin film transistor is electrically connected to the third input terminal (53), the source of each first thin film transistor is electrically connected to the first input terminal (51), and the drain of each first thin film transistor is electrically connected to a first end of a scanning line (31); the second thin film transistor quick detection circuit (2) comprises a plurality of second thin film transistors, the gate of each second thin film transistor is electrically connected to the third input terminal (53), the source of each second thin film transistor is electrically connected to the second input terminal (52), and the drain of each second thin film transistor is electrically connected to a first end of a data line (32); characterized in that: The first test circuit (4) is used for testing the open and short circuit conditions of the scan lines (31) and the data lines (32); The first test circuit (4) comprises a first sub-circuit (41) and a second sub-circuit (42); The first sub-circuit (41) comprises a plurality of third thin film transistors connected in series, each of the third thin film transistors is connected with a second end of the scan line (31) or a second end of the data line (32) at the gate, the source of the first thin film transistor is connected with the fourth input end (54), and the drain of the last thin film transistor is connected with the second output end (62); The second sub-circuit (42) comprises a plurality of thin film transistor groups, each of the thin film transistor groups is connected with the fifth input end (55), each of the thin film transistor groups is connected with the scan line (31) and the data line (32), and each of the thin film transistor groups is connected with the first output end (61); The thin film transistor group comprises a first type of thin film transistor group (421) and a second type of thin film transistor group (422), the first type of thin film transistor group (421) comprises a first type of No. 1 thin film transistor (421-1) and a first type of No. 2 thin film transistor (421-2), the source of the first type of No. 1 thin film transistor (421-1) is connected with the fifth input end (55), the gate of the first type of No. 1 thin film transistor (421-1) is connected with a second end of the data line (32), the drain of the first type of No. 1 thin film transistor (421-1) is connected with the source of the first type of No. 2 thin film transistor (421-2), the gate of the first type of No. 2 thin film transistor (421-2) is connected with a second end of the scan line (31), and the drain of the first type of No. 2 thin film transistor (421-2) is connected with the first output end (61); The second type of thin film transistor group (422) includes a second type of thin film transistor No. 1 (422-1), a second type of thin film transistor No. 2 (422-2) and a second type of thin film transistor No. 3 (422-3), the source electrode of the second type of thin film transistor No. 1 (422-1) is electrically connected with the drain electrode of the second type of thin film transistor No. 2 (422-2), the gate electrode of the second type of thin film transistor No. 1 (422-1) is electrically connected with the second end of one of the data lines (32), the drain electrode of the second type of thin film transistor No. 1 (422-1) is electrically connected with the source electrode of the second type of thin film transistor No. 2 (422-2), the source electrode of the second type of thin film transistor No. 2 (422-2) is also electrically connected with the fifth input end (55), the gate electrode of the second type of thin film transistor No. 2 (422-2) is electrically connected with the second end of one of the data lines (32), the drain electrode of the second type of thin film transistor No. 2 (422-2) is electrically connected with the source electrode of the second type of thin film transistor No. 3 (422-3), the gate electrode of the second type of thin film transistor No. 3 (422-3) is electrically connected with the second end of one of the scan lines (31), and the drain electrode of the second type of thin film transistor No. 3 (422-3) is electrically connected with the first output end (61).

2. The ink screen panel test circuit of claim 1, wherein: The first test circuit is located at the top of the display area (3).

3. The ink screen panel test circuit of claim 2, wherein: The second test circuit for testing the on-off state of the via data line (321) through the via hole (33) includes a plurality of fourth thin film transistors connected in series, the source electrode of the first end of the fourth thin film transistor is electrically connected with the fourth input end (54), the drain electrode of the last end of the fourth thin film transistor is electrically connected with the third output end (63), and the gate electrode of each fourth thin film transistor is electrically connected with the second end of the via data line (321).

4. The ink screen panel test circuit of claim 3, wherein: The second test circuit is located on one side of the via data line (321) in the display area (3).

5. A method of testing an ink screen panel test circuit, the method comprising: applying a voltage to the ink screen panel test circuit; and measuring a current through the ink screen panel test circuit. The ink screen panel test circuit suitable for any one of claims 1-4 includes a scan line (31) or data line (32) open circuit test method, a scan line (31) short circuit test method and a data line (32) short circuit test method. The scan line (31) or data line (32) open circuit test method includes the following steps: A1, input high level H1 to the first input end (51), input high level H2 to the second input end (52), and input high level H2 to the third input end, wherein H1 < H2; A2, input high level H1 or low level L to the fourth input end (54), and input high level H1 or low level L or ground signal to the fifth input end (55); A3, by using voltage detection device quantity detection first output end (61) or second output end (62), when the fourth input end (54) input high level H1, if the first output end (61) or the second output end (62) output high level signal H1, if the data line (32) and the scan line (31) are normal, if the first output end (61) or the second output end (62) output ground signal, it is proved that the scan line (31) or the data line (32) exists open circuit;When the fourth input end (54) input low level L, if the first output end (61) or the second output end (62) output low level signal L, if the data line (32) and the scan line (31) are normal, if the first output end (61) or the second output end (62) output ground signal, it is proved that the scan line (31) or the data line (32) exists open circuit; The scan line (31) short circuit test method comprises the following steps: B1, the first input end (51) is input low level L, the second input end (52) is input high level H2, the third input end is input high level H1, wherein H2<H1; B2, the fourth input end (54) is input high level H2 or input low level L or input ground signal, the fifth input end (55) is input high level H2 or input low level L; B3, by using voltage detection device quantity detection first output end (61) or second output end (62), when the fifth input end (55) input high level H2, if the first output end (61) or the second output end (62) output ground signal, it is proved that the scan line (31) is normal, if the first output end (61) or the second output end (62) output high level signal H2, it is proved that the scan line (31) exists short circuit;When the fifth input end (55) input low level L, if the first output end (61) or the second output end (62) output ground signal, it is proved that the scan line (31) is normal, if the first output end (61) or the second output end (62) output low level signal L, it is proved that the scan line (31) exists short circuit; The data line (32) short circuit test method comprises the following steps: C1, the first input end (51) is input low level H2, the second input end (52) is input high level L, the third input end is input high level H1, wherein H2<H1; C2, the fourth input end (54) is input high level H2 or input low level L or input ground signal, the fifth input end (55) is input high level H2 or input low level L; C3, by using voltage detection device to detect the first output end (61) or the second output end (62), when the fifth input end (55) inputs high level H2, if the first output end (61) or the second output end (62) outputs ground signal, it shows that the data line (32) is normal, if the first output end (61) or the second output end (62) outputs high level signal H2, it shows that the data line (32) exists short circuit;When the fifth input end (55) inputs low level L, if the first output end (61) or the second output end (62) outputs ground signal, it shows that the data line (32) is normal, if the first output end (61) or the second output end (62) outputs low level signal L, it shows that the data line (32) exists short circuit.

6. The method of claim 5, wherein: Also include the method for detecting the broken circuit of via data line (312) through the wire changing hole (33), comprising the following steps: Step one, input low level L to the first input end (51), input high level H2 to the second input end (52), input high level H1 to the third input end (53), H1>H2; Step two, input low level L to the fourth input end (54), input low level L to the fifth input end (55); Step three, by using voltage detection device to detect the voltage signal of the third output end (63), if low level signal can be detected, it shows that the via data line (321) through the wire changing hole (33) is normal, if ground signal is detected, it shows that the via data line (321) through the wire changing hole (33) exists broken circuit.

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