Container pipeline scheduling management method, system and medium
By configuring the scheduling attributes and time window scheduling strategies of containers and utilizing the timer management of the ARM+DSP heterogeneous multi-core processor, the problem of runtime interference between containers in the container system was solved, and the orderly and independent operation of containers was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN ACAD OF AEROSPACE TECH
- Filing Date
- 2022-12-27
- Publication Date
- 2026-05-12
AI Technical Summary
In a container system based on ARM+DSP heterogeneous multi-core processors, how can we ensure that each container runs independently, without affecting or interacting with each other, while sharing physical resources?
By configuring the scheduling-related attributes of containers, including container runtime (DT) and container interval (IT), a container linked list is established, and the next container to run is selected according to the static scheduling strategy of time window. The physical timers of ARM cores and DSP cores are used to provide timing services to control the operation of the container pipeline.
It enables containers to operate independently, in an orderly manner, without affecting each other, and interactively while sharing physical resources, thus ensuring the orderliness and independence of container scheduling.
Smart Images
Figure CN116149786B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of container pipeline scheduling and management technology, and in particular to a container pipeline scheduling and management method, system and medium based on an ARM+DSP heterogeneous multi-core processor. Background Technology
[0002] The concept of containers originated in the virtual machine field. With abundant physical resources, a single physical environment can support the simultaneous operation of multiple independent systems. Therefore, to ensure the independent operation of each subsystem while sharing physical resources, while maintaining order, independence, and interoperability, the concept of containers emerged. Containers based on ARM+DSP heterogeneous multi-core processors include both ARM containers based on virtualization technology (treating the client operating system as a container) and DSP containers based on multi-core DSPs (treating multiple DSP cores as a single container).
[0003] The core of container pipeline scheduling management based on ARM+DSP heterogeneous multi-core processors lies in container attribute configuration and container scheduling. Container attribute configuration refers to configuring which container attributes and how to configure them. Container scheduling mainly refers to the scheduling strategy, how to select the next container to run, and how to control the container pipeline operation. Summary of the Invention
[0004] The main objective of this invention is to provide a container pipeline scheduling and management method, system, and medium based on an ARM+DSP heterogeneous multi-core processor, aiming to achieve independent operation of each container while ensuring that they operate in an orderly manner, do not interfere with each other, and can interact with each other, under the premise of sharing physical resources.
[0005] To achieve the above objectives, this invention proposes a container pipeline scheduling and management method based on an ARM+DSP heterogeneous multi-core processor, the method comprising the following steps:
[0006] Configure the scheduling-related attributes of the container, including the container's continuous runtime DT and the container's interval time IT. The container includes ARM containers and DSP containers.
[0007] Based on the scheduling-related attributes of the containers and the pre-established container linked list, the next container to run is selected according to the time window static scheduling strategy, and the container pipeline operation is controlled.
[0008] A further technical solution of the present invention is that, in the step of selecting the next container to run according to the scheduling-related attributes of the container and controlling the operation of the container pipeline according to the time window static scheduling strategy, the execution of each container is activated by allocating time container windows, and each container window is defined by the start time of the container plus the expected continuous running time.
[0009] A further technical solution of the present invention is that the container linked list is a ready linked list composed of all ready containers, and the nodes in the ready linked list are arranged in the order in which the containers are installed and configured.
[0010] A further technical solution of the present invention is that container management uses the physical timer INTERVAL_TIMER of the ARM core to provide timing services, wherein the timing time is determined by the interval time of the currently running container, and initially the timing time is the interval time of the first container.
[0011] A further technical solution of the present invention is that the step of selecting the next container to run according to a time window static scheduling strategy based on the scheduling-related attributes of the container and a pre-established container linked list, and controlling the operation of the container pipeline, includes:
[0012] When an interrupt occurs at the set time, the next container to run is selected in the interrupt handler, and the timer's set time is reset to the interval for the next container to run.
[0013] If the next container to run is an ARM container, then start and run that candidate ARM container;
[0014] If the next running container is a DSP container, the current container continues to run and an inter-core interrupt is sent to the DSP container master core to start the candidate DSP container.
[0015] A further technical solution of the present invention is that the container linked list is composed of running container nodes, and the sorting order of the nodes is a time difference linked list composed of the difference between the DT value of the container to be run and the DT-IT value of the currently running container.
[0016] A further technical solution of the present invention is that container management uses the ARM core's internal physical timer DURATION_TIMER to provide timing services. The step of selecting the next container to run according to a time window static scheduling strategy based on the container's scheduling-related attributes and a pre-established container list, and controlling the container pipeline operation, includes:
[0017] The duration of each ongoing container installation is chained into the time difference linked list. The system waits for the DURATION_TIMER timer interrupt to occur and then iterates through the time difference linked list to execute the corresponding timed service.
[0018] A further technical solution of the present invention is that the steps of adding the duration of each ongoing container installation to the time difference linked list, waiting for the DURATION_TIMER timer interrupt to occur, and traversing the time difference linked list to execute the corresponding timed service include:
[0019] When the DURATION_TIMER timer interrupt occurs, enter the interrupt service routine to determine whether the expired container is a DSP container or an ARM container.
[0020] If the expired container is a DSP container, then a timed service is executed to send an inter-core notification to suspend the corresponding container;
[0021] If the expired container is an ARM container, then execute the ARM timed service to pause the corresponding container;
[0022] Start the DURATION_TIMER timer and exit the interrupt service.
[0023] To achieve the above objectives, the present invention also proposes a container pipeline scheduling and management system based on an ARM+DSP heterogeneous multi-core processor. The system includes a memory, a processor, and a container pipeline scheduling and management program based on an ARM+DSP heterogeneous multi-core processor stored on the processor. The container pipeline scheduling and management program based on an ARM+DSP heterogeneous multi-core processor is executed by the processor to perform the steps of the method described above.
[0024] To achieve the above objectives, the present invention also proposes a computer-readable storage medium storing a container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor. The container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor is executed by the processor to perform the steps of the method described above.
[0025] The beneficial effects of the container pipeline scheduling management method, system, and medium based on ARM+DSP heterogeneous multi-core processors of this invention are as follows: This invention configures the scheduling-related attributes of containers, including the container's continuous runtime (DT) and container interval (IT), and the containers include ARM containers and DSP containers; based on the scheduling-related attributes of the containers and a pre-established container list, the next container to run is selected according to a time window static scheduling strategy, and the container pipeline operation is controlled, thereby achieving independent operation of each container under the premise of orderly, non-influencing, and interactive operation while sharing physical resources. Attached Figure Description
[0026] Figure 1This is a flowchart illustrating a preferred embodiment of the container pipeline scheduling and management method based on ARM+DSP heterogeneous multi-core processors of the present invention.
[0027] Figure 2 This is a schematic diagram of container pipeline scheduling;
[0028] Figure 3 This is a diagram illustrating the container scheduling process;
[0029] Figure 4 This is a schematic diagram of the container's operation control process.
[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. 5. Detailed Implementation
[0031] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
[0032] Please refer to Figures 1 to 4 This invention proposes a container pipeline scheduling and management method based on ARM+DSP heterogeneous multi-core processors.
[0033] 0 as Figure 1 As shown, a preferred embodiment of the container pipeline scheduling and management method based on ARM+DSP heterogeneous multi-core processors of the present invention includes the following steps:
[0034] Step S10: Configure the scheduling-related attributes of the container. The scheduling-related attributes of the container include the container's continuous runtime DT and the container's interval time IT. The containers include ARM containers and DSP containers.
[0035] A key aspect of this invention's container pipeline scheduling management method based on ARM+DSP heterogeneous multi-core processors lies in the configuration of container attributes. This configuration primarily involves setting scheduling-related attributes, including container runtime (DT) and container interval (IT). The configuration of these attributes needs to follow certain rules to achieve pipeline scheduling. For example... Figure 2 As shown, when configuring containers, DT1 > IT1 and t2 > t1 should be satisfied. The same applies to other containers.
[0036] Step S20: Based on the scheduling-related attributes of the container and the pre-established container list, select the next container to run according to the time window 0 static scheduling strategy, and control the container pipeline operation.
[0037] In this embodiment, in the step of selecting the next container to run according to the time window static scheduling strategy based on the scheduling-related attributes of the container and controlling the operation of the container pipeline, the execution of each container is activated by allocating time container windows. Each container window is defined by the start time of the container plus the expected continuous running time.
[0038] 5. The container pipeline scheduling management method based on ARM+DSP heterogeneous multi-core processors in this invention adopts a static scheduling strategy according to time windows. Container scheduling follows a fixed, cyclical principle. The container scheduler ensures a time scheduling framework consisting of fixed execution periods, which can be periodically repeated throughout the system's operation. Each container is activated by allocating time container windows.
[0039] Container execution is defined by the sum of its start time and its expected runtime. Throughout the system, the execution sequence of containers is statically configured by system planners and stored in a scheduling configuration table, thus completing a defined container scheduling process. Each container uses processor resources at a pre-planned time.
[0040] As one implementation scheme, in this embodiment, the container linked list is a ready linked list composed of all ready containers, and the nodes in the ready linked list are arranged according to the order in which the containers are installed and configured.
[0041] Container management uses the ARM core's physical timer INTERVAL_TIMER to provide timing services. The timing interval is determined by the interval of the currently running container, and initially the timing interval is the interval of the first container.
[0042] Step S20, based on the container's scheduling-related attributes and the pre-established container list, selects the next container to run according to the time window static scheduling strategy. The steps for controlling the container pipeline operation include:
[0043] Step S21: When an interrupt occurs at the set time, select the next container to run in the interrupt handling and reset the timer's set time to the interval of the next container to run.
[0044] Step S22: If the next container to run is an ARM container, then start running the candidate ARM container.
[0045] Step S23: If the next running container is a DSP container, continue running the current container and send an inter-core interrupt to the DSP container master core to start the candidate DSP container.
[0046] In this embodiment, containers do not support preemptive scheduling. Except for actively calling the scheduling function, all other scheduling events occur when the scheduling timer generates an interrupt. Container management uses the ARM core's physical timer to provide timing services; this timer is called INTERVAL_TIMER. Its timing interval is determined by the interval of the currently running container. Initially, the timing interval is the interval of the first container. Upon reaching the timing interval, an interrupt is generated. In the interrupt handler, the next container to run is selected, and the timer's timing interval is reset to the interval of the next container to run. If the next running container is an ARM container, then the candidate ARM container is started; otherwise, the current container continues running, and an inter-core interrupt is sent to the DSP container's main core to start the candidate DSP container. Other containers in the pipeline scheduling follow the same principle.
[0047] As one implementation, in this embodiment, the container linked list consists of running container nodes, and the sorting order of the nodes is based on a time difference linked list composed of the difference between the DT value of the container to be run and the DT-IT of the currently running container.
[0048] Container management uses the ARM core's internal physical timer, DURATION_TIMER, to provide timing services. Based on the container's scheduling attributes and a pre-established container list, it selects the next container to run according to a static scheduling strategy with a time window. The steps for controlling the container pipeline include:
[0049] Step S204: String the duration of each container installation being executed into the time difference linked list, wait for the DURATION_TIMER timer interrupt to occur, and traverse the time difference linked list to execute the corresponding timed service.
[0050] Step S204, which involves adding the duration of each ongoing container installation to the time difference linked list, waiting for the DURATION_TIMER timer interrupt to occur, and traversing the time difference linked list to execute the corresponding timed service, specifically includes the following steps:
[0051] When the DURATION_TIMER timer interrupt occurs, enter the interrupt service routine to determine whether the expired container is a DSP5 container or an ARM container.
[0052] If the expiring container is a DSP container, then execute the scheduled service and send an inter-core notification to suspend the corresponding container;
[0053] If the expiring container is an ARM container, then execute the ARM scheduled service and pause the corresponding container;
[0054] Start the DURATION_TIMER timer and exit the interrupt service.
[0055] The timers in ARM containers are provided with timing services by ARM's virtual timers, while the timers in DSP containers...
[0056] Timing is provided by a physical timer within the DSP core, ensuring that the clocks of containers and the scheduler, as well as between containers, do not interfere with each other. The duration of a container is timed by another timer, called DURATION_TIMER, and then the time difference is inserted into the duration of each executing container.
[0057] In the linked list, the system waits for the DURATION_TIMER timer interrupt to occur and then traverses the list to execute the corresponding timer service. For ARM containers, the timer service pauses the execution of that container and switches to the next container. For DSP containers, the timer service sends an inter-core interrupt notification to stop the current DSP container from running.
[0058] like Figure 3 and Figure 4 As shown, in this embodiment, the container pipeline scheduler needs to maintain two container lists. One is a ready list consisting of all ready containers, with nodes arranged according to the order in which they were configured. The other is a difference list consisting of currently running container nodes, ordered based on the difference between the DT value of the container to be run and the DT-IT value of the currently running container. The ready list is a doubly linked circular list. When the INTERVAL_TIMER timer expires and generates a timer interrupt, scheduling occurs. At this time, the head node is selected from the ready list, and the container is...
[0059] The container corresponding to the node is used as a candidate container, and the head node is moved to the end of the linked list, completing the operation on the list during scheduling. The difference linked list is a doubly linear linked list. When scheduling occurs, the DT of the candidate container is calculated by difference and inserted into the corresponding position in the difference linked list. After the DURATION_TIMER timeout expires, the expired container node is deleted from the linked list.
[0060] The beneficial effects of the container pipeline scheduling management method based on ARM+DSP heterogeneous multi-core processors in this invention are as follows: Through the above technical solution, this invention configures the scheduling-related attributes of containers, including the container's continuous running time DT and the container interval time IT. Containers include ARM containers and DSP containers. Based on the scheduling-related attributes of the containers and a pre-established container list, the next container to run is selected according to a time window static scheduling strategy, and the container pipeline operation is controlled. This achieves independent operation of each container under the premise of orderly, non-influencing, and interactive operation while sharing physical resources.
[0061] To achieve the above objectives, the present invention also proposes a container pipeline scheduling management system based on an ARM+DSP heterogeneous multi-core processor. The container pipeline scheduling management system based on an ARM+DSP heterogeneous multi-core processor includes a memory, a processor, and a container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor stored on the processor. When the processor runs the container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor, it executes the steps described in the above embodiments, which will not be repeated here.
[0062] To achieve the above objectives, the present invention also proposes a computer-readable storage medium storing a container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor. When the processor runs the container pipeline scheduling management program based on the ARM+DSP heterogeneous multi-core processor, it executes the steps described in the above embodiments, which will not be repeated here.
[0063] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural changes made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A container pipeline scheduling and management method based on an ARM+DSP heterogeneous multi-core processor, characterized in that, The method includes the following steps: Configure the scheduling-related attributes of the container, including the container's continuous runtime DT and the container's interval time IT. The container includes ARM containers and DSP containers. Based on the scheduling-related attributes of the container and two pre-established container linked lists, the next container to run is selected according to the time window static scheduling strategy, and the container pipeline operation is controlled. The first container list in the two container lists is a ready list consisting of all ready containers. The nodes in the ready list are arranged in the order in which the containers are installed and configured. Container management uses the ARM core's physical timer INTERVAL_TIMER to provide timing services. The timing interval is determined by the interval of the currently running container. Initially, the timing interval is the interval of the first container. The step of selecting the next container to run according to a time window static scheduling strategy based on the scheduling-related attributes of the container and a pre-established container linked list, and controlling the operation of the container pipeline, includes: When an interrupt occurs at the set time, the next container to run is selected in the interrupt handler, and the timer's set time is reset to the interval for the next container to run. If the next container to run is an ARM container, then start and run that candidate ARM container; If the next running container is a DSP container, then continue running the current container and send an inter-core interrupt to the DSP container master core to start the candidate DSP container; The second container list in the two container lists consists of running container nodes. The nodes are sorted according to a time difference list composed of the difference between the DT value of the container to be run and the DT - IT value of the currently running container. Container management uses the ARM core's internal physical timer DURATION_TIMER to provide timing services. The steps of selecting the next container to run according to a time window static scheduling strategy based on the container's scheduling-related attributes and the pre-established container list, and controlling the container pipeline operation, include: The duration of each ongoing container installation is chained into the time difference linked list, waiting for the DURATION_TIMER timer interrupt to occur, and then the time difference linked list is traversed to execute the corresponding timed service. The steps of adding the duration of each ongoing container installation to the time difference linked list, waiting for the DURATION_TIMER timer interrupt to occur, and traversing the time difference linked list to execute the corresponding timed service include: When the DURATION_TIMER timer interrupt occurs, enter the interrupt service routine to determine whether the expired container is a DSP container or an ARM container. If the expired container is a DSP container, then a timed service is executed to send an inter-core notification to suspend the corresponding container; If the expired container is an ARM container, then execute the ARM timed service to pause the corresponding container; Start the DURATION_TIMER timer and exit the interrupt service.
2. The container pipeline scheduling and management method based on ARM+DSP heterogeneous multi-core processors according to claim 1, characterized in that, In the step of selecting the next container to run according to the scheduling-related attributes of the container and controlling the operation of the container pipeline according to the time window static scheduling strategy, the execution of each container is activated by allocating time container windows. Each container window is defined by the start time of the container plus the expected continuous running time.
3. A container pipeline scheduling and management system based on an ARM+DSP heterogeneous multi-core processor, characterized in that, The system includes a memory, a processor, and a container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor stored on the processor. The container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor is executed by the processor to perform the steps of the method as described in claim 1.
4. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor. The container pipeline scheduling management program based on an ARM+DSP heterogeneous multi-core processor is executed by the processor to perform the steps of the method described in claim 1.