Outbound transaction handling apparatus and method for a PCIe switch circuit

Abstract

The application provides a PCIe switching circuit egress port transaction processing device and method, which comprises a main control module, a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module which are connected with each other, the limit generation and load FIFO control module is connected with a parsing conversion module and two load FIFOs, the information generation and header FIFO control module is connected with a load receiving and conversion module and three packet header FIFOs, the parsing conversion module is connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is connected with an arbitration table and a loading module thereof, and the output ends of the three packet header FIFOs and the two load FIFOs are connected with reading and sending modules; the application classifies and stores the received transaction packets by using the three packet header FIFOs and the two load FIFOs, the write-in and read-out control of the transaction is simple and reliable, and the transaction of a part of delay-sensitive input ports cannot pass through the egress port for output in time.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to an out-port transaction processing device and method of a PCIe switching circuit. BACKGROUND

[0002] The PCIe bus is a third-generation high-performance IO bus after the first-generation EISA, ISA and VESA buses and the second-generation AGP, PCI and PCI-X buses, and is widely applied to computer systems.

[0003] In a PCIe system, a PCIe switching circuit is used to interconnect and communicate a plurality of electronic components or modules, the PCIe switching circuit generally has two or more PCIe ports, a port receiving transactions from external devices is referred to as an in-port, and a port pushing transactions out of the circuit is referred to as an out-port; the transactions inside the PCIe switching circuit that need to be exchanged include memory transactions, IO transactions, configuration transactions and message transactions. Among them, the memory write transaction and the message transaction packet are posted transaction packets (Posted TLP), and the IO transaction request, the configuration transaction request and the memory read transaction request packet are non-posted transaction packets (Non-Posted TLP, NP TLP), and the non-posted transaction packet needs to return a completion packet (Completion TLP) by the receiving device.

[0004] The out-port is a main component of the PCIe switching circuit, however, the transaction processing process of the PCIe circuit in the prior art is complex, the data integrity cannot be judged, and the length error processing process of the transaction is lacking. SUMMARY

[0005] In view of the problems in the prior art, the application provides an out-port transaction processing device and method of a PCIe switching circuit, the write and read control of the transaction is simple and reliable, and the out-port storage load has a dynamic adjustment function.

[0006] The application is achieved by the following technical scheme:

[0007] An out-port transaction processing device of a PCIe switching circuit, characterized in that it comprises a main control module, which is connected with a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is connected with a parsing conversion module and two load FIFOs, the information generation and header FIFO control module is connected with a load receiving and conversion module and three packet header FIFOs, the parsing conversion module is connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is connected with an arbitration table and its loading module, and the output ends of the three packet header FIFOs and the two load FIFOs are connected with a read and send module.

[0008] The input end of the information generation and header FIFO control module is connected with an out-port capacity upper limit register signal UprC and an out-port capacity lower limit register signal LowC, and outputs an inhibition request signal, the input end of the parsing conversion module and the load receiving and conversion module is connected with a request data signal and a configuration signal, the configuration signal also accesses the main control module, the input end of the port arbitration logic module is connected with a switching request signal, and the output end is connected with a response signal, the input end of the arbitration table and its loading module is connected with a PAT loading command signal and a PAT loading value signal, and the output end is connected with a PAT loading completion signal, the output end of the read and send module is connected with a send interface signal, and the output end is connected with a credit amount signal.

[0009] Preferably, the three packet header FIFOs comprise NPH_FIFO, CH_FIFO and PH_FIFO, and the two load FIFOs comprise CD_FIFO and PD_FIFO.

[0010] Preferably, the bit width of the NPH_FIFO is 165 bits, the bit width of the CH_FIFO and the PH_FIFO is 133 bits, and in each address unit of the three packet header FIFOs, 5 bits are serial number bits, and the other bits store transaction packet headers or ECRC.

[0011] Preferably, in each address unit of the two load FIFOs, an end bit and a termination bit are set, the bit width of the load FIFO is 66 bits in an x4 link port mode, and the bit width of the load FIFO is 130 bits in an x8 link port mode.

[0012] The storage bodies of the serial number bits, the header format Fmt, the TLP type Type and the length Length field in the packet header FIFO are realized by registers, and the storage bodies of the other bits are realized by memories.

[0013] Preferably, the arbitration table and its loading module are used to load the port arbitration table according to a loading command and generate a loading completion signal when the last clock cycle of the current switching transaction receiving is completed or when no transaction is received.

[0014] Preferably, the arbitration table and its loading module have a 32-phase port arbitration table (PAT) maintained internally in the egress port for use by the port arbitration logic.

[0015] An egress port transaction processing method of a PCIe switching circuit, comprising the following steps:

[0016] S101, the request data of the input port is parsed by the parsing and conversion module for transaction packet type and data length, and whether the corresponding type of cache is sufficient to store the request data is judged according to the transaction packet type and data length;

[0017] S102, after the completion of the current transaction processing, whether the host control logic is authorized to respond to the current switching request of the input port rotated by the internal port arbitration table according to the cache judged by the parsing and conversion module:

[0018] S103, when the receiving cache capacity of the current transaction is not enough to store the current transaction, the switching request of the input port rotated at present is not responded, the port arbitration jumps to the next phase, and the processing of the next input port is started from step S101;

[0019] S104, when the receiving cache capacity of the current transaction can store the current transaction, the switching request of the input port rotated at present is responded, the request data is written into the corresponding packet header FIFO and payload FIFO, and the generation and cache writing of the sequence number, end marker, termination bit and the like are completed.

[0020] S105, the read and send module reads one of the three packet header FIFOs and one possible payload FIFO according to the PCIE ordering rule according to the credit input, the sequence number of each packet header FIFO and other information, and sends the read transaction packet according to the interface requirements of the sending interface.

[0021] Preferably, the step S104 comprises the following steps:

[0022] A1, the parsing and conversion module receives the request data of the input port, and performs bit width conversion on the transaction packet header according to the bit width requirement of the packet header FIFO;

[0023] A2, the information generation and header FIFO control module stores the packet header of the completed packet or the packet header of the P transaction into the corresponding transaction packet header FIFO after bit width conversion, stores the NPH_FIFO and the possible data payload into the NPH_FIFO, and generates a sequence number according to the order of transaction reception when storing the packet header of the transaction into the corresponding transaction packet header FIFO, and writes the transaction packet header into the corresponding transaction packet header FIFO together with the bit width converted transaction packet header;

[0024] A3, the load receiving and conversion module receives the request data from the input port, and according to the indication of the configuration signal, the data load of the completion packet or the forwarding transaction packet request is bit-width converted according to the bit-width requirement of the corresponding load FIFO;

[0025] A4, the boundary generating and load FIFO control module receives the data load of the completion packet or the forwarding transaction packet output by the load receiving and conversion module, and caches the data load into the completion packet load FIFO or the PD_FIFO; an end marker is generated and written into the end bit of the FIFO when the last data load of each transaction is written; a termination marker is generated and written into the termination bit of the FIFO when the data load parsed through the transaction packet header does not match the actual requested load data amount or the current transaction has an ECRC check error; when the data load parsed through the transaction packet header is smaller than the actual requested load data amount, the corresponding load FIFO is written according to the data load number parsed through the packet header, and the excess load data is discarded.

[0026] Preferably, when the packet header FIFO is written in the step S104, the information generating and header FIFO control module calculates the total number of transaction packets stored in the three packet header FIFOs and compares the total number of transaction packets with the value of the out-end capacity upper limit register; when the total number of transaction packets is greater than or equal to the value of the out-end capacity upper limit register, the inhibit request signal is set to an active state to prohibit the input port from sending a new switching request.

[0027] Preferably, after the transaction packet header is read in the step S105, if the total number of transaction packets stored in the three packet header FIFOs is lower than the value of the out-end capacity lower limit register, the information generating and header FIFO control module clears the inhibit request signal to enable the switching request of the input port.

[0028] Compared with the prior art, the present application has the following beneficial technical effects:

[0029] The present application provides an out-end port transaction processing device and method of a PCIe switching circuit,

[0030] The application relates to a PCIe switch circuit outport transaction processing device, which comprises a main control module, a limit generation and load FIFO control module, an information generation and head FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is interconnected with an analysis conversion module and two load FIFOs, the information generation and head FIFO control module is interconnected with a load receiving and conversion module and three packet head FIFOs, the analysis conversion module is interconnected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is interconnected with an arbitration table and a loading module thereof, the output ends of the three packet head FIFOs and the two load FIFOs are connected with reading and sending modules; the input end of the information generation and head FIFO control module is connected with an outport capacity upper limit register signal UprC and an outport capacity lower limit register signal LowC, and outputs an inhibition request signal, the input ends of the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal also accesses the main control module, the input end of the port arbitration logic module is connected with a switching request signal, and the output end is connected with a response signal, the input end of the arbitration table and the loading module thereof is connected with a PAT loading command signal and a PAT loading value signal, and the output end is connected with a PAT loading completion signal, the output end of the reading and sending module is connected with a sending interface signal, and the output end is connected with a credit amount signal; the application has the following advantages: 1. three packet head FIFOs and two load FIFOs are used to classify and store received transaction packets, and the write-in and read-out control of the transaction is simple and reliable; 2. the serial number bit and the head label format Fmt in the packet head FIFO are stored by a register, and the storage body of other bits is stored by a memory, so that the storage body of the transaction has a smaller area overhead in the circuit, the key information stored by the register can be outputted without reading, and the read-out and sending scheduling of the stored transaction by the lower-level processing are facilitated; 3. by generating and writing an end mark when the last data load of each transaction is written, a write termination mark when the transaction fails and discarding the excess load data, the length error of the transaction of the outport is processed, and the data integrity of the load FIFO is ensured; 4. by reasonably setting the outport capacity upper limit register, the number of the buffered transactions in the outport is avoided to be too large, the transaction of a part of delay-sensitive input ports cannot pass through the outport and output in time, and the outport storage load has a dynamic adjusting function. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a principle block diagram of a PCIe switch circuit outport transaction processing device of the embodiment of the application.

[0032] Figure 2 It is the composition of a memory read request transaction packet in the NPH_FIFO of the embodiment. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] This invention provides a transaction processing device for the output port of a PCIe switching circuit, such as... Figure 1 As shown, the system includes a main control module, which is interconnected with a boundary generation and payload FIFO control module, an information generation and header FIFO control module, and a port arbitration logic module. The boundary generation and payload FIFO control module is interconnected with a parsing and conversion module and two payload FIFOs. The information generation and header FIFO control module is interconnected with a payload receiving and conversion module and three header FIFOs. The parsing and conversion module is interconnected with a payload receiving and conversion module and a port arbitration logic module. The port arbitration logic module is interconnected with an arbitration table and its loading module. The output terminals of the three header FIFOs and the two payload FIFOs are all connected to a read and send module.

[0037] The information generation and head FIFO control module is connected with an upper limit register signal UprC and a lower limit register signal LowC of an output port capacity, and outputs an inhibition request signal; the analysis conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal also accesses the main control module; the port arbitration logic module is connected with a switching request signal at the input end, and is connected with a response signal at the output end; the arbitration table and its loading module are connected with a PAT loading command signal and a PAT loading value signal at the input end, and are connected with a PAT loading completion signal at the output end; the reading and sending module is connected with a sending interface signal at the output end, and is connected with a credit amount signal at the output end.

[0038] It should be noted that the analysis conversion module is used for interacting with the configuration signal, the information generation and head FIFO control module, the main control module and the port arbitration logic, receiving the request data of the input port under the control of the main control module and the configuration signal, and performing analysis of the transaction packet type and the data length and conversion of the bit width, and judging whether the cache is sufficient to store the request data;

[0039] The information generation and head FIFO control module is used for storing the packet header of the complete packet or the packet header of the P transaction into the corresponding head FIFO under the control of the main control module, storing the packet header of the NP transaction and the possible data load into the NPH_FIFO, generating a serial number and writing the serial number into the corresponding transaction packet header FIFO together with the transaction packet header, and generating an inhibition request signal according to the value of the upper limit register of the output port capacity, the value of the lower limit register and the total number of transaction packets stored in the head FIFO.

[0040] The load receiving and conversion module is used for receiving the request data from the input port, and performing bit width conversion on the data load of the complete packet or the request of the forwarding transaction packet according to the indication of the configuration signal.

[0041] The limit generation and load FIFO control module is used for receiving the data load of the complete packet or the forwarding transaction packet output by the load receiving and conversion module, buffering the data load into the complete packet load FIFO or the P transaction load FIFO, generating an end marker and writing the end marker into the end bit of the FIFO when the last data load of each transaction is written, generating a termination marker and writing the termination marker into the termination bit of the FIFO when the data load parsed through the transaction packet header does not match the actual requested load data amount or the current transaction has an ECRC check error, and writing the transaction load FIFO according to the number of data loads parsed through the transaction packet header when the data load parsed through the transaction packet header is less than the actual requested load data amount, and discarding the excess load data.

[0042] The arbitration table and the loading module thereof are used for maintaining a port arbitration table inside the egress port for use by the port arbitration logic, loading the port arbitration table according to a loading command and generating a loading completion signal when the last clock cycle of the current switching transaction receiving is completed or no transaction is received;

[0043] The port arbitration logic module is used for determining whether to authorize the master control module to respond to the transaction switching request of the port rotated to the current round and give a response to the switching request according to the number of current transactions in the egress port buffer and the receiving buffer capacity of the current transaction after completion of the previous transaction processing.

[0044] The master control module is used for receiving the authorization of the port arbitration module, controlling the functions of the parsing and conversion module, the information generation and header FIFO control module, the payload receiving and conversion module, and the boundary generation and payload FIFO control module.

[0045] The reading and sending module is used for reading one of the three header FIFOs and possibly one payload FIFO according to the PCIE ordering rule and sending the read transaction packet according to the interface requirement of the sending interface according to the credit amount input, the sequence number of each header FIFO and other information; specifically, when the sequence number of the transaction packet at the head of a certain FIFO among the three header FIFOs is the smallest and the credit amount of the corresponding type transaction is greater than or equal to the credit amount required by the transaction packet, the transaction packet (including the header and the possible payload indicated by Fmt, Type and Length in the header) is read and sent according to the interface requirement of the sending interface; when the sequence number of the transaction packet at the head of a certain FIFO among the three header FIFOs is the smallest but the credit amount of the corresponding type transaction is less than the credit amount required by the transaction packet, one transaction packet (including the possible payload) that can surpass the transaction packet and has a credit amount of the corresponding type transaction greater than or equal to the credit amount required by the transaction packet is selected according to the PCIE ordering rule, and the read transaction packet is sent according to the interface requirement of the sending interface; since the storage bodies of the sequence number bit, Fmt, Type and Length in the header FIFO are registers, the reading and sending module can obtain the values of the sequence number, Fmt, Type and Length without reading the header FIFO, thereby facilitating the comparison of the sequence numbers of the three header FIFOs and the determination of the credit amount required by the transaction.

[0046] Preferably, the three header FIFOs include NPH_FIFO, CH_FIFO and PH_FIFO, and the two payload FIFOs include CD_FIFO and PD_FIFO, wherein the NPH_FIFO has a bit width of 165 bits, the CH_FIFO and PH_FIFO have a bit width of 133 bits, and each address unit of the three header FIFOs has 5 bits as sequence number bits and other bits storing transaction header or ECRC; each address unit of the two payload FIFOs is provided with one end bit and one termination bit, the payload FIFO has a bit width of 66 bits in x4 link port mode and a bit width of 130 bits in x8 link port mode; the sequence number bits, header format Fmt, TLP type Type and length Length field in the header FIFO are stored in a register, and other bits are stored in a memory. Figure 2 As shown in FIG. 8, a 64-bit memory read request transaction packet in the NPH_FIFO of the embodiment is composed of a memory read request transaction belonging to NP transaction, a sequence number of 5 bits, a transaction packet ECRC of 32 bits, and a transaction packet header of 127 bits. Figure 2 As shown in FIG. 8, a 64-bit memory read request transaction packet in the NPH_FIFO of the embodiment is composed of a memory read request transaction belonging to NP transaction, a sequence number of 5 bits, a transaction packet ECRC of 32 bits, and a transaction packet header of 127 bits.

[0047] Preferably, the arbitration table and the loading module thereof are used to load the port arbitration table according to the loading command and generate a loading completion signal when the last clock cycle of the current switching transaction receiving is completed or no transaction is received; the arbitration table and the loading module thereof internally maintain a 32-phase port arbitration table (PAT) for use by the port arbitration logic, and it needs to be noted that the port arbitration table is loaded according to the loading command and the loading completion signal is generated when the last clock cycle of the current switching transaction receiving is completed or no transaction is received, and specifically, when the arbitration table and the loading module thereof receive the port arbitration table loading command: if the egress port is not currently in the process of receiving a switching transaction of a certain input port, the internal maintenance port arbitration table of the egress port is immediately updated and an indication of completing the update is made; if the egress port is currently in the process of receiving a switching transaction of a certain input port, the received loading command is saved first, and then the internal maintenance port arbitration table is updated and an indication of completing the update is made when the last clock cycle of the current switching transaction receiving is completed; the port arbitration logic determines whether to authorize the master control module to respond to the transaction switching request of the port in the current rotation according to the number of current transactions in the egress port buffer and the receiving buffer capacity of the current transaction after the completion of the current transaction processing, and gives a response to the switching request; the rotation of the port is according to the port sequence represented by the 0-31 phase values of the above-mentioned internal 32-phase port arbitration table.

[0048] The application provides an egress port transaction processing method of a PCIe switching circuit, which comprises the following steps:

[0049] S101, the request data of the input port is parsed by the parsing and conversion module to analyze the transaction packet type and data length, and whether the corresponding type of cache is sufficient to store the request data is judged according to the transaction packet type and data length;

[0050] S102, after the completion of the current transaction, whether the cache judged by the parsing and conversion module is sufficient to store the corresponding request data is determined by the port arbitration logic to decide whether to authorize the master control logic to respond to the current exchange request of the input port rotated by the internal port arbitration table:

[0051] S103, when the receiving cache capacity of the current transaction is not enough to store the current transaction, the exchange request of the input port rotated at present is not responded, and the port arbitration jumps to the next phase, and the processing of the next input port is started from step S101;

[0052] S104, when the receiving cache capacity of the current transaction can store the current transaction, the exchange request of the input port rotated at present is responded, the request data is written into the corresponding packet header FIFO and payload FIFO, and the generation and cache writing of sequence number, end marker, termination bit and the like are completed;

[0053] S105, the read and send module reads one of the three packet header FIFOs and one possible payload FIFO according to the PCIE ordering rule according to the credit input, the sequence number of each packet header FIFO, and sends the read transaction packet according to the interface requirements of the sending interface.

[0054] Preferably, the step S104 comprises the following steps:

[0055] A1, the parsing and conversion module receives the request data of the input port, and performs bit width conversion on the transaction packet header according to the bit width requirement of the packet header FIFO;

[0056] A2, the information generation and header FIFO control module stores the packet header of the completed packet or the packet header of the P transaction into the corresponding transaction packet header FIFO after bit width conversion, stores the NPH_FIFO and the possible data payload into the NPH_FIFO, and generates a sequence number according to the order of transaction reception when storing the packet header of the transaction into the corresponding transaction packet header FIFO, and writes the transaction packet header into the corresponding transaction packet header FIFO together;

[0057] A3, the payload receiving and conversion module receives the request data from the input port, and performs bit width conversion on the data payload of the completed packet or the forwarded transaction packet request according to the indication of the configuration signal according to the bit width requirement of the corresponding payload FIFO;

[0058] A4, the boundary generating and load FIFO control module is used for receiving the data load of the complete packet or the forwarding transaction packet output by the load receiving and converting module, buffering the data load to the complete packet load FIFO or PD_FIFO, generating an end mark and writing the end bit of the FIFO when the last data load of each transaction is written, generating a termination mark and writing the termination bit of the FIFO when the data load parsed by the transaction packet header and the actual requested load data amount are inconsistent or the current transaction has an ECRC check error, and writing the corresponding load FIFO according to the data load number parsed by the packet header when the data load parsed by the transaction packet header is less than the actual requested load data amount, and discarding the excess load data.

[0059] Preferably, the information generating and header FIFO control module calculates the total number of transaction packets stored in the three packet header FIFOs and compares the total number with the value of the out port capacity upper limit register when the packet header FIFO is written in the step S104, and sets the inhibit request signal to the active state when the total number of transaction packets is greater than or equal to the value of the out port capacity upper limit register, thereby inhibiting the input port from sending a new switching request.

[0060] Preferably, the information generating and header FIFO control module clears the inhibit request signal and enables the switching request of the input port when the total number of transaction packets stored in the three packet header FIFOs is lower than the value of the out port capacity lower limit register after the transaction packet header is read in the step S105.

Claims

1. An egress port transaction handling apparatus of a PCIe switch circuit, characterized by, The PCIe switching circuit comprises a main control module, a limit generation and load FIFO control module, an information generation and header FIFO control module and a port arbitration logic module, the limit generation and load FIFO control module is connected with a parsing conversion module and two load FIFOs, the information generation and header FIFO control module is connected with a load receiving and conversion module and three packet header FIFOs, the parsing conversion module is connected with the load receiving and conversion module and the port arbitration logic module, the port arbitration logic module is connected with an arbitration table and a loading module thereof, and read and send modules are connected to output ends of the three packet header FIFOs and the two load FIFOs. The information generation and header FIFO control module is connected with an upper limit register signal UprC and a lower limit register signal LowC of an out port capacity, and outputs an inhibition request signal, the parsing conversion module and the load receiving and conversion module are connected with a request data signal and a configuration signal, the configuration signal is also connected to the main control module, the port arbitration logic module is connected with a switching request signal at an input end and an answer signal at an output end, the arbitration table and the loading module thereof are connected with a PAT loading command signal and a PAT loading value signal at an input end and a PAT loading completion signal at an output end, and the read and send modules are connected with a sending interface signal at an output end and a credit amount signal at an output end.

2. The egress port transaction handling apparatus of a PCIe switch circuit according to claim 1, wherein, The three packet header FIFOs comprise an NPH_FIFO, a CH_FIFO and a PH_FIFO, and the two load FIFOs comprise a CD_FIFO and a PD_FIFO.

3. The egress port transaction handling apparatus of a PCIe switch circuit according to claim 2, wherein, The NPH_FIFO has a bit width of 165 bits, the CH_FIFO and the PH_FIFO have a bit width of 133 bits, and in each address unit of the three packet header FIFOs, 5 bits are serial number bits, and the other bits store transaction packet headers or ECRCs.

4. The apparatus of claim 2, wherein, Each address unit of the two load FIFOs is provided with an end bit and a termination bit, the load FIFO has a bit width of 66 bits in an x4 link port mode and a bit width of 130 bits in an x8 link port mode. Serial number bits, a header format Fmt, a TLP type Type and a length Length field in the packet header FIFO are stored in a register, and the other bits are stored in a memory.

5. The transaction handling apparatus of a PCIe switch circuit's egress port according to claim 1, wherein, The arbitration table and the loading module thereof are used for loading a port arbitration table according to a loading command and generating a loading completion signal when a last clock cycle of a current switching transaction is received or no transaction is received.

6. The egress port transaction handling apparatus of a PCIe switch circuit according to claim 5, wherein, The arbitration table and the loading module thereof maintain a 32-phase port arbitration table (PAT) in an out port, which is used by the port arbitration logic.

7. A method for processing outgoing port transactions of a PCIe switching circuit, characterized in that, The out port transaction processing device of the PCIe switching circuit according to any one of claims 1-6 comprises the following steps: In S101, the parsing conversion module parses transaction packet types and data lengths of request data of an input port, and judges whether a buffer of a corresponding type is sufficient to store the request data according to the transaction packet types and the data lengths. S102. After the current transaction is completed, the port arbitration logic determines whether to authorize the main control logic to respond to the current exchange request of the input port that has been rotated through the internal port arbitration table, based on whether the cache determined by the parsing and conversion module is sufficient to store the corresponding request data. S103. When the receive buffer capacity of the current transaction is insufficient to store the current transaction, the exchange request of the input port to which the current round is turned is not responded to, the port arbitration jumps to the next phase, and the processing of the next input port starts from step S101. S104. When the receive buffer capacity of the current transaction can store the current transaction, respond to the exchange request of the input port to which the current round is turned, write the request data into the corresponding header FIFO and payload FIFO, and complete the generation and buffer writing of sequence number, end mark, termination bit, etc. S105. The reading and sending module reads one of the three header FIFOs and one possible payload FIFO according to the PCIE sorting rules based on the credit input, the sequence number of each header FIFO, and other information, and sends the read transaction packet according to the interface requirements of the sending interface.

8. The method of Claim 7, wherein, Step S104 includes the following steps: A1. The parsing and conversion module receives the request data from the input port and converts the transaction packet header according to the bit width requirement of the packet header FIFO. A2. The information generation and header FIFO control module stores the header of the completed packet or the header of the P transaction after bit width conversion into the corresponding transaction header FIFO, stores the NPH_FIFO and possible data payload into the NPH_FIFO, and when storing the transaction header into the corresponding transaction header FIFO, it generates a sequence number according to the order of transaction reception and writes it together with the bit width converted transaction header into the corresponding transaction header FIFO. A3. The payload receiving and conversion module receives the request data from the input port and, according to the instructions of the configuration signal, converts the data payload of the completed packet or forwarding transaction packet request into bit width according to the bit width requirements of the corresponding payload FIFO. A4. The boundary generation and payload FIFO control module receives the data payload of the completion packet or forwarding transaction packet output by the payload receiving and conversion module and caches it in the completion packet payload FIFO or PD_FIFO. When the last data payload is written in each transaction, an end marker is generated and written to the end bit of the FIFO. When the data payload parsed from the transaction header does not match the actual requested payload data amount or when an ECRC check error occurs in the current transaction, a termination marker is generated and written to the termination bit of the FIFO. When the data payload parsed from the transaction header is less than the actual requested payload data amount, the corresponding payload FIFO is written according to the number of data payloads parsed from the header, and the excess payload data is discarded.

9. The method of claim 7, wherein the method further comprises: receiving a request from the root complex to transmit a packet to the device; and transmitting the packet to the device. When writing to the packet header FIFO in step S104, the information generation and header FIFO control module calculates the total number of transaction packets stored in the three types of packet header FIFOs and compares it with the value of the output capacity limit register. When the total number of transaction packets is greater than or equal to the value of the output capacity limit register, the request signal will be set to an active state, and the input port will be prohibited from sending new exchange requests.

10. The method of Claim 7, wherein the method further comprises: If the total number of transaction packets stored in the three packet header FIFOs is lower than the value of the lower limit register of the out port capacity, the information generation and header FIFO control module clears the disable request signal and enables the switch request of the input port.

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