A Dual-Firmware Intelligent Boot System for Military-Reinforced Computing Platforms

Abstract

The present invention relates to a dual-firmware intelligent startup system for a military reinforced computing platform, belonging to the field of computer system design. The system of the present invention comprises: a CPU, a CPLD, a BMC, Flash 1, Flash 2, load switch 1, load switch 2, and a platform power supply. Dual-firmware startup is performed through communication between the CPU, CPLD, and BMC. The CPLD switches the dual-flash read / write channels to flexibly select the firmware required for the current startup. If problems occur in either of the dual-firmware flashes, the CPLD can communicate with the BMC to notify it to perform an online firmware refresh. The system allows for flexible selection of the startup firmware type and online firmware updates, significantly reducing maintenance time and shortening maintenance time.

Description

Technical Field

[0001] The present invention belongs to the field of computer system design, and in particular relates to a dual-firmware intelligent startup system for a military reinforced computing platform. Background Art

[0002] The current military hardened computing platform uses a single BIOS firmware solution. When the firmware Flash is physically damaged or has data errors, resulting in a boot failure or when a specific firmware needs to be switched, the system must be disassembled to replace the current firmware or update the firmware online through the BMC. Problems with existing technologies include:

[0003] 1. Military ruggedized computing platforms use a single BIOS firmware solution. When the firmware flash becomes physically damaged or has data errors, causing it to fail to boot, the system must be disassembled and replaced. Military computing platforms require the ability to quickly repair and rework faulty equipment. Disassembling and replacing the flash memory results in a prolonged repair window.

[0004] 2. The computing platform needs to implement a special firmware function that is only used in a single scenario and has a certain timeliness, such as port control. In a single-firmware solution, if this function is required, the device must be disassembled and the firmware replaced.

[0005] 3. If the dual-Flash dual-firmware platform still cannot start, you need to be able to refresh the firmware. Summary of the Invention

[0006] (1) Technical issues to be solved

[0007] The technical problem to be solved by the present invention is how to provide a dual-firmware intelligent startup system for a military reinforced computing platform to solve the problem of using a single BIOS firmware solution. When the firmware Flash is physically damaged or has data errors, resulting in an inability to boot or when switching to specific required firmware is required, the current firmware needs to be disassembled and replaced.

[0008] (2) Technical solution

[0009] In order to solve the above technical problems, the present invention proposes a dual-firmware intelligent startup system for a military reinforced computing platform, which includes: a CPU, a CPLD, a BMC, Flash1, Flash2, a load switch 1, a load switch 2 and a platform power supply;

[0010] Connect the CPU_QSPI interface for reading firmware in the CPU to the CPLD. Connect the UP_QSPI interface in the BMC for online firmware upgrades for Flash1 and Flash2 to the CPLD. Connect the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2 to the CPLD. Flash1 is used to store Firmware 1, and Flash2 is used to store Firmware 2. The platform power supply supplies power to Flash1 through load switch 1, and the platform power supply supplies power to Flash2 through load switch 2.

[0011] The CPU and CPLD also transmit information through GPIO and UART interfaces. The UART interface is used to transmit information on whether the firmware is successfully started.

[0012] The BMC and CPLD also communicate via the IIC bus. The BMC provides a management interface for selecting the order in which the firmware in Flash 1 and Flash 2 are booted. The information transmitted via the IIC bus includes the boot order and whether the firmware boot is successful.

[0013] The CPLD connects to the platform power supply through GPIO and controls the platform power on and off. The CPLD controls load switch 1 and load switch 2 through GPIO to control the power supply to Flash 1 and Flash 2.

[0014] Dual Flash is used to store two boot firmware copies. Dual firmware boot is performed through communication between the CPU, CPLD, and BMC. The CPLD switches the dual Flash read and write channels to flexibly select the firmware required for the current boot. If there is a problem with both firmware Flash copies, the CPLD communicates with the BMC and notifies the BMC to perform an online firmware refresh.

[0015] Dual firmware booting may occur in the following situations:

[0016] Case 11: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. The Flash1 firmware is booted successfully.

[0017] Case 12: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. The Flash1 firmware is booted but fails. The system reports a boot failure for firmware 1.

[0018] Case 13: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2 firmware. The Flash2 firmware boots successfully.

[0019] Case 14: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2 firmware. Booting Flash2 firmware fails, and the system issues an alarm indicating that booting of firmware 2 has failed.

[0020] Case 15: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. By default, Flash1 is booted, but the boot fails. The system issues an alarm indicating that firmware 1 failed to boot. The BMC specifies booting Flash2, but firmware 2 fails to boot. The system issues an alarm indicating that firmware 2 failed to boot.

[0021] Case 16: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. The default boot from Flash1 fails. The system alarms that firmware 1 fails to boot. The BMC specifies booting from Flash2, and firmware 2 boots successfully.

[0022] The following situations may occur when the BMC is flashing the firmware online:

[0023] Case 21: BMC selects to update firmware 1;

[0024] Case 22: BMC selects to update firmware 2;

[0025] Case 23: The BMC selects to update firmware 1 or firmware 2.

[0026] (3) Beneficial effects

[0027] This invention proposes a dual-firmware intelligent boot system for a military reinforced computing platform. This system uses dual Flash memory to store two copies of the boot firmware. Through communication between the CPU, CPLD, and BMC, the CPLD switches the dual Flash read / write channels, ensuring stable platform boot and allowing flexible selection of the current boot firmware. If problems arise in either firmware Flash memory, the CPLD communicates with the BMC, informing it to perform an online firmware refresh. This system allows for flexible selection of the boot firmware type and online firmware updates, significantly reducing maintenance and support time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Design a block diagram for the solution of the present invention;

[0029] Figure 2 This is a flow chart of the dual-firmware intelligent startup method for the military reinforced computing platform of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0031] Glossary:

[0032] BMC Web: BMC management interface power-on self-test test

[0033] BMC: Base-Board Management Controller

[0034] CPLD: bank: CPLD logic array

[0035] UART: serial port

[0036] The present invention is a dual-firmware intelligent startup solution for Feiteng platform military reinforced computing equipment, which relates to the technical field of firmware startup solution selection and firmware automatic repair when the computing platform is powered on.

[0037] The present invention uses dual Flash to store two boot firmware copies. Through communication between the CPU, CPLD, and BMC, the CPLD switches the dual Flash read / write channels, ensuring a stable platform startup and allowing flexible selection of the current boot firmware. If problems occur in either firmware Flash, the CPLD communicates with the BMC to notify it to perform an online firmware refresh.

[0038] In view of the problems in the background technology, the present invention can achieve:

[0039] 1. When the present invention uses a solution of dual Flash with the same firmware (Flash1 and Flash2 are loaded with the same firmware), the maintenance time can be greatly reduced and the guarantee time can be shortened.

[0040] 2. When the present invention uses a solution with dual Flash and different firmware, the type of startup firmware can be flexibly selected in the BMC management interface.

[0041] 3. The CPLD of the present invention communicates with the BMC, and the CPLD informs the BMC that both firmwares fail to start. The BMC management interface can be entered into the firmware refresh state, and the firmware of Flash1 and Flash2 can be refreshed simultaneously or individually.

[0042] The present invention proposes a dual-firmware intelligent startup system for a military reinforced computing platform. The overall design scheme is shown in the following diagram: Figure 1 The system includes: CPU, CPLD, BMC, Flash1, Flash2, load switch 1, load switch 2 and platform power supply;

[0043] Connect the CPU_QSPI interface for reading firmware in the CPU to the CPLD. Connect the UP_QSPI interface in the BMC for online firmware upgrades for Flash1 and Flash2 to the CPLD. Connect the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2 to the CPLD. Flash1 is used to store Firmware 1, and Flash2 is used to store Firmware 2. The platform power supply supplies power to Flash1 through load switch 1, and the platform power supply supplies power to Flash2 through load switch 2.

[0044] The CPU and CPLD also transmit information through GPIO and UART interfaces. The UART interface is used to transmit information on whether the firmware is successfully started.

[0045] The BMC and CPLD also communicate via the IIC bus. The BMC provides a management interface for selecting the order in which the firmware in Flash 1 and Flash 2 are booted. The information transmitted via the IIC bus includes the boot order and whether the firmware boot is successful.

[0046] The CPLD connects to the platform power supply through GPIO and controls the platform power on and off. The CPLD controls load switch 1 and load switch 2 through GPIO to control the power supply to Flash 1 and Flash 2.

[0047] Dual Flash memories store two copies of the boot firmware, enabling dual-firmware booting through communication between the CPU, CPLD, and BMC. The CPLD switches the dual Flash read / write channels, ensuring a stable platform boot and allowing flexible selection of the current boot firmware. If problems occur in either Flash memory, the CPLD communicates with the BMC, instructing it to perform an online firmware refresh. BMC online firmware refresh allows users to perform a firmware refresh through the management interface of a remote computer.

[0048] like Figure 2 As shown, the dual-firmware intelligent startup method for a military reinforced computing platform of the present invention includes:

[0049] There are the following situations for dual firmware startup in the present invention.

[0050] Case 11: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. Booting Flash1 firmware succeeds.

[0051] Case 12: Both Flash 1 and Flash 2 exist, but the BMC has not specified a boot firmware or has specified booting from firmware 1. The Flash 1 firmware is booted, but the boot fails. The system issues an alarm indicating that the firmware 1 boot failed.

[0052] Case 13: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2. The Flash2 firmware boots successfully.

[0053] Case 14: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2. The Flash2 firmware fails to boot, and the system issues an alarm indicating that booting from Flash2 failed.

[0054] Case 15: Both Flash 1 and Flash 2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. By default, booting from Flash 1 fails. The system issues an alarm indicating that booting from firmware 1 failed. The BMC specifies booting from Flash 2, but firmware 2 fails to boot, and the system issues an alarm indicating that booting from firmware 2 failed.

[0055] Case 16: Both Flash 1 and Flash 2 exist, but the BMC does not specify a boot firmware or specifies firmware 1. By default, Flash 1 is booted, but the boot fails. The system issues an alarm indicating that firmware 1 failed to boot. The BMC specifies Flash 2 as the boot firmware, and firmware 2 boots successfully.

[0056] In the present invention, the BMC updates the Flash1 and Flash2 firmware in the following situations.

[0057] Case 21: BMC selects firmware update 1.

[0058] Case 22: BMC selects to update firmware 2.

[0059] Case 23: The BMC selects to update firmware 1 or firmware 2.

[0060] Case 11 The startup process includes:

[0061] After the platform is connected to the power supply, the standby power supply is first started, and the BMC and CPLD are powered on using the BMC standby power supply. One minute after the BMC is started, if the user does not select the order of booting firmware in the BMC management interface (Web), the BMC defaults to booting from firmware 1. At this time, the CPLD defaults to logically connecting the CPU-side CPU_QSPI interface with the data interface of QSPI1 of Flash1, and simultaneously turning on load switch 1 and load switch 2 to power on Flash1 and Flash2. If the CPLD detects that Flash1 is in place, the CPLD turns off load switch 2 and powers on the platform in sequence after an interval of 5 seconds. Turning off load switch 2 can avoid the influence of the firmware in Flash2 and can also prevent the CPLD from erroneously operating firmware 2. At this time, the CPU will automatically read the firmware in Flash1 and start by default. In the present invention, the CPU startup information is connected to the CPLD via the UART interface. The CPLD determines the current firmware startup status by capturing the boot complete flag in the UART interface. When the CPLD parses the boot complete flag, it indicates that the system has successfully started.

[0062] Case 12 The startup process includes:

[0063] After the platform is connected to power, the standby power supply is first activated. The BMC and CPLD are powered on using the BMC standby power supply. One minute after the BMC boots, if the user does not select the boot firmware order on the BMC management interface (web), the BMC defaults to booting from firmware 1. The CPLD then logically connects the CPU's CPU_QSPI interface to the QSPI1 data interface of Flash 1, simultaneously turning on load switches 1 and 2 to power on Flash 1 and Flash 2. If the CPLD detects that Flash 1 is in place, it turns off load switch 2 and, after a 5-second interval, powers on the platform in sequence. The CPU automatically reads the firmware from Flash 1 and boots. The CPLD does not detect the boot complete flag on the CPU's UART interface, determining that the Flash 1 firmware boot failed, and the BMC issues a warning indicating that the firmware 1 boot failed.

[0064] Case 13 The startup process includes:

[0065] After the platform is connected to the power supply, the standby power supply is first started. The BMC and CPLD use the BMC standby power supply to complete power-up. One minute after the BMC starts, the user specifies to start from the Flash2 firmware in the BMC management interface (Web). At this time, the CPLD defaults to logically connect the CPU-side CPU_QSPI interface with the data interface of Flash2's QSPI2, and simultaneously opens load switches 1 and 2 to power on Flash1 and Flash2. If the CPLD detects that Flash2 is in place, the CPLD closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash2 and starts by default. In the present invention, the CPU startup information is connected to the CPLD via the UART interface. The CPLD determines the current firmware startup status by capturing the boot complete flag in the UART interface. When the CPLD parses the boot complete flag, the system startup is successful.

[0066] Case 14 The startup process includes

[0067] After the platform is connected to the power supply, the standby power supply is first started, and the BMC and CPLD are powered on using the BMC standby power supply; one minute after the BMC is started, the user specifies to start from the Flash2 firmware in the BMC management interface (Web). At this time, the CPLD logically connects the CPU_QSPI interface on the CPU side with the data interface of the QSPI2 of Flash2 by default, and simultaneously opens load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash2 is in place, the CPLD closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash2 and starts by default; in the present invention, the startup information of the CPU is connected to the CPLD through the UART interface. The CPLD does not determine the firmware startup status at this time by capturing the boot complete flag in the UART interface. The CPLD does not capture the boot complete flag, and the BMC alarms that the Flash2 firmware startup fails.

[0068] Case 15 The startup process includes:

[0069] After the platform is connected to the power supply, the standby power is started first, and the BMC and CPLD are powered on using the BMC standby power. One minute after the BMC is started, if the user does not specify the startup firmware or specifies to start from Flash1 firmware in the BMC management interface (Web), the CPLD will logically connect the CPU_QSPI interface on the CPU side with the data interface of QSPI1 of Flash1 by default, and turn on load switch 1 and load switch 2 at the same time to power on Flash1 and Flash2. If the CPLD detects that Flash1 is in place, the CPLD will turn off load switch 2 and power on the platform in sequence after an interval of 5 seconds. At this time, the CPU will automatically read the firmware in Flash1 and start by default. The CPLD does not capture the boot firmware in the UART interface. The complete flag indicates that the firmware startup has failed, and the BMC alarm indicates that the Flash1 firmware startup has failed. On the BMC interface, reselect the Flash2 firmware startup. At this point, the CPLD logically connects the CPU_QSPI interface on the CPU side to the QSPI2 data interface of Flash2 by default, and simultaneously opens load switches 1 and 2 to power on Flash1 and Flash2. If the CPLD detects that Flash2 is in place, it closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this point, the CPU automatically reads the firmware in Flash2 and starts. The CPLD detects the boot complete flag on the UART interface and determines that the firmware startup has succeeded.

[0070] Case 16 The startup process includes:

[0071] After the platform is connected to power, the standby power is first activated. The BMC and CPLD are powered on using the BMC standby power. One minute after the BMC starts, if the user does not specify the boot firmware or specifies to boot from Flash1 on the BMC management interface (web), the CPLD will logically connect the CPU's CPU_QSPI interface to the QSPI1 data interface of Flash1 by default, and simultaneously open load switches 1 and 2 to power on Flash1 and Flash2. If the CPLD detects that Flash1 is in place, it closes load switch 1 and then powers on the platform in sequence after a 5-second interval. The CPU will automatically read the firmware from Flash1 and boot. If the CPLD does not capture the boot complete flag on the UART interface, it determines that the firmware boot has failed, and the BMC will alarm that the Flash1 firmware boot has failed. If you reselect to boot from Flash2 on the BMC interface, the CPLD will logically connect the CPU's CPU_QSPI interface to the QSPI2 data interface of Flash2 by default. Simultaneously turn on load switches 1 and 2 to power on Flash 1 and Flash 2. If the CPLD detects that Flash 2 is in place, it turns off load switch 1 and then powers on the platform in sequence after a 5-second interval. The CPU automatically reads the firmware from Flash 2 and starts it. If the CPLD does not detect the boot complete flag on the UART interface, it determines that the firmware startup has failed. The BMC issues an alarm indicating that both Flash 1 and Flash 2 have failed to start.

[0072] When the BMC performs online firmware update, the following occurs:

[0073] The situations 21 where the BMC performs online firmware flashing include:

[0074] After both Flash1 and Flash2 firmware fail to boot, the BMC selects a firmware refresh in the management interface. If Flash1 firmware is updated in the management interface, the CPLD logically disconnects the CPU's CPU_QSPI interface from Flash1's QSPI1 interface and Flash2's QSPI2 interface. Simultaneously, the BMC's UP_QSPI interface is logically connected to Flash1's QSPI1 interface. The BMC then updates Flash1's firmware.

[0075] The situations 22 where the BMC performs online firmware flashing include:

[0076] After both Flash1 and Flash2 firmware fail to boot, the BMC selects firmware refresh in the management interface. If Flash2 firmware is updated in the management interface, the CPLD logically disconnects the CPU-side CPU_QSPI interface from the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2. At the same time, the CPLD logically connects the BMC-side UP_QSPI interface to the QSPI2 interface of Flash2. The BMC then updates the Flash2 firmware.

[0077] The situations 23 where the BMC performs online firmware flashing include:

[0078] After both Flash1 and Flash2 fail to boot, the BMC selects a firmware refresh in the management interface. If you select Update Flash1 and Flash2 in the management interface, the CPLD logically disconnects the CPU's CPU_QSPI interface from Flash1's QSPI1 interface and Flash2's QSPI2 interface. Simultaneously, the BMC's UP_QSPI interface logically connects Flash1's QSPI1 interface and Flash2's QSPI2 interface. The BMC then updates the firmware of Flash1 and Flash2 simultaneously, and the updated firmware is the same.

[0079] In the military reinforced computing platform, dual-version firmware can be used to select firmware startup items through the BMC, and users can switch the startup firmware according to actual conditions.

[0080] The dual-version firmware of the present invention in the military reinforced computing platform can selectively update a single Flash firmware or synchronously update two Flash firmwares through the BMC.

[0081] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A dual-firmware intelligent startup system for a military reinforced computing platform, characterized in that: The system includes: CPU, CPLD, BMC, Flash1, Flash2, load switch 1, load switch 2 and platform power supply; Connect the CPU_QSPI interface for reading firmware in the CPU to the CPLD. Connect the UP_QSPI interface in the BMC for online firmware upgrades for Flash1 and Flash2 to the CPLD. Connect the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2 to the CPLD. Flash1 is used to store Firmware 1, and Flash2 is used to store Firmware 2. The platform power supply supplies power to Flash1 through load switch 1, and the platform power supply supplies power to Flash2 through load switch 2. The CPU and CPLD also transmit information through GPIO and UART interfaces. The UART interface is used to transmit information on whether the firmware is successfully started. The BMC and CPLD also communicate via the IIC bus. The BMC provides a management interface for selecting the order in which the firmware in Flash 1 and Flash 2 are booted. The information transmitted via the IIC bus includes the boot order and whether the firmware boot is successful. The CPLD connects to the platform power supply through GPIO and controls the platform power on and off. The CPLD controls load switch 1 and load switch 2 through GPIO to control the power supply to Flash 1 and Flash 2. Dual Flash is used to store two boot firmware copies. Dual firmware boot is performed through communication between the CPU, CPLD, and BMC. The CPLD switches the dual Flash read and write channels to flexibly select the firmware required for the current boot. If there is a problem with both firmware Flash copies, the CPLD communicates with the BMC and notifies the BMC to perform an online firmware refresh. Dual firmware startup has the following situations: Case 11: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. The Flash1 firmware is booted successfully. Case 12: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. The Flash1 firmware is booted but fails. The system reports a boot failure for firmware 1. Case 13: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2 firmware. The Flash2 firmware boots successfully. Case 14: Both Flash1 and Flash2 exist, and the BMC specifies booting from Flash2 firmware. Booting Flash2 firmware fails, and the system issues an alarm indicating that booting of firmware 2 has failed. Case 15: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. By default, Flash1 is booted, but the boot fails. The system issues an alarm indicating that firmware 1 failed to boot. The BMC specifies booting Flash2, but firmware 2 fails to boot. The system issues an alarm indicating that firmware 2 failed to boot. Case 16: Both Flash1 and Flash2 exist, but the BMC does not specify a boot firmware or specifies booting from firmware 1. By default, booting from Flash1 fails. The system alarms that firmware 1 fails to boot. The BMC specifies booting from Flash2, and firmware 2 boots successfully. The following situations may occur when the BMC is flashing the firmware online: Case 21: BMC selects to update firmware 1; Case 22: BMC selects to update firmware 2; Case 23: The BMC selects to update firmware 1 or firmware 2.

2. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: The startup process in case 11 includes: after the platform is connected to the power supply, the standby power is first started, and the BMC and CPLD are powered on using the BMC standby power; one minute after the BMC starts, if the user does not select the startup firmware order in the BMC management interface, the BMC defaults to starting from firmware 1; at this time, the CPLD defaults to logically connecting the CPU-side CPU_QSPI interface with the data interface of QSPI1 of Flash1, and simultaneously turning on load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash1 is in place, the CPLD turns off load switch 2 and powers on the platform in sequence after an interval of 5 seconds; at this time, the CPU automatically reads the firmware in Flash1 and starts; the CPU startup information is connected to the CPLD through the UART interface, and the CPLD determines the current firmware startup status by capturing the bootcomplete flag in the UART interface. When the CPLD parses the bootcomplete flag, it means that the system has successfully started.

3. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: The startup process in case 12 includes: after the platform is connected to the power supply, the standby power is started first, and the BMC and CPLD are powered on using the BMC standby power. One minute after the BMC starts, if the user does not select the startup firmware order in the BMC management interface, the BMC defaults to starting from firmware 1. At this time, the CPLD defaults to logically connecting the CPU_QSPI interface on the CPU side to the data interface of QSPI1 of Flash1, and simultaneously turning on load switch 1 and load switch 2 to power on Flash1 and Flash2. If the CPLD detects that Flash1 is in place, the CPLD turns off load switch 2 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash1 and starts. The CPLD does not capture the bootcomplete flag in the CPUUART interface and determines that the Flash1 firmware startup has failed. The BMC then alarms that the firmware 1 startup has failed.

4. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: The startup process in case 13 includes: after the platform is connected to the power supply, the standby power is first started, and the BMC and CPLD are powered on using the BMC standby power; one minute after the BMC starts, the user specifies to boot from the Flash2 firmware in the BMC management interface. At this time, the CPLD logically connects the CPU-side CPU_QSPI interface with the data interface of Flash2's QSPI2 by default, and simultaneously opens load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash2 is in place, the CPLD closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash2 and starts by default; the CPU startup information is connected to the CPLD through the UART interface, and the CPLD determines the current firmware startup status by capturing the boot complete flag in the UART interface; when the CPLD parses the bootcomplete flag, the system startup is successful.

5. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: The startup process in case 14 includes: after the platform is connected to the power supply, the standby power supply is first started, and the BMC and CPLD are powered on using the BMC standby power supply; one minute after the BMC starts, the user specifies to start from the Flash2 firmware in the BMC management interface. At this time, the CPLD logically connects the CPU-side CPU_QSPI interface with the data interface of Flash2's QSPI2 by default, and simultaneously opens load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash2 is in place, the CPLD closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash2 and starts by default; the CPU startup information is connected to the CPLD through the UART interface. The CPLD does not determine the firmware startup status at this time by capturing the bootcomplete flag in the UART interface. The CPLD does not capture the bootcomplete flag, and the BMC alarms that the Flash2 firmware startup failed.

6. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: Case 15: The startup process includes: After the platform is connected to the power supply, the standby power is started first, and the BMC and CPLD are powered on using the BMC standby power; one minute after the BMC is started, the user does not specify the startup firmware or specifies to start from the Flash1 firmware in the BMC management interface. At this time, the CPLD defaults to logically connecting the CPU_QSPI interface on the CPU side with the data interface of the QSPI1 of Flash1, and simultaneously opens load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash1 is in place, the CPLD closes load switch 2 and powers on the platform in sequence after an interval of 5 seconds; at this time, the CPU automatically reads the firmware in Flash1 and starts; the CPLD does not capture the UART interface If the bootcomplete flag is displayed, the firmware startup fails and the BMC issues an alarm indicating that the Flash1 firmware startup has failed. On the BMC interface, the user reselects the boot option from Flash2. The CPLD then logically connects the CPU_QSPI interface on the CPU side to the QSPI2 data interface on Flash2 by default, and simultaneously opens load switches 1 and 2 to power on Flash1 and Flash2. If the CPLD detects that Flash2 is in place, it closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. The CPU then automatically reads the firmware from Flash2 and starts. The CPLD detects the bootcomplete flag on the UART interface and determines that the firmware startup is successful.

7. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: Case 16 The startup process includes: After the platform is connected to the power supply, the standby power is started first, and the BMC and CPLD are powered on using the BMC standby power; one minute after the BMC is started, the user does not specify the startup firmware or specifies to start from the Flash1 firmware in the BMC management interface. At this time, the CPLD defaults to logically connecting the CPU_QSPI interface on the CPU side with the data interface of the QSPI1 of Flash1, and simultaneously opens load switch 1 and load switch 2 to power on Flash1 and Flash2; if the CPLD detects that Flash1 is in place, the CPLD closes load switch 1 and powers on the platform in sequence after an interval of 5 seconds. At this time, the CPU automatically reads the firmware in Flash1 and starts; the CPLD does not capture the bootcomplete flag in the UART interface. The BMC displays the flag indicating that the firmware startup has failed. The BMC then issues an alarm indicating that the Flash1 firmware startup has failed. The BMC selects the Flash2 firmware startup flag again. The CPLD then logically connects the CPU_QSPI interface on the CPU side to the QSPI2 data interface on Flash2 by default. Load switches 1 and 2 are simultaneously turned on to power on Flash1 and Flash2. If the CPLD detects that Flash2 is in place, it turns off load switch 1 and powers on the platform in sequence after a 5-second interval. The CPU then automatically reads the firmware from Flash2 and starts up. The CPLD does not capture the bootcomplete flag on the UART interface, indicating that the firmware startup has failed. The BMC then issues an alarm indicating that both Flash1 and Flash2 firmware startup have failed.

8. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: Situation 21 in which the BMC performs online firmware refresh includes: after both Flash1 and Flash2 firmware fail to start, the BMC selects to refresh the firmware in the management interface. If the Flash1 firmware is updated in the management interface, the CPLD logically disconnects the connection between the CPU-side CPU_QSPI interface and the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2, and logically connects the BMC-side UP_QSPI interface and the QSPI1 interface of Flash1, and the BMC updates the firmware of Flash1.

9. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: Situation 22 in which the BMC performs online firmware refresh includes: after both Flash1 and Flash2 firmware fail to start, the BMC selects to refresh the firmware in the management interface. If the Flash2 firmware is updated in the management interface, the CPLD logically disconnects the connection between the CPU-side CPU_QSPI interface and the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2, and logically connects the BMC-side UP_QSPI interface and the QSPI2 interface of Flash2, and the BMC updates the firmware of Flash2.

10. The dual-firmware intelligent startup system for a military reinforced computing platform according to claim 1, characterized in that: Situation 23 in which the BMC performs online firmware refresh includes: after both Flash1 and Flash2 firmware fail to start, the BMC selects to refresh the firmware in the management interface. If the management interface selects to update the Flash1 and Flash2 firmware, the CPLD logically disconnects the CPU_QSPI interface on the CPU side from the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2, and logically connects the UP_QSPI interface on the BMC side to the QSPI1 interface of Flash1 and the QSPI2 interface of Flash2. The BMC synchronously updates the firmware of Flash1 and Flash2, and the updated firmware is the same.

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