Monitoring circuit, statistical method and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to a monitoring circuit, a statistical method and a memory, which comprises: storage units, comparators and counters, each storage unit corresponding to a comparator and a counter; a storage judgment module receiving a current enabled word line address, comparing the word line address stored in the storage unit with the enabled word line address based on the comparators corresponding to the storage units in sequence, if there is a storage unit same as the enabled word line address, indicating that the count value of the counter corresponding to the storage unit is increased by one, if there is no storage unit same as the enabled word line address, storing the enabled word line address into the storage unit; a processing output module comparing the preset value with the count value of the counter, obtaining the word line addresses stored in the storage units corresponding to all the counters with the count value greater than the preset value, and outputting the word line addresses based on all the obtained word line addresses, so as to obtain the word line addresses with the enabled times greater than the preset value.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular, to a monitoring circuit, a counting method and a memory. BACKGROUND

[0002] A dynamic random access memory (DRAM) stores data through a structure of one transistor connecting one memory cell (1T1C), wherein the transistor is controlled by a word line (WL), and when the WL is turned on, the charge in the memory cell is shared with the charge of a bit line (BL) to read out the data in the target memory cell or write data into the target memory cell.

[0003] However, frequent or long-time turning on of the WL will cause the loss of charge in the adjacent memory cells, which may cause errors in the data stored in the memory cells.

[0004] How to count the number of times of turning on the WL to ensure the accuracy of the data stored in the memory cells is a counting problem to be solved at present. SUMMARY

[0005] Embodiments of the present disclosure provide a monitoring circuit to obtain word line addresses with a number of times of being turned on greater than a preset value.

[0006] Embodiments of the present disclosure provide a monitoring circuit, comprising: a plurality of memory cells, a plurality of comparators and a plurality of counters, wherein each memory cell is configured to store a word line address, and each memory cell corresponds to a comparator and a counter; a storage judging module configured to receive a currently turned-on word line address, and configured to: based on the comparators corresponding to the memory cells storing the word line addresses, compare the word line addresses stored in the memory cells with the turned-on word line address in sequence, if there is a memory cell with the same word line address as the turned-on word line address, then indicate that the count value of the counter corresponding to the memory cell is incremented by one, and if there is no memory cell with the same word line address as the turned-on word line address, then store the turned-on word line address in the memory cell without storing the word line address; and a processing output module configured to: based on a comparison between a preset value and the count value of the counter, obtain the word line addresses stored in the memory cells corresponding to all the counters with a count value greater than the preset value, and based on the obtained word line addresses, output the word line addresses.

[0007] The storage unit is connected with a comparator for comparing whether the current enabled word line address is stored in the storage unit, and storing the un-stored enabled word line address through the storage unit, and the storage unit is connected with a counter for counting the multiple enabled word line addresses, i.e. counting the number of the enabled word line addresses, comparing the counter value with a preset value to output the word line address whose enabled number is greater than the preset value, thereby realizing the monitoring of the enabled number of the word line, and through the obtained word line address, the subsequent optimization of the memory is avoided to prevent the loss of the charge in the adjacent storage units due to the frequent enabling of the word line.

[0008] In addition, based on the obtained all word line addresses, the word line address is outputted, including: based on the obtained all word line addresses, a word line address is randomly outputted.

[0009] In addition, each storage unit also has a flag bit; the flag bit includes a valid flag bit and an invalid flag bit, wherein the valid flag bit is used to represent that the storage unit has stored the word line address, and the invalid flag bit is used to represent that the storage unit has not stored the word line address; the valid flag bit is also used to turn on the comparator and the counter corresponding to the storage unit. Through the flag bit, the comparator connected with the storage unit is turned on, the process that the storage unit which has not stored the word line address compares with the current enabled word line address through the comparator is saved, and the monitoring process of the enabled number of the word line address is optimized.

[0010] In addition, the plurality of storage units are arranged in the form of a linked list.

[0011] In addition, the plurality of storage units are arranged in the form of a queue.

[0012] In addition, the storage judgment module includes: a receiving unit for receiving the enabled word line address; a control unit connected with the receiving unit, the plurality of storage units and the comparators corresponding to the storage units; if there is a storage unit same as the enabled word line address, the control unit instructs the counter corresponding to the storage unit to count plus one, and if there is no storage unit same as the enabled word line address, the control unit stores the enabled word line address into the storage unit which has not written the word line address.

[0013] In addition, if there is a storage unit same as the enabled word line address, the control unit instructs the counter corresponding to the storage unit to count plus one, including: if there is a storage unit same as the enabled word line address, the control unit generates a first control signal and a second control signal; the counter corresponding to the storage unit storing the enabled word line address counts plus one based on the first control signal; the second control signal is used to instruct to prevent the enabled word line address from being stored into the storage unit.

[0014] In addition, the processing output module comprises a processing unit connected to the plurality of storage units corresponding counters, configured to output a counter data with a value greater than the preset value according to the preset value; and an output unit connected to the processing unit and the plurality of storage units, configured to output the word line address stored in the corresponding storage unit according to the counter data.

[0015] In addition, the processing unit comprises an address counting circuit configured to poll the counters corresponding to the storage units storing the word line addresses based on a clock signal, and generate a first indication signal and a second indication signal based on the polling times and the comparison results of the polled counters and the preset value; a threshold unit configured to set a comparison threshold i, wherein the number of the storage units storing the word line addresses < i ≤ twice the number of the storage units storing the word line addresses, and i is an integer; a counting unit configured to count based on the clock signal and the first indication signal; and a control unit configured to provide the clock signal to the counting unit if the count value of the counting unit is less than the comparison threshold, mask the clock signal provided to the counting unit if the count value of the counting unit is equal to the comparison threshold, and output the counter data currently accessed by the address counting circuit when the count value of the counting unit is equal to the comparison threshold.

[0016] In addition, the address counting circuit is specifically configured to output the first indication signal if the counter is accessed for the first time by the address counting circuit, and output the first indication signal if the counter is repeatedly accessed by the address counting circuit, and output the second indication signal if the count value of the polled counter is less than the preset value based on the comparison results of the polled counter and the preset value.

[0017] In addition, the control unit comprises an AND gate having a first input end, a second input end and an output end; the first input end is configured to receive the clock signal, the second input end is connected to the threshold unit and the counting unit, and is configured to receive the comparison result of the count value of the counting unit and the comparison threshold; and the output end is connected to the counting unit.

[0018] In addition, the monitoring circuit further comprises a statistical sub-circuit configured to count the second indication signals; and the statistical sub-circuit is configured to generate a third indication signal if the number of the counted second indication signals is the same as the number of the storage units storing the word line addresses, and the third indication signal is used to indicate that the number of times that the word line addresses stored in the corresponding storage units of all the counters are turned on is less than the preset value. The third indication signal prompts the relevant staff that there is no word line address with the number of times turned on exceeding the preset value at present, so as to avoid the relevant staff from mistakenly thinking that the monitoring process is still in progress.

[0019] In addition, the control unit comprises an AND gate and an NOR gate; the AND gate has a first input end, a second input end and a first output end; the NOR gate has a third input end, a fourth input end and a second output end; the third input end is used for receiving a third indication signal, the fourth input end is connected with the threshold unit and the counting unit and is used for receiving a comparison result of the counting value of the counting unit and the comparison threshold; the second output end is connected with the second input end, the first input end is used for receiving a clock signal, and the first output end is connected with the counting unit. The clock signal is shielded by the third indication signal, so as to avoid resource waste caused by the continuous work of the monitoring circuit when there is no word line address which is opened more than the preset value.

[0020] In addition, the threshold unit comprises a random number generator, and the random number generator is used for generating the comparison threshold i.

[0021] In addition, the monitoring circuit further comprises a first switch module connected with the storage judgment module and configured to turn on the first switch module and make the storage judgment module work. The running of the monitoring circuit is controlled by the first switch module, so as to avoid resource consumption when there is no need for monitoring.

[0022] In addition, the monitoring circuit further comprises a second switch module connected with the processing output module and configured to turn on the second switch module and make the processing output module work. The output of the monitoring circuit is controlled by the second switch module, so as to avoid error output of the monitoring circuit when the opened counting of the word line address is not completed.

[0023] The embodiment of the present disclosure further provides a statistical method applied to the above monitoring circuit, comprising: acquiring a currently opened word line address; judging whether the opened word line address has been stored in the storage unit, if the opened word line address has been stored in the storage unit, counting the corresponding counter of the storage unit, if the opened word line address has not been stored in the storage unit, storing the word line address in the storage unit; acquiring a preset value, and comparing the values of the counters corresponding to the storage units of the stored word line addresses one by one based on the preset value, acquiring the word line address stored in the storage unit of the counter whose value is greater than the preset value; and outputting the word line address based on all the acquired word line addresses.

[0024] The embodiment of the present disclosure further provides a memory applied to the above monitoring circuit, and the word line corresponding to the word line address is protected based on the acquired word line address. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic diagram of the general circuit structure of the monitoring circuit provided by an embodiment of the present disclosure is shown;

[0026] Figure 2 A schematic diagram of the specific circuit structure of the monitoring circuit provided by an embodiment of the present disclosure is shown;

[0027] Figure 3 A structure diagram of a processing unit provided by an embodiment of the present disclosure is shown in FIG. 1.

[0028] Figure 4 A generation diagram of a first indication signal and a second indication signal provided by an embodiment of the present disclosure is shown in FIG. 3.

[0029] Figures 5 to 7 A structure diagram of a control unit provided by an embodiment of the present disclosure is shown in FIG. 5.

[0030] Figure 8 A flow diagram of a statistical method provided by another embodiment of the present disclosure is shown in FIG. 7. DETAILED DESCRIPTION

[0031] As known from the background, frequent or long-time opening of the WL will cause loss of electric charges in adjacent memory cells, which may result in errors of data stored in the memory cells.

[0032] An embodiment of the present disclosure provides a monitoring circuit to obtain a word line address with a number of openings greater than a preset value. Through the obtained word line address, the subsequent optimization of the memory can avoid loss of electric charges in adjacent memory cells due to frequent opening of the word line.

[0033] Those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed to enable the readers to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0034] Figure 1 A general circuit structure diagram of the monitoring circuit provided by the present embodiment is shown in FIG. 1, Figure 2 A specific circuit structure diagram of the monitoring circuit provided by the present embodiment is shown in FIG. 2, Figure 3 A structure diagram of a processing unit provided by the present embodiment is shown in FIG. 1, Figure 4 A generation diagram of a first indication signal and a second indication signal provided by the present embodiment is shown in FIG. 3, Figures 5 to 7 A structure diagram of a control unit provided by the present embodiment is shown in FIG. 5, and the monitoring circuit provided by the present embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0035] Reference Figure 1 The monitoring circuit comprises:

[0036] a plurality of memory cells 101, a plurality of comparators 102, and a plurality of counters 103, wherein each memory cell 101 is configured to store a word line address, and each memory cell 101 corresponds to a comparator 102 and a counter 103.

[0037] Figure 1The eight storage units 101, eight comparators 102, and eight counters 103 are taken as an example for illustration, and the number of storage units, comparators, and counters can be set according to the specific application scenario in other embodiments.

[0038] The storage unit n is connected to the comparator n and the counter n, n is a natural number greater than or equal to 1 and less than or equal to 8; the word line address 1 is stored in the storage unit 1, the word line address 2 is stored in the storage unit 2, the word line address 3 is stored in the storage unit 3, the word line address 4 is stored in the storage unit 4, and the storage units after the storage unit 5 do not store word line addresses, that is, empty storage units.

[0039] The storage judgment module 104 is configured to: based on the comparators 102 corresponding to the storage units 101 that have stored word line addresses, compare, in sequence, whether the word line addresses stored by the storage units are the same as the word line address that is currently enabled, if there is a storage unit 101 that is the same as the word line address that is currently enabled, then indicate that the count value of the counter 103 corresponding to the storage unit 101 that stores the same word line address is incremented by one, and if there is no storage unit 101 that is the same as the word line address that is currently enabled, then store the word line address that is currently enabled in the storage unit 101 that has not stored a word line address.

[0040] Corresponding to Figure 1 , it is assumed that the storage judgment module 104 receives the word line address that is currently enabled, the storage units 101 that have stored word line addresses are the storage unit 1 to the storage unit 4, the comparators 1 to 4 corresponding to the storage unit 1 to the storage unit 4 respectively compare with the storage judgment module 104, if the comparison values are the same, then it is proved that the word line address that is currently enabled has been stored in the storage unit 101, then the counter 103 connected to the comparator 102 is counted by one, and if the comparison values are all different, then it is proved that the word line address that is currently enabled has not been stored in the storage unit 101, then the word line address that is currently enabled is stored in a new storage unit.

[0041] The storage unit 101 is connected to the comparator 102, which is configured to compare whether the word line address that is currently enabled is stored in the storage unit 101, and to store the word line address that is currently enabled in the storage unit 101 that has not stored the word line address, and the storage unit 101 is connected to the counter 103, which is configured to count the word line address that is currently enabled, that is, to count the number of times the word line address that is currently enabled.

[0042] It should be noted that, in one example, the initial values of the counters 103 are all 1, that is, when the storage unit 101 stores data, the counter 103 represents that the word line address stored in the storage unit 101 is enabled once; in other embodiments, only the initial values of the counters need to be the same, and the specific initial value can be any value.

[0043] The processing output module 105 is configured to: based on a preset value and a value comparison of the counter 103, obtain a word line address stored in the storage unit 101 corresponding to all the counters 103 with a value greater than the preset value, and output the word line address based on the obtained all word line addresses.

[0044] By comparing the counter value with the preset value, the word line address with the most number of openings is output, thereby monitoring the number of openings of the word line. Through the obtained word line address, the subsequent optimization of the memory can avoid the loss of charges in the adjacent storage units due to the frequent opening of the word line.

[0045] It should be noted that in the embodiment, the counter 103 counts in an incremental manner. Subsequently, the word line address stored in the storage unit 101 corresponding to the counter 103 with a value greater than the preset value is output by comparison, that is, the word line address with a number of openings greater than the preset value. In other embodiments, the counter can also count in a decremental manner. Subsequently, the word line address stored in the storage unit corresponding to the counter with a value less than the preset value is output by comparison, that is, the word line address with a number of openings greater than the preset value.

[0046] In some embodiments, with reference to Figure 2 , the storage judgment module 104 includes a receiving unit 114 and a control unit 124. The receiving unit 114 is configured to receive the opened word line address. The control unit 124 is connected to the receiving unit 114, the plurality of storage units 101, and the comparators 102 corresponding to the storage units 101. If there is a storage unit 101 with the same word line address as the opened word line address, the control unit 124 instructs the counter 103 corresponding to the storage unit 101 to count plus one. If there is no storage unit 101 with the same word line address as the opened word line address, the control unit 124 stores the opened word line address in the storage unit 101 without writing the word line address.

[0047] Specifically, in one example, if there is a storage unit 101 with the same word line address as the opened word line address, the control unit 124 instructs the counter 103 corresponding to the storage unit 101 to count plus one. If there is no storage unit 101 with the same word line address as the opened word line address, the control unit 124 stores the opened word line address in the storage unit 101 without writing the word line address, including:

[0048] If there is a storage unit 101 with the same word line address as the opened word line address, the control unit 124 generates a first control signal and a second control signal. The counter 103 corresponding to the storage unit 101 storing the opened word line address counts plus one based on the first control signal. The second control signal is used to instruct to prevent the opened word line address from being stored in the storage unit 101.

[0049] If the comparator 102 corresponding to the storage unit 101 storing the enabled word line address does not generate the first control signal and the second control signal, it indicates that the currently enabled word line address is not stored in the storage unit 101 , and the currently enabled word line address is stored in the storage unit 101 .

[0050] In some embodiments, the plurality of storage units 101 are arranged in the form of a linked list. Figure 1 and Figure 2 If a linked list is used, if a new word line address needs to be stored, the word line address is directly stored in the storage unit 5.

[0051] In some embodiments, the plurality of storage units 101 are arranged in a queue. Figure 1 and Figure 2 If a queue formation setting is adopted, if a new word line address needs to be stored at this time, storage unit 4 moves the data down to storage unit 5, storage unit 3 moves the data down to storage unit 4, storage unit 2 moves the data down to storage unit 3, storage unit 1 moves the data down to storage unit 2, and the new word line address is stored in storage unit 1; it should be noted that in the process of data downshifting of storage unit 101, the comparator 102 and counter 103 corresponding to storage unit 101 will move together with the storage unit 101.

[0052] In some embodiments, each memory cell further has a flag bit, wherein the flag bit includes a valid flag bit and an invalid flag bit. The valid flag bit is used to indicate that the memory cell 101 has stored a word line address, and the invalid flag bit is used to indicate that the memory cell 101 is storing a word line address. The valid flag bit is also used to turn on the comparator 102 and counter 103 corresponding to the memory cell 101. By turning on the comparator 102 connected to the memory cell 101 via the flag bit, the process of comparing the memory cell 101 that does not store a word line address with the currently enabled word line address through the comparator 102 is eliminated, thereby optimizing the process of monitoring the number of times the word line address is turned on.

[0053] It should be noted that in specific applications, the flag bit can be one bit or multiple bits. This embodiment does not constitute a limitation on the number of bits of the flag bit. Solutions that conform to the flag bit setting method mentioned in this disclosure should all fall within the scope of protection of this disclosure.

[0054] In some embodiments, based on all word line addresses obtained, outputting a word line address includes: based on all word line addresses obtained, randomly outputting a word line address, specifically, referring to Figure 2 , processing output module 105 (reference Figure 1), comprising: a processing unit 115 and an output unit 125; the processing unit 115 is connected with the plurality of storage units 101 corresponding counter 103, and is configured to output a counter data with a value greater than a preset value according to the preset value; the output unit 125 is connected with the processing unit 115 and the plurality of storage units 101, and is configured to output the word line address stored in the corresponding storage unit 101 according to the counter data.

[0055] Specifically, referring to Figure 3 , the processing unit 115 (referring to Figure 2 ) comprises: an address counting circuit 201, a threshold unit 202, a counting unit 203 and a control unit 204.

[0056] The address counting circuit 201 is configured to poll the counter 103 corresponding to the storage unit 101 storing the word line address based on the clock signal clk, and generate the first indication signal and the second indication signal based on the polling times and the comparison structure of the polled counter 103 and the preset value; the threshold unit 202 is configured to set the comparison threshold i, wherein the number of storage units storing the word line address < i ≤ twice the number of storage units storing the word line address, and i is an integer; the counting unit 203 is configured to count based on the clock signal clk and the first indication signal; the control unit 204 is configured to provide the clock signal clk to the counting unit 203 if the count value of the counting unit 203 is less than the comparison threshold i, and mask the clock signal provided to the counting unit 203 if the count value of the counting unit 203 is equal to the comparison threshold i; and when the count value of the counting unit 203 is equal to the comparison threshold, output the counter data currently accessed by the address counting circuit 201.

[0057] Specifically, the counting unit 203 is configured to, when receiving the clock signal clk, the next count value of the counting unit 203 = the current count value of the counting unit 203 + flag.

[0058] Specifically, the address counting circuit 201 is specifically configured to, if the counter 103 is accessed for the first time by the address counting circuit, output the first indication signal; if the counter 103 is repeatedly accessed by the address counting circuit, based on the comparison structure of the polled counter 103 and the preset value, if the polled counter value is greater than or equal to the preset value, the first indication signal is generated, and if the polled counter 103 value is less than the preset value, the second indication signal is generated.

[0059] Referring to Figure 4The embodiment takes preset value = 2 as an example, wherein the first indication signal is flag = 1, and the second indication signal is flag = 0. For the eight addresses "000" to "111", the number of times of being enabled is respectively 1, 3, 2, 1, 1, 5, 6 and 3. When the addresses "000" to "111" are accessed for the first time, the first indication signal is generated. When the addresses "000" to "111" are accessed for the second time, the addresses "000", "011" and "100" are enabled for less than 2 times, the second indication signal is generated, and the addresses "001", "010", "101", "110" and "111" are enabled for more than or equal to 2 times, the first indication signal is generated.

[0060] With continued reference to Figure 4 Since the number of storage units in which the word line address has been stored is < i ≤ twice the number of storage units in which the word line address has been stored, Figure 4 The number of storage units in which the word line address has been stored is 8, and 8 < i ≤ 16 at this time;

[0061] Assuming i = 9, when the count unit 203 counts the value of 9, the counter data is outputted, when the count unit 203 counts the value of 9, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that when the count unit 203 counts the value of 9, the current polling address of the address counting circuit 201 is "001"; assuming i = 10, when the count unit 203 counts the value of 10, the counter data is outputted, when the count unit 203 counts the value of 10, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "010"; assuming i = 11, when the count unit 203 counts the value of 11, the counter data is outputted, when the count unit 203 counts the value of 11, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "101"; assuming i = 12, when the count unit 203 counts the value of 12, the counter data is outputted, when the count unit 203 counts the value of 12, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "110"; assuming i = 13, when the count unit 203 counts the value of 13, the counter data is outputted, when the count unit 203 counts the value of 13, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "111"; assuming i = 14, when the count unit 203 counts the value of 14, the counter data is outputted, when the count unit 203 counts the value of 14, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "001"; assuming i = 15, when the count unit 203 counts the value of 15, the counter data is outputted, when the count unit 203 counts the value of 15, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "010"; assuming i = 16, when the count unit 203 counts the value of 16, the counter data is outputted, when the count unit 203 counts the value of 16, the flags corresponding to the addresses "000"~"111" are added in turn, and it can be obtained that the current polling address of the address counting circuit 201 is "101".

[0062] In some embodiments, the threshold unit comprises a random number generator, and the random number generator is configured to generate the comparison threshold i.

[0063] In one example, the control unit 204 comprises an AND gate, and the AND gate has a first input end, a second input end and an output end.

[0064] The first output end is used for receiving the clock signal clk, the second input end is connected with the threshold unit 202 and the counting unit 203, and is used for receiving the comparison result of the counting value of the counting unit 203 and the comparison threshold value. The output end is connected with the counting unit 203.

[0065] At this time, when the counting value of the counting unit 203 is less than the comparison threshold value, the generated comparison result is 1, which is used for indicating that the AND gate transmits the clock signal clk to the counting unit 203, and the counting unit 203 continues to count. When the counting value of the counting unit 203 is equal to the comparison threshold value, the generated comparison result is 0, and the AND gate cannot transmit the clock signal clk to the counting unit 203, and the counting unit 203 stops counting.

[0066] In one example, referring to Figure 5 , the control unit 204 includes an AND gate and a NOR gate. The AND gate has a first input end, a second input end and an output end. The NOR gate has a first input end, a second input end and an output end.

[0067] The first input end of the AND gate is used for receiving the clock signal clk, and the output end is connected with the counting unit 203 (referring to Figure 3 ). The first input end of the NOR gate is connected with the threshold unit 202 (referring to Figure 3 ) and the counting unit 203, and is used for receiving the comparison result of the counting value of the counting unit 203 and the comparison threshold value. The second input end is used for receiving the flag states, and the output end is connected with the second input end of the AND gate.

[0068] Due to the circuit logic of the NOR gate, that is, when the input is at a high level, the output is at a low level, that is, the AND gate cannot transmit the clock signal clk to the counting unit 203, and the counting unit 203 stops counting. When the input is at a full low level, the output is at a high level, and the AND gate transmits the clock signal clk to the counting unit 203, and the counting unit 203 continues to count. At this time, when the flag is 1, the flag states are not generated, that is, the second input end of the NOR gate is input at a low level. When the flag is 0, the flag states are generated, that is, the second input end of the NOR gate is input at a high level. When the counting value of the counting unit 203 is less than the comparison threshold value, the generated comparison result is 0. When the counting value of the counting unit 203 is equal to the comparison threshold value, the generated comparison result is 1. That is, under this control logic, when the flag is 0 or when the counting value of the counting unit 203 is equal to the comparison threshold value, the counting unit 203 stops counting.

[0069] In one example, the monitoring circuit further comprises a counting sub-circuit configured to count the second indication signals, and the counting sub-circuit is configured to generate a third indication signal if the number of counted second indication signals is the same as the number of storage units of the stored word line addresses, and the third indication signal is used to indicate that the number of times that all the storage units corresponding to the counters are opened is less than a preset value. The third indication signal prompts the relevant staff that there is no word line address whose opening number exceeds the preset value at present, so as to avoid the relevant staff from mistakenly thinking that the monitoring process is still in progress.

[0070] Further, with reference to Figure 6 , the control unit 204 comprises an AND gate and a NOR gate; the AND gate has a first input end, a second input end and a first output end; the NOR gate has a third input end, a fourth input end and a second output end; the third input end is used to receive the third indication signal, the fourth input end is connected to the threshold unit and the counting unit and is used to receive the comparison result of the counting value of the counting unit and the comparison threshold; the second output end is connected to the second input end, the first input end is used to receive the clock signal, and the first output end is connected to the counting unit.

[0071] At this time, when the third indication signal is 1, the second input end of the NOR gate inputs a high level, when the third indication signal is 0, the second input end of the NOR gate inputs a low level, when the counting value of the counting unit 203 is less than the comparison threshold, the generated comparison result is 0, and when the counting value of the counting unit 203 is equal to the comparison threshold, the generated comparison result is 1, that is, under this control logic, when the third indication signal exists or when the counting value of the counting unit 203 is equal to the comparison threshold, the counting unit 203 stops counting.

[0072] The third indication signal masks the clock signal, so as to avoid resource waste caused by the fact that the monitoring circuit continues to work when there is no word line address whose opening number exceeds the preset value at present.

[0073] In some embodiments, the circuit shown in Figure 5 and the circuit shown in Figure 6 may be combined to obtain the circuit shown in Figure 7 At this time, when the third indication signal exists, when the flag is 0 or when the counting value of the counting unit 203 is equal to the comparison threshold, the counting unit 203 stops counting.

[0074] In some embodiments, the monitoring circuit further comprises a first switch module (not shown) connected to the storage judgment module 104 (with reference to Figure 1 and configured to turn on the first switch module (not shown) to make the storage judgment module 104 work. The first switch module controls the operation of the monitoring circuit, so as to avoid resource consumption when no monitoring is needed.

[0075] In some embodiments, the monitoring circuit further comprises a second switch module (not shown) connected to the processing output module 105 (refer to Figure 2 ), configured to turn on the second switch module (not shown) to make the processing output module 105 work. By controlling the output of the monitoring circuit through the second switch module, the error output of the monitoring circuit when the uncompleted word line address is counted is avoided.

[0076] The storage unit 101 is connected to the comparator 102 for comparing whether the current opened word line address is stored in the storage unit 101, and storing the unopened word line address in the storage unit 101, and the storage unit 101 is connected to the counter 103 for counting the number of times of opening the word line address, that is, counting the number of times of opening the word line address; by comparing the counter value with the preset value, the word line address whose opening times are greater than the preset value is outputted, so as to realize the monitoring of the opening times of the word line, and by obtaining the word line address, the subsequent optimization of the memory is avoided to avoid the loss of the charge in the adjacent storage unit due to the frequent opening of the word line.

[0077] The units involved in the embodiment are logical units. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the disclosure, units not closely related to solving the technical problems proposed in the disclosure are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0078] It should be noted that the features disclosed in the monitoring circuit provided by the above embodiments can be combined arbitrarily without conflict, and a new circuit embodiment can be obtained.

[0079] Another embodiment of the disclosure provides a statistical method applied to the monitoring circuit provided by the above embodiments to realize the monitoring of the opening times of the word line and output the word line address whose opening times are greater than the preset value.

[0080] Figure 8 The flowchart of the statistical method provided by the embodiment is shown in the following detailed description of the statistical method provided by the embodiment in combination with the drawings, and the specific steps are as follows:

[0081] Referring to Figure 6 , the statistical method comprises:

[0082] Step 401: obtaining the current opened word line address.

[0083] Step 402: processing the obtained word line address.

[0084] Specifically, it is judged whether the opened word line address has been stored in the storage unit, if the opened word line address has been stored in the storage unit, the counter corresponding to the storage unit is counted, if the opened word line address has not been stored in the storage unit, the word line ground is stored in the storage unit.

[0085] Corresponding to Figure 1 , assuming that the storage judgment module 104 receives the opened word line address, the storage unit 101 storing the word line address, i.e. the storage unit 1 to the storage unit 4, the comparators 1 to 4 corresponding to the storage unit 1 to the storage unit 4 respectively compare with the storage judgment module 104, if the comparison values are the same, it is proved that the opened word line address has been stored in the storage unit 101, then the counter 103 connected corresponding to the comparator 102 counts plus one; if the comparison values are all different, it is proved that the opened word line address has not been stored in the storage unit 101, then the opened word line address is stored in the new storage unit.

[0086] The storage unit 101 is connected with the comparator 102, which is used to compare whether the currently opened word line address is stored in the storage unit 101, and store the opened word line address not stored in the storage unit 101, and the storage unit 101 is connected with the counter 103, which is used to count the opened word line address multiple times, i.e. count the number of times of the opened word line address.

[0087] Step 403, comparing and obtaining the word line address opened more than a preset value.

[0088] Specifically, the preset value is obtained, and the values of the counters corresponding to the storage units of the stored word line addresses are compared one by one based on the preset value, the word line address stored in the storage unit with the value of the counter greater than the preset value is obtained, and the word line address is output based on all the obtained word line addresses.

[0089] It should be noted that, in some embodiments, based on all the obtained word line addresses, a word line address is randomly output.

[0090] By comparing the counter value with the preset value, the word line address opened more than the preset value is output, so as to realize the monitoring of the number of times of opening the word line, and through the obtained word line address, the subsequent optimization of the memory is avoided, so as to avoid the loss of charge in the adjacent storage units due to the frequent opening of the word line.

[0091] It should be noted that the description of the above statistical method is similar to the description of the above monitoring circuit embodiment, and has similar beneficial effects as the monitoring circuit embodiment, so it is not repeated. For technical details not disclosed in the statistical method of the embodiment of the present disclosure, please refer to the description of the monitoring circuit in the embodiment of the present disclosure.

[0092] The stage division of the above statistical methods is only for clear description, and can be combined into one statistical stage or split into multiple statistical stages in actual implementation, as long as the logic of the statistical methods is the same, which is within the protection scope of the patent; in addition, adding insignificant modifications or introducing insignificant designs to the above statistical methods, but not changing the core design of the above statistical methods, are within the protection scope of the patent.

[0093] A further embodiment of the present disclosure provides a memory applied to the monitoring circuit provided by the above embodiments, and the memory is used to protect the word line corresponding to the obtained word line address. By optimizing the memory through the obtained word line address, the loss of charges in adjacent storage units caused by frequent opening of the word line is avoided.

[0094] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, and the memory of the dynamic random access memory (DRAM) chip conforms to a DDR2 memory specification.

[0095] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, and the memory of the dynamic random access memory (DRAM) chip conforms to a DDR3 memory specification.

[0096] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, and the memory of the dynamic random access memory (DRAM) chip conforms to a DDR4 memory specification.

[0097] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, and the memory of the dynamic random access memory (DRAM) chip conforms to a DDR5 memory specification.

[0098] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A monitoring circuit, characterized in that: include: A plurality of storage units, a plurality of comparators, and a plurality of counters, wherein each of the storage units is used to store a word line address, and each of the storage units corresponds to one of the comparators and one of the counters; a storage determination module, configured to receive a currently enabled word line address and to: based on the comparator corresponding to the storage unit that has stored the word line address, sequentially compare whether the word line address stored in the storage unit is the same as the enabled word line address; if there is a storage unit that is the same as the enabled word line address, instruct the count value of the counter corresponding to the storage unit to increase by one; if there is no storage unit that is the same as the enabled word line address, then store the enabled word line address in a storage unit that has not written a word line address; A processing and output module is configured to: obtain, based on a comparison between a preset value and a value of the counter, word line addresses stored in the storage units corresponding to all the counters whose values ​​are greater than the preset value, and output the word line addresses based on all the obtained word line addresses; the processing and output module includes a processing unit, and the processing unit includes: The address counting circuit is configured to poll a counter corresponding to a storage unit having stored a word line address based on a clock signal, and generate a first indication signal and a second indication signal based on a number of polling times and a comparison result between the polled counter and the preset value; a threshold unit, configured to set a comparison threshold i, wherein the number of storage cells storing word line addresses < i ≤ twice the number of storage cells storing word line addresses, and i is an integer; a counting unit, configured to count based on a clock signal and the first indication signal; a control unit configured to, if the count value of the counting unit is less than the comparison threshold, provide the clock signal to the counting unit; and if the count value of the counting unit is equal to the comparison threshold, shield the clock signal provided to the counting unit; When the count value of the counting unit is equal to the comparison threshold, the counter data currently accessed by the address counting circuit is output.

2. The monitoring circuit according to claim 1, wherein: Outputting the word line address based on all the acquired word line addresses includes: randomly outputting a word line address based on all the acquired word line addresses.

3. The monitoring circuit according to claim 1, wherein: Each of the storage units also has a flag bit; The flag bit includes a valid flag bit and an invalid flag bit, wherein the valid flag bit is used to indicate that the memory cell has stored a word line address, and the invalid flag bit is used to indicate that the memory cell has not stored a word line address; The valid flag is further used to turn on the comparator and the counter corresponding to the storage unit.

4. The monitoring circuit according to claim 1, wherein: The plurality of storage units are arranged in the form of a linked list.

5. The monitoring circuit according to claim 1, wherein: The plurality of storage units are arranged in the form of a queue.

6. The monitoring circuit according to claim 1, wherein: The storage judgment module includes: A receiving unit, configured to receive the enabled word line address; a control unit connected to the receiving unit, the plurality of storage units, and the comparators corresponding to the storage units; If there is a storage cell with the same address as the word line that is turned on, the control unit instructs the counter corresponding to the storage cell to count up by one; if there is no storage cell with the same address as the word line that is turned on, the control unit stores the turned on word line address in a storage cell that has not written the word line address.

7. The monitoring circuit according to claim 6, wherein: If there is a storage unit with the same address as the turned-on word line, the control unit instructs the counter corresponding to the storage unit to count up by one, including: If there is a memory cell with the same address as the turned-on word line, the control unit generates a first control signal and a second control signal; The counter corresponding to the storage unit storing the turned-on word line address is incremented by one based on the first control signal; The second control signal is used to instruct to prevent the enabled word line address from being stored in the memory unit.

8. The monitoring circuit according to claim 2, wherein: The processing output module includes: a processing unit connected to the counters corresponding to the plurality of storage units, and configured to randomly output counter data having a value greater than the preset value according to the preset value; An output unit is connected to the processing unit and the plurality of storage units, and is used to output the word line address stored in the corresponding storage unit according to the counter data.

9. The monitoring circuit according to claim 1, wherein: The address counting circuit is specifically configured as follows: If the counter is accessed for the first time by the address counting circuit, outputting a first indication signal; If the counter is repeatedly accessed by the address counting circuit, based on the comparison result of the polled counter and the preset value, if the polled counter value is greater than or equal to the preset value, a first indication signal is generated; if the polled counter value is less than the preset value, a second indication signal is generated.

10. The monitoring circuit according to claim 1, wherein: The control unit includes an AND gate having a first input terminal, a second input terminal and an output terminal; The first input terminal is used to receive the clock signal, and the second input terminal is connected to the threshold unit and the counting unit, and is used to receive a comparison result between the count value of the counting unit and the comparison threshold; The output end is connected to the counting unit.

11. The monitoring circuit according to claim 1, wherein: Also includes: a counting sub-circuit, configured to count the second indication signal; The statistical sub-circuit is configured to generate a third indication signal if the number of the second indication signals counted is the same as the number of the storage units that have stored the word line addresses. The third indication signal is used to indicate that the number of times the word line addresses stored in the storage units corresponding to all the counters are turned on is less than the preset value.

12. The monitoring circuit according to claim 11, wherein: The control unit includes an AND gate and a NOR gate; The AND gate has a first input terminal, a second input terminal and a first output terminal; The NOR gate has a third input terminal, a fourth input terminal and a second output terminal; The third input terminal is used to receive the third indication signal, and the fourth input terminal is connected to the threshold unit and the counting unit, and is used to receive a comparison result between the count value of the counting unit and the comparison threshold; The second output end is connected to the second input end, the first input end is used to receive the clock signal, and the first output end is connected to the counting unit.

13. The monitoring circuit according to claim 1, wherein: The threshold unit includes a random number generator, which is used to generate the comparison threshold i.

14. The monitoring circuit according to claim 1, wherein: Also includes: The first switch module is connected to the storage determination module and is configured such that when the first switch module is turned on, the storage determination module works.

15. The monitoring circuit according to claim 1 or 14, characterized in that: Also includes: The second switch module is connected to the processing output module and is configured so that when the second switch module is turned on, the processing output module works.

16. A statistical method, applied to the monitoring circuit according to any one of claims 1 to 15, characterized in that: include: Get the address of the word line currently turned on; determining whether the enabled word line address has been stored in a storage unit, and if so, counting a counter corresponding to the storage unit; and if not, storing the word line address in the storage unit; Obtaining a preset value, and comparing the values ​​of the counters corresponding to the storage units storing the word line addresses one by one based on the preset value, and obtaining the word line addresses stored in the storage units whose counter values ​​are greater than the preset value; Based on all the acquired word line addresses, the word line address is output.

17. A memory, applied to the monitoring circuit according to any one of claims 1 to 15, characterized in that: Based on the acquired word line address, a word line corresponding to the word line address is protected.

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