System and method for estimating non-parametric optimal read threshold

Abstract

The present disclosure relates to a non-parametric optimal read threshold estimation scheme for a memory system. The memory system includes a memory device having pages and a controller having a neural network. The controller performs read operations on selected pages using a read threshold set; obtains a read threshold set, a checksum value, and an asymmetric ratio of 1 counts to 0 counts associated with decoding of the selected page based on each read operation; provides the obtained read threshold set, checksum value, and asymmetric ratio as input information to the neural network; and estimates an optimal read threshold voltage by the neural network based on the input information and weights, wherein the weights include a combination of multiple matrices and a bias vector.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a scheme for determining an optimal read threshold voltage in a memory system. Background Art

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices, such as mobile phones, digital cameras, and notebook computers, has rapidly increased. These portable electronic devices typically utilize a memory system having a memory device (i.e., a data storage device). The data storage device serves as a primary memory device or a secondary memory device for the portable electronic device.

[0003] Because memory devices have no moving parts, memory systems using memory devices offer excellent stability, durability, high information access speed, and low power consumption. Examples of memory systems with such advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Storage (UFS), and solid-state drives (SSDs). The memory system can determine the optimal read threshold voltage among the read threshold voltages according to various schemes. Summary of the Invention

[0004] Aspects of the present invention include a system and method for estimating a non-parametric optimal read threshold using a deep neural network.

[0005] In one aspect of the present invention, a memory system includes a memory device having a plurality of pages and a controller having a neural network. The controller is configured to: perform one or more read operations on a page selected from the plurality of pages using a read threshold set including a plurality of read threshold voltages; obtain a read threshold set, a checksum value, and an asymmetric ratio of 1 counts to 0 counts associated with decoding of the selected page based on each of the one or more read operations; provide the obtained read threshold set, checksum value, and asymmetric ratio as input information to the neural network; and estimate, by the neural network, an optimal read threshold voltage based on the input information and weights of the input information, the weights comprising a combination of a plurality of matrices and a bias vector.

[0006] In another aspect of the present invention, a method of operating a memory system includes a memory device having multiple pages and a controller having a neural network, the method including: performing one or more read operations on a page selected from the multiple pages using a read threshold set including multiple read threshold voltages; obtaining a read threshold set, a checksum value, and an asymmetric ratio of counts of 1s to counts of 0s associated with decoding of the selected page based on each of the one or more read operations; providing the obtained read threshold set, checksum value, and asymmetric ratio as input information to the neural network; and estimating, by the neural network, an optimal read threshold voltage based on the input information and weights of the input information, the weights including a combination of multiple matrices and bias vectors.

[0007] Additional aspects of the invention will become apparent from the description below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a data processing system.

[0009] Figure 2 is a block diagram illustrating a memory system.

[0010] Figure 3 is a circuit diagram showing a memory block of a memory device.

[0011] Figure 4 is a diagram illustrating the state distribution of different types of cells of a memory device.

[0012] Figure 5A is a diagram illustrating an example of encoding of a multi-layer cell (MLC).

[0013] Figure 5B is a diagram showing status distribution of pages of a multi-level cell (MLC).

[0014] Figure 6A is a diagram showing an example of Gray coding of a triple-layer cell (TLC).

[0015] Figure 6B is a diagram showing status distribution of pages of a triple-level cell (TLC).

[0016] Figure 7 is a diagram illustrating the flow of an error recovery algorithm in a memory system.

[0017] Figure 8 is a diagram illustrating distribution of cell levels of a specific page of a triple-level cell (TLC) flash memory device.

[0018] Figure 9is a diagram illustrating a memory system according to an embodiment of the present invention.

[0019] Figure 10 is a diagram illustrating a neural network according to one embodiment of the present invention.

[0020] Figure 11 is a diagram illustrating an optimal read threshold estimator according to one embodiment of the present invention.

[0021] Figure 12 is a diagram illustrating a training operation of an optimal read threshold estimator according to one embodiment of the present invention.

[0022] Figure 13 is a flow chart illustrating an optimal read threshold estimation operation according to one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should therefore not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure conveys the scope of the present invention to those skilled in the art. In addition, references to "an embodiment," "another embodiment," etc. herein are not necessarily intended to refer only to one embodiment, and different references to any such phrases are not necessarily intended to refer to the same embodiment. The term "embodiment" as used herein does not necessarily refer to all embodiments. Throughout the disclosure, the same reference numerals refer to the same components in the drawings and embodiments of the present invention.

[0024] The present invention can be implemented in many ways, including: a process; an apparatus; a system; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to run instructions stored on and / or provided by a memory coupled to the processor. In this specification, these embodiments or any other form that the present invention may take may be referred to as techniques. In general, the order of operations of the disclosed processes may be changed within the scope of the present invention. Unless otherwise stated, a component such as a processor or memory described as being adapted to perform a task may be implemented as a general device or circuit component configured or otherwise programmed to perform that task at a given time or as a specific device or circuit component manufactured or preconfigured or preprogrammed to perform that task. As used herein, the term "processor" or the like refers to one or more devices, circuits, and / or processing cores adapted to process data such as computer program instructions.

[0025] Method described herein, process and / or operation can be performed by the code or instruction to be run by a computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein, processor, controller or other signal processing device or those computers, processor, controller or other signal processing device except the element described herein.Because the algorithm (or the operation of computer, processor, controller or other signal processing device) forming the basis of the method is described herein, the code or instruction for implementing the operation of method embodiment can be changed into a computer, processor, controller or other signal processing device for performing a special-purpose processor of any method herein.

[0026] If implemented at least in part in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers and other signal generation and signal processing functional components may include, for example, a memory or other storage device for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller or other signal processing device.

[0027] Detailed descriptions of various embodiments of the present invention and accompanying drawings illustrating aspects of the present invention are provided below. The present invention is described in conjunction with these embodiments, but the invention is not limited to any particular embodiment. The present invention encompasses numerous alternatives, modifications, and equivalents. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. These details are provided for illustrative purposes; the present invention may be practiced without some or all of these specific details. For the sake of clarity, technical material known in the art related to the present invention has not been described in detail to avoid unnecessarily obscuring the present invention.

[0028] Figure 1 is a block diagram illustrating a data processing system 2 according to one embodiment of the present invention.

[0029] Reference Figure 1 , the data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive a request from the host device 5 and operate in response to the received request. For example, the memory system 10 may store data to be accessed by the host device 5.

[0030] The host device 5 can be implemented using any of various types of electronic devices. In various embodiments, the host device 5 can be an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 can be a portable electronic device such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0031] The memory system 10 may be implemented using any of various types of storage devices such as a solid-state drive (SSD) and a memory card. In various embodiments, the memory system 10 may be configured as one of various components in an electronic device such as a computer, an ultra-mobile personal computer (PC) (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3D television, a smart TV, a digital audio recorder, a digital audio player, a digital photo recorder, a digital photo player, a digital video recorder, a digital video player, a storage device in a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, one of various electronic devices in a home network, one of various electronic devices in a computer network, one of electronic devices in a telematics network, or one of various components in a computing system.

[0032] The memory system 10 may include a controller 100 and a memory device 200. The controller 100 may control the overall operation of the memory device 200.

[0033] The memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the controller 100. The memory device 200 can receive commands CMD, addresses ADDR, and data DATA through input / output lines. The memory device 200 can receive power PWR through power lines and control signals CTRL through control lines. Depending on the design and configuration of the memory system 10, the control signals CTRL may include, for example, a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0034] The controller 100 and the memory device 200 may be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein. In one embodiment of the present invention, when the memory system 10 is used in an SSD, a host device (e.g., Figure 1 The operating speed of the host device 5) can be significantly improved.

[0035] The controller 100 and the memory device 200 may be integrated into a single semiconductor device such as a memory card. For example, the controller 100 and the memory device 200 may be integrated to configure a Personal Computer Memory Card International Association (PCMCIA) personal computer (PC) card, a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a reduced size multimedia card (RS-MMC), a micro-sized version of MMC (micro-MMC), a secure digital (SD) card, a mini secure digital (mini SD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC), and / or a universal flash memory (UFS).

[0036] Figure 2 is a block diagram illustrating a memory system according to one embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 is shown.

[0037] Reference Figure 2 , the memory system 10 may include a controller 100 and a memory device 200. The memory system 10 may respond to a request from a host device (e.g., Figure 1 The server operates based on a request of a host device 5 and, in particular, stores data to be accessed by the host device.

[0038] The memory device 200 may store data to be accessed by a host device.

[0039] The memory device 200 may be implemented using a volatile memory device such as a dynamic random access memory (DRAM) and / or a static random access memory (SRAM), or a non-volatile memory device such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric random access memory (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), and / or a resistive RAM (RRAM).

[0040] The controller 100 may control the storage of data in the memory device 200. For example, the controller 100 may control the memory device 200 in response to a request from a host device. The controller 100 may provide data read from the memory device 200 to the host device, and may store data provided from the host device in the memory device 200.

[0041] The controller 100 may include a storage device 110, a control component 120, an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 connected via a bus 160, and the control component 120 may be implemented as a processor such as a central processing unit (CPU).

[0042] The memory device 110 may be used as a working memory of the memory system 10 and the controller 100, and the memory device 110 may store data for driving the memory system 10 and the controller 100. For example, when the controller 100 controls the operation of the memory device 200, the memory device 110 may store data used by the controller 100 and the memory device 200 for operations such as a read operation, a write operation, a program operation, and an erase operation.

[0043] The storage device 110 may be implemented using a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage device 110 may store data used by the host device in the memory device 200 for read and write operations. To store data, the storage device 110 may include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, and the like.

[0044] The control component 120 can control the general operation of the memory system 10 and control the write operation or read operation of the memory device 200 in response to a write request or read request from a host device. The control component 120 can drive firmware or other program instructions, which can be referred to as a flash translation layer (FTL), to control the operation of the memory system 10. For example, the FTL can perform operations such as logical to physical (L2P) mapping, wear leveling, garbage collection, and / or bad block processing. L2P mapping is called logical block addressing (LBA).

[0045] During a read operation, the ECC component 130 may detect and correct errors in data read from the memory device 200. In one embodiment, when the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but may output an error correction failure signal indicating a failure to correct the error bits.

[0046] In various embodiments, the ECC component 130 can perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chadhouli-Houchungum (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), or block coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, the ECC component 130 can include any and all circuits, systems, or devices suitable for error correction operations.

[0047] The host interface 140 may communicate with a host device through one or more of various communication standards or interfaces, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0048] The memory interface 150 may provide an interface between the controller 100 and the memory device 200 to allow the controller 100 to control the memory device 200 in response to a request from a host device. The memory interface 150 may generate control signals for the memory device 200 and process data under the control of the control component 120. In one embodiment, when the memory device 200 is a flash memory such as a NAND flash memory, the memory interface 150 may generate control signals for the memory and process data under the control of the control component 120.

[0049] For example, Figure 2 The memory device 200 shown in FIG may include a memory cell array 210, a control circuit 220, a voltage generating circuit 230, a row decoder 240, a page buffer 250 that may be in the form of a page buffer array, a column decoder 260, and an input and output (input / output) circuit 270. The memory cell array 210 may include a plurality of memory blocks 211 that may store data. The voltage generating circuit 230, the row decoder 240, the page buffer 250, the column decoder 260, and the input / output circuit 270 may form a peripheral circuit of the memory cell array 210. The peripheral circuit may perform a program operation, a read operation, or an erase operation on the memory cell array 210. The control circuit 220 may control the peripheral circuit.

[0050] The voltage generating circuit 230 may generate various levels of operating voltages. For example, in an erase operation, the voltage generating circuit 230 may generate various levels of operating voltages such as an erase voltage and a pass voltage.

[0051] The row decoder 240 may electrically communicate with the voltage generating circuit 230 and the plurality of memory blocks 211. The row decoder 240 may select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit an operating voltage supplied from the voltage generating circuit 230 to the selected memory block.

[0052] The page buffer 250 can be connected to the memory cell array 210 through the bit line BL ( Figure 3 ). The page buffer 250 may precharge the bit line BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transmit and receive data to and from a selected memory block in a program operation and a read operation, or temporarily store the transmitted data.

[0053] The column decoder 260 may transmit and receive data to and from the page buffer 250 , and may also transmit and receive data from the input / output circuit 270 .

[0054] The input / output circuit 270 can transmit data from an external device (e.g., Figure 1 The controller 100 transmits a command and an address received from the controller 100 to the control circuit 220, transmits data from an external device to the column decoder 260, or outputs data from the column decoder 260 to an external device.

[0055] The control circuit 220 may control the peripheral circuits in response to commands and addresses.

[0056] Figure 3 1 is a circuit diagram showing a memory block of a memory device according to an embodiment of the present invention. Figure 3 The storage block can be Figure 2 Any one of the memory blocks 211 of the memory cell array 210 shown.

[0057] Reference Figure 3 , the memory block 211 may include a plurality of word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL coupled to the row decoder 240. These lines may be arranged in parallel with the plurality of word lines between DSL and SSL.

[0058] The memory block 211 may further include a plurality of cell strings 221 respectively connected to the bit lines BL0 to BLm-1. The cell string of each column may include one or more drain select transistors DST and one or more source select transistors SST. In the embodiment shown, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the memory cells may be formed as a multi-layer cell. For example, each of the memory cells may be formed as a single-layer cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-layer cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a triple-layer cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a quad-layer cell (QLC) storing 4 bits of data.

[0059] The source of the SST in each cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of the SST in the cell string can be connected to the SSL, and the gate of the DST in the cell string can be connected to the DSL. The gates of the memory cells across the cell strings can be connected to the corresponding word lines. That is, the gate of the memory cell MC0 is connected to the corresponding word line WL0, the gate of the memory cell MC1 is connected to the corresponding word line WL1, and so on. The group of memory cells connected to a particular word line can be referred to as a physical page. Therefore, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0060] The page buffer 250 may include a plurality of page buffers 251 coupled to the bit lines BL0 to BLm-1. The page buffers 251 may operate in response to page buffer control signals. For example, during a read operation or a verify operation, the page buffers 251 may temporarily store data received through the bit lines BL0 to BLm-1 or sense a voltage or current of the bit lines.

[0061] In various embodiments of the present invention, the memory block 211 may include NAND-type flash memory cells. However, the memory block 211 is not limited to this cell type and may include NOR-type flash memory cells. The memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory in which a controller is embedded within a memory chip.

[0062] Figure 4 is a diagram illustrating state distribution or programming voltage (PV) level distribution of different types of cells of a memory device.

[0063] Reference Figure 4 Each of the memory cells may be implemented using a specific type of cell, for example, a single-level cell (SLC) storing 1 bit of data, a multi-level cell (MLC) storing 2 bits of data, a triple-level cell (TLC) storing 3 bits of data, or a quad-level cell (QLC) storing 4 bits of data. Typically, all memory cells in a particular memory device are of the same type, but this is not required.

[0064] SLCs can include two states, P0 and P1. P0 can represent an erased state, and P1 can represent a programmed state. Because SLCs can be set to one of two different states, each SLC can program or store one bit according to a set encoding method. MLCs can include four states, P0, P1, P2, and P3. Among these states, P0 can represent an erased state, and P1 to P3 can represent programmed states. Because MLCs can be set to one of four different states, each MLC can program or store two bits according to a set encoding method. TLCs can include eight states, P0 to P7. Among these states, P0 can represent an erased state, and P1 to P7 can represent programmed states. Because TLCs can be set to one of eight different states, each TLC can program or store three bits according to a set encoding method. QLCs can include 16 states, P0 to P15. Among these states, P0 can represent an erased state, and P1 to P15 can represent programmed states. Because QLC can be set to one of sixteen different states, each QLC can program or store four bits depending on the set encoding method.

[0065] Re-reference Figure 2 and Figure 3 , the memory device 200 may include a plurality of memory cells (eg, NAND flash memory cells). The memory cells are arranged as follows Figure 3The array arrangement of rows and columns shown. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are connected to a bit line (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when the word line is addressed, the data to be written ("1" or "0") is provided to the bit line. During a read operation, the word line is addressed again, and the threshold voltage of each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. For example, a coding scheme (eg, Gray coding) may be used to program memory cells in order to increase the capacity of the memory system 10 , such as an SSD.

[0066] Figure 5A is a diagram illustrating an example of encoding of a multi-layer cell (MLC).

[0067] Reference Figure 5A , the MLC can be programmed using a set type of encoding. The MLC can have four programming states, including an erased state E (or PV0) and first to third programming states PV1 to PV3. The erased state E (or PV0) can correspond to "11". The first programming state PV1 can correspond to "10". The second programming state PV2 can correspond to "00". The third programming state PV3 can correspond to "01".

[0068] In MLC, such as Figure 5B As shown, there are two types of pages, including LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For the MSB page, a single threshold is VT1. VT1 distinguishes between the first programmed state PV1 and the second programmed state PV2. For the LSB page, two thresholds are used, including VT0 and VT2. VT0 distinguishes between the erased state E and the first programmed state PV1. VT2 distinguishes between the second programmed state PV2 and the third programmed state PV3.

[0069] Figure 6A is a diagram illustrating an example of Gray coding of a triple-layer cell (TLC).

[0070] Reference Figure 6A, Gray coding can be used to program TLC. TLC can have 8 programming states, including an erased state E (or PV0) and a first programming state PV1 to a seventh programming state PV7. The erased state E (or PV0) may correspond to "111". The first programming state PV1 may correspond to "011". The second programming state PV2 may correspond to "001". The third programming state PV3 may correspond to "000". The fourth programming state PV4 may correspond to "010". The fifth programming state PV5 may correspond to "110". The sixth programming state PV6 may correspond to "100". The seventh programming state PV7 may correspond to "101".

[0071] In TLC, as Figure 6B As shown, there are three types of pages, including LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For the MSB page, the two thresholds include threshold VT0, which distinguishes between the erased state E and the first programmed state PV1, and threshold VT4, which distinguishes between the fourth programmed state PV4 and the fifth programmed state PV5. For the CSB page, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between the first programmed state PV1 and the second programmed state PV2. VT3 distinguishes between the third programmed state PV3 and the fourth programmed state PV4. VT5 distinguishes between the fifth programmed state PV5 and the sixth programmed state PV6. For the LSB page, the two thresholds include VT2 and VT6. VT2 distinguishes between the second programmed state PV2 and the third programmed state PV3. VT6 distinguishes between the sixth programmed state PV6 and the seventh programmed state PV7.

[0072] In such Figure 5A and Figure 6A After programming a memory array comprising a plurality of memory cells, when a read operation is performed on the memory array using a reference voltage such as a read threshold voltage (also referred to as a "read voltage level" or "read threshold"), the charge level of the memory cell (e.g., the threshold voltage level of the transistor of the memory cell) is compared with one or more reference voltages to determine the state of each memory cell. When a particular read threshold is applied to the memory array, those memory cells having a threshold voltage level higher than the reference voltage are turned on and detected as "on" cells, while those memory cells having a threshold voltage level lower than the reference voltage are turned off and detected as "off" cells. Thus, each read threshold is set between adjacent threshold voltage distribution windows corresponding to different programming states, so that each read threshold can distinguish between these programming states by turning on or off the memory cell transistor.

[0073] When a read operation is performed on a memory cell in a data storage device using MLC technology, the threshold voltage level of the memory cell is compared with more than one read threshold level to determine the state of each memory cell. Distorted or overlapping threshold voltage distributions may cause read errors. For example, due to program and erase (P / E) cycles, inter-cell interference and / or data retention errors, the ideal memory cell threshold voltage distribution may be significantly distorted or overlapped. For example, as the program / erase cycle increases, the margin between adjacent threshold voltage distributions of different programming states decreases and the distributions eventually overlap. Therefore, a memory cell whose threshold voltage falls within the overlapping region of adjacent distributions may be read as being programmed to a value different from the original target value, and thus cause a read error. In many cases, such read errors can be managed by using an error correction code (ECC). When the number of bit errors of the read operation exceeds the ECC correction capability of the data storage, the read operation using the set read threshold voltage fails. The set read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage may be a read threshold voltage used in the most recent successful decoding, that is, a read voltage used in a read-through read operation performed before the read retry operation. When a read operation using the set read threshold voltage fails, the controller 100 may control, for example, Figure 7 Error recovery algorithm for the algorithm shown.

[0074] Reference Figure 7 , the controller 100 may perform one or more read retry operations on the memory cell using one or more read threshold voltages applied in a set order (S100). For example, the read threshold voltage may include N (e.g., N is 5 or 10) read threshold voltages (or read voltage levels), including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage may be a read threshold voltage used in the most recent successful decoding, i.e., a read voltage used in a read-through read operation performed prior to the read retry operation. The controller 100 may perform a read retry operation until it is determined that the decoding associated with the corresponding read retry operation is successful.

[0075] When all read retry operations using the read threshold voltage have failed, the controller 100 may perform additional recovery operations. For example, the additional recovery operations may include optimal read threshold voltage search (S200), soft decoding using error correction code (ECC) (S300), and / or redundant array of independent disks (RAID) recovery (S400).

[0076] As described above, due to various noise sources, data retrieved from a memory device (e.g., a NAND flash memory device) in a data storage device (e.g., a solid-state drive (SSD)) often contains many bit errors. In order to protect the data, the data is encoded with an error correction code before being written to the memory device (i.e., before being written to the storage medium). A decoder can correct all bit errors by using this error correction code. Figure 7 As shown in the "Read Retry" section, in one embodiment of the present invention, when the number of errors exceeds the capability of the error correction code, the data storage device may invoke a specific defense algorithm (e.g., a read retry operation) to read the storage medium multiple times using parameters more optimal than those of the original read operation until the data can be recovered by the error correction code. As described in detail below, different read thresholds may be used to better read data pages.

[0077] For solid-state drives, one source of increased bit errors is in Figure 8 A sub-optimal read threshold is used during the read operation shown. Figure 8 In

[0014] , OptVt represents an optimal read threshold voltage, and Rd0 to Rd2 represent suboptimal read threshold voltages during a read operation for a particular page (e.g., an LSB page) of a triple-level cell (TLC) NAND flash memory device. One method for estimating the optimal read threshold (e.g., the eBoost algorithm) performs multiple additional read operations on the same page using different read thresholds and estimates the optimal read threshold that minimizes bit errors in the retrieved data. These additional read operations increase the latency of the read operation and reduce the quality of service (QoS) of the data storage device (or memory system). Therefore, embodiments of the present invention provide a scheme for estimating the optimal read threshold without performing additional read operations.

[0078] Figure 9 is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0079] Reference Figure 9 , the memory system 10 includes a controller 100 and a memory device 200. The memory device 200 may include a plurality of memory cells (eg, NAND flash memory cells) 210. The memory cells are as follows: Figure 3As shown, the memory cells are arranged in an array of rows and columns. The cells in each row are connected to a word line (e.g., WL0), while the cells in each column are connected to a bit line (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, when the word line is addressed, the data to be written ("1" or "0") is provided to the bit line. During a read operation, the word line is addressed again, and the threshold voltage of each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. Memory cells may be programmed using a coding scheme (eg, Gray coding) in order to increase the capacity of the memory system 10 such as an SSD.

[0080] The controller 100 may include a read processor 910, a decoder 920, and an optimal read threshold determiner 930. Although the components of the controller 100 are shown as being implemented separately, these components may be implemented using Figure 2 The internal components of the control component 120 (ie, firmware (FW)) are implemented. Figure 10 , but the controller 100 and the memory device 200 may include a Figure 2 Various other components shown.

[0081] The read processor 910 may respond to a request from a host (eg, Figure 1 The read processor 910 may control one or more read operations for the memory device 200 based on a read request from a host device 5. The read processor 910 may use various read thresholds to control the read operations. The decoder 920 may decode data associated with the read operations.

[0082] In various embodiments of the present invention, the read processor 910 may use a selected read threshold from a set read level table to control a read operation for a memory cell. In various embodiments, the read level table may include multiple read thresholds, and the selected read threshold may include a default read threshold. Figure 6BAs shown, when a read operation is performed on the MSB page of the TLC, the selected read threshold may include a pair of a first read threshold and a second read threshold [VT0, VT4]. The first read threshold VT0 is used to distinguish between the erased state (ie, E) and the first programmed state (ie, PV1), and the second read threshold VT4 is used to distinguish between the fourth programmed state (ie, PV4) and the fifth programmed state (ie, PV5). Figure 6B As shown, when a read operation is performed on the LSB page of the TLC, the selected read threshold may include a pair of a first read threshold and a second read threshold [VT2, VT6]. The first read threshold VT2 is used to distinguish between the second programming state (i.e., PV2) and the third programming state (i.e., PV3), and the second read threshold VT6 is used to distinguish between the sixth programming state (i.e., PV6) and the seventh programming state (i.e., PV7).

[0083] In one embodiment of the present invention, it can be determined whether a read operation using a read threshold selected from the read threshold set succeeds or fails based on the decoding result of the decoder 920. When a read operation using the selected read threshold fails, the read processor 910 can, for example, Figure 7 The use of a read retry entry is shown to control one or more read retry operations for a memory cell.

[0084] The optimal read threshold determiner 930 can provide a solution for estimating (or predicting) the optimal read threshold voltage (Vt). The optimal read threshold determiner 930 can be implemented using one or more deep neural networks (DNNs). In various embodiments of the present invention, the optimal read threshold determiner 930 can include a training component 930A and an inference component 930B. The operations of the training component 930A and the inference component 930B are described below.

[0085] Figure 10 is a diagram illustrating an example of a neural network 1000 (representing a training component) according to one embodiment of the present invention. In various embodiments of the present invention, for optimal read threshold estimation or prediction, the neural network 1000 may be included in Figure 9 In other words, the neural network 1000 can be used for Figure 9 The optimal read threshold determiner 1030 is implemented in .

[0086] Reference Figure 10, a feature map 1002 associated with one or more input conditions can be input to the neural network 1000. In turn, the neural network 1000 can output information 1004. As shown, the neural network 1000 includes an input layer 1010, one or more hidden layers 1020, and an output layer 1030. Features from the feature map 1002 can be connected to input nodes in the input layer 1010. Information 1004 can be generated from the output nodes of the output layer 1030. One or more hidden layers 1020 can exist between the input layer 1010 and the output layer 1030. The neural network 1000 can be pre-trained to process features from the feature map 1002 through different layers 1010, 1020, and 1030 to output information 1004.

[0087] Neural network 1000 can be a multi-layer neural network representing a network of interconnected nodes, such as an artificial deep neural network, in which knowledge about the nodes (e.g., information about the specific features represented by the nodes) is shared across layers, while also retaining knowledge specific to each layer. Each node represents a piece of information. Knowledge can be exchanged between nodes through node-to-node interconnections. Input to neural network 1000 can activate a group of nodes. In turn, this group of nodes can activate other nodes, thereby propagating knowledge about the input. This activation process can be repeated across other nodes until a node in output layer 1030 is selected and activated.

[0088] As shown, neural network 1000 includes a hierarchy of layers, and the hierarchy of layers represents a hierarchy of nodes interconnected in a feedforward manner. Input layer 1010 can be located at the lowest level of the hierarchy. Input layer 1010 can include a group of nodes referred to herein as input nodes. When feature map 1002 is input to neural network 1000, each of the input nodes of input layer 1010 can be connected to each feature of feature map 1002. Each of the connections can have a weight. These weights can be a set of parameters derived from the learning / training of neural network 1000. Input nodes can transform features by applying activation functions to these features. The information obtained from this transformation can be passed to nodes at higher levels of the hierarchy.

[0089] The output layer 1030 may be located at the highest hierarchical level. The output layer 1030 may include one or more output nodes. Each output node may provide a specific value for the output information 1004. The number of output nodes may depend on the desired amount of output information 1004. In other words, in one embodiment, there is a one-to-one correspondence or mapping between the number of output nodes and the amount of output information 1004.

[0090] The hidden layer 1020 may be located between the input layer 1010 and the output layer 1030. The hidden layer 1020 may include "N" hidden layers, where "N" is an integer greater than or equal to 1. Each of the hidden layers 1020 may include a set of nodes referred to herein as hidden nodes. Exemplary hidden layers may include upsampling layers, convolutional layers, fully connected layers, and / or data transformation layers.

[0091] At the lowest level hidden layer 1020, the hidden nodes at that level can be interconnected with input nodes. At the highest level hidden layer 1020, the hidden nodes at that level can be interconnected with output nodes. Input nodes may not be directly interconnected with output nodes. If there are multiple hidden layers, the input nodes are interconnected with the hidden nodes of the lowest hidden layer. These hidden nodes are then interconnected with the hidden nodes of the next hidden layer. An interconnection can represent a piece of information learned about two interconnected nodes. The interconnections can have numerical weights that can be adjusted (e.g., based on a training data set) to enable the neural network 1000 to adapt to the input and learn.

[0092] Typically, the hidden layer 1020 can allow knowledge about the input nodes of the input layer 1010 to be shared among the output nodes of the output layer 1030. To this end, a transformation f can be applied to the input nodes through the hidden layer 1020. In one example, the transformation f can be nonlinear. Different nonlinear transformations f can be used, including, for example, a rectification function f(x)=max(0,x). In another example, a specific nonlinear transformation f can be selected based on cross-validation. For example, given a known example pair (x, y), where x∈X and y∈Y, the function f:X→Y is selected when it produces the best match.

[0093] For example, neural network 1000 can be a deep learning neural network for a memory system that includes a NAND flash memory device. A deep learning neural network can be created using output nodes and "K" input nodes, where "K" is the number of factors (e.g., features) that define input conditions for the memory system. The output nodes can be used to perform activation functions for the combination of input conditions. The number of layers in neural network 1000 and the size of each layer can depend on the NAND flash memory device and the amount of data that the NAND flash memory device can store.

[0094] As described above, neural network 1000 may implement Figure 9The optimal read threshold determiner 1030 in . In various embodiments of the present invention, implementations of the neural networks described in the following patent applications may be used: U.S. Patent Application No. 17 / 157,495, filed on January 25, 2021, entitled “DEEP LEARNING BASED PROGRAM-VERIFY MODELING AND VOLTAGE ESTIMATION FOR MEMORY DEVICES”; U.S. Patent Application No. 17 / 374,750, filed on July 13, 2021, entitled “SYSTEMS AND METHODS FOR NON-PARAMETRIC PV-LEVEL MODELING AND READ THRESHOLD VOLTAGE ESTIMATION”; U.S. Patent Application No. 17 / 443,755, filed on July 27, 2021, entitled “SYSTEMS AND METHODS FOR MODELESS READ THRESHOLD VOLTAGE ESTIMATION”. and U.S. patent application Ser. No. 17 / 443,726, filed on July 27, 2021, entitled “READ THRESHOLD VOLTAGE ESTIMATION SYSTEMS AND METHODS FOR PARAMETRIC PV-LEVEL MODELING,” the entire contents of which are incorporated herein by reference in their entirety.

[0095] Figure 11 is a diagram illustrating an optimal read threshold estimator 1100 (representing an inference component) according to one embodiment of the present invention. For example, the optimal read threshold estimator 1100 may correspond to Figure 9 The reasoning component 930B of the optimal read threshold determiner 930 in FIG.

[0096] Reference Figure 11 , the optimal read threshold estimator 1100 may include a deep neural network (DNN). The DNN 1100 may be implemented as a system on chip (SoC) or firmware (FW) depending on the size of the DNN used. In various embodiments of the present invention, the DNN 1600 may be used for a specific page (e.g., MSB, CSB, or LSB page) of a triple-level cell (TLC) NAND flash memory device.

[0097] The optimal read threshold estimator 1100 can estimate the optimal read threshold for a failed read page based on information collected from previous read attempts of the failed read page. That is, the DNN 1100 can estimate the optimal read threshold without requiring any additional sensing operations and any intermediate parameter estimation (which are necessary in the above-described embodiments).

[0098] like Figure 11 and Figure 12 As shown, DNN 1100 may receive information associated with a previous read operation as input. The input may include a read threshold set (Vt read0 、Vt read1 , ...), checksum (CS read0 , CS read1 , ...) and asymmetric ratios / counts of 1 / counts of 0 (AR read0 , AR read1 ,……).like Figure 12 As shown, DNN 1100 outputs the estimated threshold Vt DNN , the estimated threshold Vt DNN is output to the loss function 1150. The loss function 1150 receives Vt Opt signal and will estimate the threshold Vt DNN With Vt Opt The signals are compared. Figure 12 As shown, this comparison is fed back to the DNN 1100 and can continue to estimate Vt DNN Until the comparison (difference) provided back to DNN 1100 is low enough.

[0099] Figure 11 The read threshold set Vt in may include multiple values for each read of a particular page. Figure 6B As shown, the read threshold set Vt for reading the LSB page of the TLC memory device may include two read threshold voltage values VT2 and VT6. VT2 distinguishes the second programming state PV2 from the third programming state PV3. VT6 distinguishes the sixth programming state PV6 from the seventh programming state PV7. For the CSB page of the TLC memory device, it can be estimated as follows Figure 6B For the MSB page of a TLC memory device, the following can be estimated: Figure 6B The two read threshold voltage values (VT0, VT4) are shown.

[0100] Each checksum can be an approximation of the number of bit errors, which indicates the noise level in the best read threshold voltage estimate. When a read page is decoded using a low-density parity-check (LDPC) code as an error correction code (ECC), the syndrome weight can correspond to the number of unsatisfied check (USC) nodes of the codeword and can be used as a checksum.

[0101] Each asymmetry ratio / count of 1s / count of 0s (i.e., an asymmetric ratio of count of 1s to count of 0s) can be any one of the following three metrics: count of 1s; count of 0s; and an asymmetric ratio of count of 1s to count of 0s. The count of 1s can be the number of bits that are 1 in the codeword. The count of 0s can be the number of bits that are 0 in the codeword. The asymmetry ratio AR can be defined as the ratio of the number of first binary values to the number of second binary values in the codeword. For example, the asymmetry ratio AR can be a value representing the number of 1s (i.e., count of 1s) divided by the number of 0s (i.e., count of 0s) in the decoded original data. In one embodiment using a reverse logic convention, AR can be the number of 0s (i.e., count of 0s) divided by the number of 1s (i.e., count of 1s). In one embodiment, the read threshold optimization system of the present invention can use any of the asymmetric ratios described in U.S. patent application Ser. No. 16 / 927,567, filed on July 13, 2020, entitled “READ THRESHOLD OPTIMIZATION SYSTEMS AND METHODS USING DOMAIN TRANSFORMATION.”

[0102] DNN 1100 may be a single fully connected network with multiple layers in which the setting function (e.g., rectified linear unit (ReLu) function) is nonlinear, or any other suitable DNN structure. Figure 11 The input shown (ie, the read threshold set (Vt read0 、Vt read1 , ...), checksum (CS read0 , CS read1 , ...) and the asymmetric ratio / count of 1 / count of 0 (AR read0 , AR read1 , ...)) to estimate (i.e., predict) the optimal read threshold set OptVt. The predicted optimal read threshold set OptVt can be used for the next read operation and subsequent read operations until successful recovery of data read from a specific NAND flash memory page is achieved. For this estimate, Figure 12 As shown, DNN 1100 is trained.

[0103] The DNN 1100 may be trained on a specific dataset that includes a set of read thresholds (Vt read0 、Vt read1 , ...), checksum (CS read0 , CS read1 , ...) and asymmetric ratios / counts of 1 / counts of 0 (AR read0 , AR read1 , ...) and the predicted optimal read threshold voltage as output. In some embodiments, DNN 1100 can be trained offline on measurements collected from pages of real NAND flash memory devices or appropriate channel models.

[0104] For training of the DNN 1100, a set loss function 1150 (e.g., a differentiable loss function) may be defined to measure the predicted optimal read threshold voltage Vt as the output of the DNN 1100. DNN The expected optimal read threshold voltage Vt of the data points in the data set Opt For example, the mean square error function (Vt DNN -Vt Opt ) 2 / n (where n is the number of data points in the subset of training data of the dataset) may be used as the loss function 1150. The loss function 1150 may not be limited to the mean square error function.

[0105] The DNN 1100 may receive the results from the loss function 1150. Further, the DNN 1100 may be trained to find the predicted optimal read threshold voltage Vt based on the results of the loss function. DNN , so that the real (actual) optimal read threshold voltage Vt Opt and the predicted optimal read threshold voltage Vt from DNN 1100 DNN Minimize the difference between them.

[0106] exist Figure 10 In the example of , the neural network 1000 (ie, Figure 11 The DNN 1100 can be pre-trained to process features from the feature map 1002 (i.e., read threshold, checksum, and asymmetric ratio / count of 1 / count of 0) through different layers 1010, 1020, and 1030 to output an optimal read threshold voltage 1004. Therefore, the DNN 1100 can be trained to improve the optimal read threshold voltage so that the actual optimal read threshold voltage Vt Opt and the predicted optimal read threshold voltage Vt from DNN 1100 DNN Minimize the difference (or error) between them.

[0107] In various embodiments of the present invention, the weights of the DNN 1100 may be obtained. For example, a stochastic gradient descent (SGD) process, its variants, and / or other algorithms may be used to obtain the weights of the DNN 1100 such that the loss function is minimized. The obtained weights (weight values) may then be used to process the input features (vectors) to obtain an optimal read threshold voltage. In various embodiments, the input features may have a read threshold, a checksum, and an asymmetric ratio. For example, the obtained weights of the DNN may be a plurality of matrices A DNN,0 、A DNN,1 ,……,A DNN,N and the bias vector b DNN,0 、b DNN,1 ,……,b DNN,N In other words, the weights obtained by DNN can include multiple matrices A DNN,0 、A DNN,1 ,……,A DNN,N and the bias vector b DNN,0 、b DNN,1 ,……,b DNN,N combination.

[0108] The DNN 1100 may receive inputs (i.e., a read threshold set, a checksum, and an asymmetric ratio / count of 1s / count of 0s) and estimate an optimal read threshold voltage OptVt based on the received inputs and weights. An example of estimating the optimal read threshold set by the DNN 1100 is described below.

[0109] In one embodiment, three reads such as a checksum and an asymmetric ratio of / 1 counts / 0 counts are used to collect input information. As described above, because the LSB page in a TLC NAND flash memory device uses two read threshold voltages, these three reads correspond to six read threshold voltages. Therefore, the read threshold set Vt, the checksum CS, and the asymmetric ratio of / 1 counts / 0 counts AR are expressed as follows:

[0110]

[0111] CS=[CS read ,CS read ,CS read ];and

[0112] AR=[AR read0 ,AR read1 ,AR read2 ].

[0113] In the above equation, represents the first read threshold voltage for the zeroth read of a particular page (eg, Figure 6BVT2), represents a first read threshold voltage for a first read of a particular page, and Represents a first read threshold voltage for a second read of a particular page. represents the second read threshold voltage for the zeroth read of a particular page (eg, Figure 6B VT6), represents a second read threshold voltage for a first read of a particular page, and represents the second read threshold voltage for the second read of a particular page. CS read0 represents the checksum associated with the zeroth read of a particular page, CS read1 represents the checksum associated with the first read of a particular page, and CS read2 Represents the checksum associated with the second read of a particular page. read0 represents the checksum associated with the zeroth read of a particular page, AR read1 represents the checksum associated with the first read of a particular page, and AR read2 Represents the checksum associated with the second read of a particular page.

[0114] In one embodiment of the present invention, Figure 12 The DNN 1100 shown in FIG1 may receive input information obtained from three reads (i.e., a read threshold set, a checksum, and an asymmetric ratio / a count of 1s / a count of 0s). Further, the DNN 1100 may estimate an optimal read threshold voltage OptVt based on the received input information and the weights, which is expressed as follows:

[0115] OptVt=A DNN,2 ×(R(A DNN,1 ×R(A DNN,0 ×[Vt,CS,AR]+b DNN,0 )+b DNN,1 ))+b DNN,N2 .

[0116] The above equation for three (3) previous reads can be generalized to N previous reads as follows:

[0117] OptVt=A DNN,N ×R(A DNN,N-1 ×R(A DNN,N-2 ×R(…R(A DNN,0 ×[Vt,CS,AR]+b DNN,0 )…)+b DNN,N-2 )+b DNN,N-1 )+b DNN,N .

[0118] In the above equation, R represents the activation function. In various embodiments of the present invention, the activation function may be a rectified linear unit (ReLU) activation function. Other activation functions may be applicable. As described above, the weights of the DNN may be multiple matrices A DNN,0 、A DNN,1 ,……,A DNN,N and the bias vector b DNN,0 、b DNN,1 ,……,b DNN,N form.

[0119] Figure 13 FIG. 1 is a flow chart illustrating an optimal read threshold estimation operation 1300 according to one embodiment of the present invention. The optimal read threshold estimation operation 1300 may be performed by Figure 9 The optimal read threshold value determiner 930 of the controller 100 in the embodiment of the present invention is executed, and the optimal read threshold value determiner 930 can utilize Figure 11 The neural network (i.e., DNN) 1100 in is implemented.

[0120] Reference Figure 13 In operation 1310 , the optimal read threshold determiner 930 may perform one or more read operations on a page selected from among a plurality of pages using a read threshold set including a plurality of read threshold voltages.

[0121] In operation 1320 , the optimal read threshold determiner 930 may obtain a read threshold set associated with decoding of the selected page, a checksum value, and an asymmetric ratio of counts of 1s to counts of 0s according to each read operation.

[0122] In operation 1330 , the optimal read threshold determiner 930 may provide the obtained read threshold set, the checksum value, and the asymmetry ratio as input information of the neural network.

[0123] In operation 1340 , the optimal read threshold determiner 930 may estimate an optimal read threshold voltage based on input information and a weight of the input information, the weight including a combination of a plurality of matrices and a bias vector, through the neural network 1100 .

[0124] In various embodiments of the present invention, the neural network 1100 may be trained to obtain weights of input information so as to minimize a set loss function. In this embodiment, the set loss function may include a differentiable loss function for measuring the error between the output of the neural network and the optimal read threshold voltage.

[0125] In other embodiments, the neural network 1100 may estimate the optimal read threshold voltage based on a combination of input information, multiple matrices, bias vectors, and a specific activation function. In this embodiment, the optimal read threshold voltage may be based on the above equation OptVt=A DNN,N ×R(A DNN,N-1 ×R(A DNN,N-2 ×R(…R(A DNN,0 ×[Vt,CS,AR]+b DNN,0 )…)+b DNN,N-2 )+b DNN,N-1 )+b DNN,N to estimate, where OptVt represents the optimal read threshold voltage, Vt represents the read threshold set, CS represents the checksum value, AR represents the asymmetric ratio of the count of 1 to the count of 0, and A DNN,N represents the (N+1)th matrix, b DNN,N Denotes the (N+1)th bias vector, and R denotes an activation function. In this embodiment, the activation function may include a rectified linear unit (ReLU) activation function.

[0126] In various embodiments of the present invention, the selected page may include a least significant bit (LSB) page of a triple-level cell (TLC). In this embodiment, the read threshold set may include a first read threshold voltage for distinguishing an erased state from a first programmed state and a second read threshold voltage for distinguishing a second programmed state from a third programmed state.

[0127] As described above, embodiments of the present invention can provide a solution for estimating the optimal read threshold voltage in a memory system (e.g., an SSD). Embodiments of the present invention can estimate the optimal read threshold voltage using information obtained from previous read attempts via a neural network without requiring any additional sensing operations or any intermediate parameter estimation. Therefore, these embodiments can improve the quality of service (QoS) and reliability of the memory system.

[0128] Although the foregoing embodiments have been shown and described in some detail for purposes of clarity and understanding, the present invention is not limited to the details provided. As will be appreciated by those skilled in the art based on the foregoing disclosure, there are many alternative ways to implement the present invention. Therefore, the disclosed embodiments are illustrative, not restrictive. The present invention is intended to encompass all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments may be combined to form additional embodiments.

Claims

1. A memory system comprising: a memory device comprising a plurality of pages; as well as A controller, including a neural network, that: performing one or more read operations on a page selected from among the plurality of pages using a read threshold set comprising a plurality of read threshold voltages; obtaining the set of read thresholds, a checksum value, and an asymmetric ratio of counts of ones to counts of zeros associated with decoding of the selected page based on each of the one or more read operations; providing the obtained read threshold set, the checksum value, and the asymmetry ratio as input information to the neural network; as well as An optimal read threshold voltage is estimated by the neural network based on the input information and weights of the input information, the weights comprising a combination of a plurality of matrices and a bias vector.

2. The memory system according to claim 1, wherein the neural network is trained to obtain the weights so that a set loss function is minimized.

3. The memory system of claim 2, wherein the set loss function comprises a differentiable loss function for measuring a corresponding error between an output of the neural network and the optimal read threshold voltage. 4 . The memory system of claim 1 , wherein the controller estimates the optimal read threshold voltage based on a combination of the input information, the plurality of matrices, the bias vector, and an activation function.

5. The memory system of claim 4 , wherein the controller estimates the optimal read threshold voltage based on the following equation: OptVt=A DNN,N ×R(A DNN,N-1 ×R(A DNN,N-2 ×R(…R(A DNN,0 ×[Vt,CS,AR]+b DNN,0 )…)+b DNN,N-2 )+b DNN,N-1 )+b DNN,N , wherein OptVt represents the optimal read threshold voltage, Vt represents the read threshold set, CS represents the checksum value, AR represents the asymmetric ratio of the count of the 1s to the count of the 0s, and A DNN,N represents the N+1th matrix, b DNN,N denotes the N+1th bias vector, and R denotes the activation function. 6 . The memory system of claim 5 , wherein the asymmetric ratio of the count of ones to the count of zeros comprises a ratio of the count of ones divided by the count of zeros.

7. The memory system of claim 4, wherein the activation function comprises a rectified linear unit (ReLU) activation function.

8. The memory system of claim 1, wherein the selected page comprises a least significant bit (LSB) page of a triple level cell (TLC).

9. The memory system of claim 8, wherein the read threshold set comprises: a) a first read threshold voltage for distinguishing an erased state from a first programmed state, and b) a second read threshold voltage for distinguishing a second programmed state from a third programmed state.

10. A method of operating a memory system, the memory system comprising a memory device having a plurality of pages and a controller having a neural network, the method comprising: performing one or more read operations on a page selected from among the plurality of pages using a read threshold set comprising a plurality of read threshold voltages; obtaining the set of read thresholds, a checksum value, and an asymmetric ratio of counts of ones to counts of zeros associated with decoding of the selected page based on each of the one or more read operations; providing the obtained read threshold set, the checksum value, and the asymmetry ratio as input information to the neural network; as well as An optimal read threshold voltage is estimated by the neural network based on the input information and weights of the input information, the weights comprising a combination of a plurality of matrices and a bias vector.

11. The method according to claim 10, wherein the neural network is trained to obtain the weights so that a set loss function is minimized.

12. The method of claim 11, wherein the set loss function comprises a differentiable loss function for measuring a corresponding error between an output of the neural network and the optimal read threshold voltage. 13 . The method of claim 10 , wherein the controller estimates the optimal read threshold voltage based on a combination of the input information, the plurality of matrices, the bias vector, and an activation function.

14. The method of claim 13 , wherein the controller estimates the optimal read threshold voltage based on the following equation: OptVt=A DNN,N ×R(A DNN,N-1 ×R(A DNN,N-2 ×R(…R(A DNN,0 ×[Vt,CS,AR]+b DNN,0 )…)+b DNN,N-2 )+b DNN,N-1 )+b DNN,N , wherein OptVt represents the optimal read threshold voltage, Vt represents the read threshold set, CS represents the checksum value, AR represents the asymmetric ratio of the count of 1s to the count of 0s, and A DNN,N represents the N+1th matrix, b DNN,N denotes the N+1th bias vector, and R denotes the activation function. 15 . The method of claim 14 , wherein the asymmetric ratio of the count of ones to the count of zeros comprises a ratio of the count of ones divided by the count of zeros.

16. The method according to claim 13, wherein the activation function comprises a rectified linear unit activation function (ReLU activation function).

17. The method of claim 10, wherein the selected page comprises a least significant bit (LSB) page of a triple-level cell (TLC).

18. The method of claim 17, wherein the read threshold set comprises: a) a first read threshold voltage for distinguishing an erased state from a first programmed state, and b) a second read threshold voltage for distinguishing a second programmed state from a third programmed state.

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