Test structure and method of testing the same

Abstract

This invention provides a test structure and its test method. The test structure includes a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially. The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are arranged opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion. A plurality of release holes are formed in the first insulating layer. All release holes are spaced around the outside of the first portion. The test structure can automatically measure and obtain the side-cut distance of the sacrificial layer before and after the sacrificial layer release cavity structure process by a testing machine, thereby improving the measurement accuracy and testing efficiency of the side-cut distance and saving testing time and labor costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a test structure and its test method. Background Technology

[0002] Existing MEMS devices all employ a process of creating a cavity structure by etching a sacrificial layer using wet etching. This process requires monitoring the side-cut distance formed within the sacrificial layer. Typically, monitoring this side-cut distance in wet etching requires optical measurement methods. However, current measurement techniques rely on optical microscopes, which are manual and prone to errors. Furthermore, current testing structures are not precise enough, allowing only approximate assessments and introducing human error. Summary of the Invention

[0003] The purpose of this invention is to provide a test structure and test method that can automatically monitor the side-cut distance of the sacrificial layer release cavity structure process, thereby reducing labor costs and improving measurement accuracy.

[0004] To address the aforementioned problems, this invention provides a test structure capable of automatic measurement using a testing machine before and after the sacrificial layer release cavity structure process. The test structure comprises a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially from bottom to top.

[0005] The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are disposed opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion, and a plurality of release holes are formed in the first insulating layer. All the release holes are spaced around the outside of the first portion.

[0006] Optionally, the second electrode structure further includes a second insulating layer, in which the second electrode layer is embedded and located inside the second electrode layer, and the second insulating layer covers the second portion.

[0007] Furthermore, both the first electrode layer and the second electrode layer are polycrystalline silicon material layers, both the first insulating layer and the second insulating layer are silicon nitride material layers, and the dielectric layer is a silicon oxide material layer.

[0008] Optionally, the first electrode layer, the first portion, and the second electrode layer have the same shape and the same cross-sectional area.

[0009] Optionally, all the release holes are equally spaced on the outer side of the first part.

[0010] Optionally, the diameter of the release hole is greater than the distance between two adjacent release holes.

[0011] Optionally, the test structure further includes a first test pad and a second test pad, wherein the first test pad is connected to the first electrode layer and the second test pad is connected to the second electrode layer.

[0012] On the other hand, the present invention also provides a testing method for a test structure, comprising the following steps:

[0013] The test structure is formed on a semiconductor substrate;

[0014] The testing equipment automatically measures the first capacitance between the first electrode layer and the second electrode layer, and obtains the height of the dielectric layer between the first electrode layer and the second electrode layer through the first capacitance.

[0015] A sacrificial layer release cavity structure process is performed, in which the dielectric layer is etched from the release hole to expose the semiconductor substrate, at which time a side hole is formed in the dielectric layer;

[0016] The testing machine automatically measures the second capacitance between the first electrode layer and the second electrode layer, and obtains the side-cut distance of the side cut through the second capacitance and the height.

[0017] Optionally, the method for obtaining the height of the dielectric layer between the first electrode layer and the second electrode layer is as follows:

[0018] At the first test pad and the second test pad, the testing machine automatically measures the first capacitance between the first electrode layer and the second electrode layer.

[0019] The height of the dielectric layer between the first electrode layer and the second electrode layer is calculated based on the first capacitance.

[0020] Optionally, the method for obtaining the side-cut distance is as follows:

[0021] At the first test pad and the second test pad, the testing machine automatically measures the second capacitance between the first electrode layer and the second electrode layer;

[0022] The side cut distance is calculated based on the second capacitor and the height.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] This invention provides a test structure and its test method. The test structure includes a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially from bottom to top. The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are arranged opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion, and a plurality of release holes are formed in the first insulating layer. All the release holes are spaced around the outside of the first portion. The test structure can automatically measure and obtain the side-cut distance of the sacrificial layer before and after the sacrificial layer release cavity structure process by a test machine, thereby improving the measurement accuracy and testing efficiency of the side-cut distance. It also solves the problem of manual operation in traditional optical measurement, greatly saving testing time and labor costs. Attached Figure Description

[0025] Figure 1 This is a top view schematic diagram of a test structure provided in an embodiment of the present invention;

[0026] Figure 2 for Figure 1 A schematic diagram of the structure at AA' and before the process of releasing the cavity structure in the sacrificial layer;

[0027] Figure 3 This is a flowchart illustrating a testing method for a test structure provided in an embodiment of the present invention.

[0028] Figure 4 This is a simplified structural diagram of the test structure provided in an embodiment of the present invention before the process of releasing the cavity structure in the sacrificial layer;

[0029] Figure 5 for Figure 1 A schematic diagram of the structure after the cavity structure is released at AA' and in the sacrificial layer;

[0030] Figure 6 This is a simplified structural diagram of the test structure provided in an embodiment of the present invention after the sacrificial layer releases the cavity structure process.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10-First electrode structure; 11-First electrode layer; 12-First insulating layer; 20-Dielectric layer; 21-First part; 22-Second part; 30-Second electrode structure; 31-Second electrode layer; 32-Second insulating layer; 33-Release hole; 41-First test pad; 42-Second test pad. Detailed Implementation

[0033] The following will provide a more detailed description of a test structure and test method of the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0034] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0035] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0036] Figure 1 This is a top view schematic diagram of a test structure provided in this embodiment. Figure 2 for Figure 1 A schematic diagram of the structure at AA' before the process of releasing the cavity structure in the sacrificial layer. (See diagram below.) Figure 1 and Figure 2 As shown, this embodiment provides a test structure that can be used to automatically measure the side-cut distance of the sacrificial layer before and after the sacrificial layer release cavity structure process of MEMS devices. The test structure is formed on a semiconductor substrate (not shown in the figure), which has an array of chip regions and dicing channels surrounding the chip regions. The test structure is formed, for example, on the dicing channels. Other devices or other structural layers may also be formed in the semiconductor substrate.

[0037] The test structure includes a first electrode structure 10, a dielectric layer 20, and a second electrode structure 30 stacked sequentially from bottom to top, with the first electrode structure 10 and the second electrode structure 30 facing each other.

[0038] The first electrode structure 10 includes a first electrode layer 11 and a first insulating layer 12, with the first electrode layer 11 embedded in the first insulating layer 12. The second electrode structure 30 includes a second electrode layer 31 and a second insulating layer 32, with the second electrode layer 31 embedded in the second insulating layer 32. The first insulating layer 12 surrounds the outside of the first electrode layer 11, making the overall structure of the first electrode structure 10 stable and defining the shape of the first electrode layer 11. The second insulating layer 32 surrounds the outside of the second electrode layer 31, making the overall structure of the second electrode structure 30 stable and defining the shape of the second electrode layer 31.

[0039] The first electrode layer 11 and the second electrode layer 31 are arranged parallel to each other and facing each other, such that the projections of the first electrode layer 11 and the second electrode layer 31 on a plane parallel to the first electrode layer 11 at least partially overlap. Preferably, the first electrode layer 11 and the second electrode layer 31 have the same shape and the same cross-sectional area, such that the projections of the first electrode layer 11 and the second electrode layer 31 on a plane parallel to the first electrode layer 11 completely overlap.

[0040] The dielectric layer 20 includes a first portion 21 and a second portion 22, the second portion 22 being disposed around the outside of the first portion 21, and the first portion 21 being located between the first electrode layer 11 and the second electrode layer 31; on the side of the first electrode layer 11, the first insulating layer 12 covers the second portion 22, and on the inside side of the second electrode layer 31, the second insulating layer 32 covers the second portion 22. The projections of the first portion 21, the first electrode layer 11, and the second electrode layer 31 onto the plane parallel to the first electrode layer 11 all overlap, such that the first portion 21, the first electrode layer 11, and the second electrode layer 31 have the same shape and the same cross-sectional area.

[0041] In this embodiment, both the first electrode layer 11 and the second electrode layer 31 are circular. The shape of the first portion 21 is the same as that of the first electrode layer 11, for example, it is also circular. The shape of the dielectric layer 20 may be the same as or different from that of the first electrode layer 11 and the second electrode layer 31. Preferably, the shape of the dielectric layer 20 is the same as that of the first electrode layer 11 and the second electrode layer 31, for example, it is also circular, so that the second portion 22 is annular.

[0042] Both the first electrode layer 11 and the second electrode layer 31 can be conductive layers, specifically, for example, polycrystalline silicon material layers. The etching selectivity of both the first insulating layer 12 and the second insulating layer 32 is much greater than that of the dielectric layer 20. Specifically, both the first insulating layer 12 and the second insulating layer 32 can be silicon nitride material layers. The dielectric layer 20 and the sacrificial layer can both be silicon oxide material layers. The thickness of both the first insulating layer 12 and the second insulating layer 32 in the first portion is relatively small, so that the first insulating layer 12 and the second insulating layer 32 have almost no capacitance affecting the test structure.

[0043] A plurality of release holes 33 are formed in the first insulating layer 12. All the release holes 33 are spaced apart in the second portion 22 and surround the outside of the first portion 21. Preferably, all the release holes 33 are equally spaced on the outside of the first portion. The release holes 33 can expose the surface of the second portion 22 facing the first electrode structure 10. The shape of the release holes 33 can be set according to requirements, for example, a regular shape (circular, square, polygonal, etc.). The diameter of the release hole 33 is larger than the distance between two adjacent release holes 33, so that in the sacrificial layer release cavity structure process, when the etching liquid or etching gas enters the dielectric layer 20 through the release holes 33 to etch and form sidewalls, the dielectric layer 20 between two adjacent release holes 33 can be connected.

[0044] The test structure further includes a first test pad 41 and a second test pad 42. The first test pad 41 is connected to the first electrode layer 11, and the second test pad 42 is connected to the second electrode layer 31, so as to perform electrical testing on the test structure through the first test pad 41 and the second test pad 42 to obtain the capacitance of the test structure.

[0045] Figure 3 This is a flowchart illustrating the testing method for the test structure provided in this embodiment. Figure 3 As shown, this embodiment also provides a test method for a test structure, which can be used to measure the sacrificial layer side cut-out distance of a semiconductor device during a sacrificial layer release cavity structure process. The semiconductor device includes, but is not limited to, MEMS devices.

[0046] The testing method for the test structure includes the following steps:

[0047] Step S1: Form the test structure on the semiconductor substrate;

[0048] Step S2: The testing machine automatically measures the first capacitance between the first electrode layer and the second electrode layer, and obtains the height of the dielectric layer between the first electrode layer and the second electrode layer through the first capacitance.

[0049] Step S3: Perform a sacrificial layer release cavity structure process to etch the dielectric layer from the release hole and expose the semiconductor substrate. At this time, a side hole is formed in the dielectric layer.

[0050] Step S4: The testing machine automatically measures the second capacitance between the first electrode layer and the second electrode layer, and obtains the side-cut distance of the side cut through the second capacitance and the height.

[0051] The following combination Figures 1-2 , Figures 4-6 The testing method for a test structure provided in this embodiment will be described in detail.

[0052] like Figure 1 and Figure 2 As shown, step S1 is first performed to form the test structure on the semiconductor substrate.

[0053] In this step, the semiconductor substrate can be a processed substrate, meaning that other devices and other structural layers may be formed in the semiconductor substrate.

[0054] A sacrificial layer (not shown in the figure) and a third insulating layer (not shown in the figure) and a fourth insulating layer (not shown in the figure) located on both sides of the sacrificial layer are also formed on the semiconductor substrate. The third insulating layer is located above the sacrificial layer, and a via (not shown in the figure) is formed in the third insulating layer, exposing the sacrificial layer. The sacrificial layer and the dielectric layer 20 can be disposed in the same layer or in different layers. In the subsequent sacrificial layer release cavity structure process, the sacrificial layer can be etched at the via, and the dielectric layer 20 can be etched at the release hole 33.

[0055] Figure 4 This is a simplified structural diagram of the test structure provided in this embodiment before the process of releasing the cavity structure in the sacrificial layer. Figure 4 As shown, step S2 is then executed, where the testing machine automatically measures the first capacitance C1 between the first electrode layer 11 and the second electrode layer 12, and obtains the height of the dielectric layer 20 located between the first electrode layer 11 and the second electrode layer 12, i.e., the height d of the first portion 21, through the first capacitance C1.

[0056] This step specifically includes: First, at the first test pad 41 and the second test pad 42, the test machine automatically measures the first capacitance C1 between the first electrode layer 11 and the second electrode layer 12.

[0057] Next, based on the first capacitor C1, the height of the dielectric layer 20 between the first electrode layer 11 and the second electrode layer 12 is calculated.

[0058] The formula for calculating the first capacitor C1 is as follows:

[0059] C1=εS1 / d;

[0060] Wherein, S1 is the cross-sectional area of ​​the dielectric layer directly opposite the first electrode layer 11 and the second electrode layer 31, and d is the distance between the first electrode layer 11 and the second electrode layer 31, that is, the height of the first part 21.

[0061] Since the cross-sectional area S1 of the dielectric layer opposite to the first electrode layer 11 and the second electrode layer 31 is known, the distance d between the first electrode layer 11 and the second electrode layer 31 can be calculated given the first capacitor C1 and the cross-sectional area S1 of the dielectric layer.

[0062] In this step, since MEMS devices have a fully automated electrical testing process in the automated manufacturing process, the capacitance measurement of the test structure can be incorporated into the fully automated electrical testing process. This allows the measurement of the side distance of the sacrificial layer release cavity structure to be completed by the fully automated testing machine, which helps to solve the manual operation of traditional optical measurement, reduces labor costs and improves measurement accuracy.

[0063] Figure 5 for Figure 1 A schematic diagram of the structure after the cavity structure is released at AA' and in the sacrificial layer. (See diagram below.) Figure 5 As shown, step S3 is then performed to execute the sacrificial layer release cavity structure process to etch the dielectric layer 20 from the release hole 33 and expose the semiconductor substrate. At this time, a side hole is formed in the dielectric layer 20.

[0064] This step specifically includes:

[0065] A sacrificial layer release cavity structure process is performed to etch the sacrificial layer at the via using an etching liquid or etching gas, exposing the semiconductor substrate beneath the sacrificial layer. Simultaneously, at the release hole 33, the dielectric layer 20 is etched using an etching liquid or etching gas, exposing the semiconductor substrate beneath the dielectric layer 20. At this time, a lateral side cutout appears in the dielectric layer 20 below the release hole 33, reducing the cross-sectional area of ​​the dielectric layer 20 in the area directly opposite the first electrode layer 11 and the second electrode layer 31.

[0066] Figure 6 This is a simplified structural diagram of the test structure provided in this embodiment after the process of releasing the cavity structure in the sacrificial layer. Figure 6As shown, step S4 is then executed, in which the testing machine automatically measures the second capacitance C2 between the first electrode layer 11 and the second electrode layer 31, and obtains the side hole distance ΔR of the side hole a through the second capacitance C2 and the height d.

[0067] This step specifically includes:

[0068] First, at the first test pad 41 and the second test pad 42, the testing machine automatically measures the second capacitance C2 between the first electrode layer 11 and the second electrode layer 31.

[0069] Next, based on the second capacitor C2 and the height d, the side cut distance ΔR of the side cut a is calculated.

[0070] The formula for calculating the second capacitor C2 is:

[0071] C2=εS2 / d;

[0072] Wherein, S2 is the cross-sectional area of ​​the dielectric layer directly opposite the first electrode layer 11 and the second electrode layer 31, and d is the distance between the first electrode layer 11 and the second electrode layer 31, that is, the height of the first part 21.

[0073] Because the side cutout a reduces the cross-sectional area of ​​the first portion 21, and the presence of the dielectric layer 20 and air in the area directly opposite the first electrode layer 11 and the second electrode layer 31 causes the second capacitor C2 to have different values ​​than the first capacitor C1. Furthermore, since the distance d between the first electrode layer 11 and the second electrode layer 31 remains constant, the cross-sectional area S2 of the dielectric layer directly opposite the first electrode layer 11 and the second electrode layer 31 can be calculated given the distance d and the second capacitor C2. Because the spacing between each release hole 33 and the first portion 21 is the same, the side cutout distance ΔR formed by the etching process on the outer periphery of the first portion 21 is approximately the same, thus allowing the side cutout distance ΔR to be obtained.

[0074] In this step, capacitance measurement is also incorporated into the fully automated electrical measurement process. This allows the measurement and calculation of the side clearance distance in the sacrificial layer release cavity structure process to be completed automatically, solving the manual operation of traditional optical measurement, reducing labor costs, improving measurement accuracy, and facilitating online monitoring of the side clearance distance during the mass production of semiconductor devices.

[0075] In summary, this invention provides a test structure and its test method. The test structure can automatically measure the sacrificial layer release cavity structure before and after the process using a testing machine. The test structure includes a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially from bottom to top. The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are arranged opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion, and a plurality of release holes are formed in the first insulating layer. All the release holes are spaced around the outside of the first portion. The test structure can automatically measure and obtain the side-cut distance of the sacrificial layer before and after the process using a testing machine, thereby improving the measurement accuracy and testing efficiency of the side-cut distance. It also solves the problem of manual operation in traditional optical measurement, greatly saving testing time and labor costs.

[0076] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

Claims

1. A test structure capable of automatic measurement using a testing machine before and after the sacrificial layer release cavity structure process, characterized in that, The test structure includes a first electrode structure, a dielectric layer, and a second electrode structure stacked sequentially from bottom to top. The first electrode structure includes a first insulating layer and a first electrode layer embedded in the first insulating layer. The dielectric layer includes a first portion and a second portion surrounding the outside of the first portion. The second electrode structure includes a second electrode layer. The first electrode layer and the second electrode layer are disposed opposite each other. The first portion is located between the first electrode layer and the second electrode layer. On the side of the first electrode layer, the first insulating layer covers the second portion, and a plurality of release holes are formed in the first insulating layer. All the release holes are spaced around the outside of the first portion.

2. The test structure as described in claim 1, characterized in that, The second electrode structure further includes a second insulating layer, in which the second electrode layer is embedded and located inside the second electrode layer, and the second insulating layer covers the second portion.

3. The test structure as described in claim 2, characterized in that, The first electrode layer and the second electrode layer are both polycrystalline silicon material layers, the first insulating layer and the second insulating layer are both silicon nitride material layers, and the dielectric layer is a silicon oxide material layer.

4. The test structure as described in claim 1, characterized in that, The first electrode layer, the first portion, and the second electrode layer have the same shape and the same cross-sectional area.

5. The test structure as described in claim 1, characterized in that, All the release holes are evenly spaced on the outer side of the first part.

6. The test structure as described in claim 1, characterized in that, The diameter of the release hole is greater than the distance between two adjacent release holes.

7. The test structure as described in claim 1, characterized in that, The test structure further includes a first test pad and a second test pad, wherein the first test pad is connected to the first electrode layer and the second test pad is connected to the second electrode layer.

8. A test method for a test structure, characterized in that, Includes the following steps: A test structure as described in any one of claims 1 to 7 is formed on a semiconductor substrate; The testing equipment automatically measures the first capacitance between the first electrode layer and the second electrode layer, and obtains the height of the dielectric layer between the first electrode layer and the second electrode layer through the first capacitance. A sacrificial layer release cavity structure process is performed to etch the dielectric layer from the release hole and expose the semiconductor substrate, during which a side hole is formed in the dielectric layer; The testing machine automatically measures the second capacitance between the first electrode layer and the second electrode layer, and obtains the side-cut distance of the side cut through the second capacitance and the height.

9. The test method for the test structure as described in claim 8, characterized in that, The method for obtaining the height of the dielectric layer between the first electrode layer and the second electrode layer is as follows: At the first test pad and the second test pad, the testing machine automatically measures the first capacitance between the first electrode layer and the second electrode layer. The height of the dielectric layer between the first electrode layer and the second electrode layer is calculated based on the first capacitance.

10. The test method for the test structure as described in claim 8, characterized in that, The method for obtaining the side-cut distance is as follows: At the first test pad and the second test pad, the testing machine automatically measures the second capacitance between the first electrode layer and the second electrode layer; The side cut distance is calculated based on the second capacitor and the height.

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