Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, the substrate comprising a first dielectric layer having a first interconnect structure formed therethrough; forming a capping layer on top of the first interconnect structure; forming a stress buffer layer on top of the first dielectric layer and the capping layer after forming the capping layer; forming a second dielectric layer on top of the stress buffer layer; forming a second interconnect structure on top of the first interconnect structure, the second interconnect structure formed through the second dielectric layer, the stress buffer layer and the capping layer, a bottom of the second interconnect structure electrically connected to a top of the first interconnect structure after forming the second dielectric layer. The stress buffer layer reduces the probability of delamination or voids between the first interconnect structure and the capping layer and the second dielectric layer, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the requirements of interconnects after the critical size reduction, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through interconnect structures. As technology nodes advance, the size of interconnect structures is becoming smaller and smaller; correspondingly, the process of forming interconnect structures is becoming more and more difficult. The formation quality of interconnect structures has a significant impact on the back end of line (BEOL) electrical performance and device reliability, and in severe cases, it can affect the normal operation of semiconductor devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first dielectric layer; a first interconnect structure located in and penetrating the first dielectric layer; a capping layer located on top of the first interconnect structure, the capping layer exposing a portion of the top of the first interconnect structure; a stress buffer layer located on top of the first dielectric layer and the capping layer; a second dielectric layer located on top of the stress buffer layer; and a second interconnect structure located on top of the first interconnect structure exposed by the capping layer, the second interconnect structure penetrating the second dielectric layer and the stress buffer layer, the bottom of the second interconnect structure being electrically connected to the top of the first interconnect structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first dielectric layer, wherein a first interconnect structure is formed in the first dielectric layer penetrating the first dielectric layer; forming a capping layer on top of the first interconnect structure; after forming the capping layer, forming a stress buffer layer on top of the first dielectric layer and the capping layer; forming a second dielectric layer on top of the stress buffer layer; and after forming the second dielectric layer, forming a second interconnect structure penetrating the second dielectric layer, the stress buffer layer, and the capping layer on top of the first interconnect structure, wherein the bottom of the second interconnect structure is electrically connected to the top of the first interconnect structure.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. After forming a capping layer on top of a first interconnect structure, a stress buffer layer is formed on top of the first dielectric layer and the capping layer. Then, a second dielectric layer is formed on top of the stress buffer layer, such that the stress buffer layer is located between the first interconnect structure, the capping layer, and the second dielectric layer. An annealing process is used in the subsequent process of forming the second dielectric layer. By forming a stress buffer layer between the first interconnect structure, the capping layer, and the second dielectric layer, the stress buffer layer can release or offset the thermal stress generated between the first interconnect structure, the capping layer, and the second dielectric layer, thereby buffering the thermal stress generated between the first interconnect structure, the capping layer, and the second dielectric layer. Correspondingly, the probability of delamination or voids appearing between the first interconnect structure, the capping layer, and the second dielectric layer is reduced, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 8 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one semiconductor structure formation method as an example.

[0013] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 A substrate is provided, the substrate including a first dielectric layer 10, a first interconnect structure 12 extending through the first dielectric layer 10 is formed therein, and a capping layer 11 is formed on top of the first interconnect structure 12.

[0015] refer to Figure 2 An etch stop layer 13 is formed on top of the second dielectric layer 10 and the cap layer 11.

[0016] refer to Figure 3 A metal interlayer dielectric layer 15 is formed on top of the etching stop layer 13.

[0017] The intermetallic dielectric layer 15 and the etch stop layer 13 constitute the second dielectric layer 30.

[0018] refer to Figure 4 A patterned hard mask layer 17 is formed on top of the inter-metal dielectric layer 15, and the inter-metal dielectric layer 15, etch stop layer 13 and cap layer 11 exposed by the hard mask layer 17 are patterned, and an interconnect opening 20 is formed on top of the first interconnect structure 12.

[0019] refer to Figure 5 A conductive material layer 21 is formed in the interconnect opening 20, and the conductive material layer 21 also covers the top of the hard mask layer 17.

[0020] refer to Figure 6 Using the top of the inter-metal dielectric layer 15 as an etching stop layer, the conductive material layer 21 above the top of the inter-metal dielectric layer 15 is planarized, and the remaining conductive material layer 21 in the interconnect opening serves as the second interconnect structure 21, which is electrically connected to the first interconnect structure 12.

[0021] Research revealed that the first interconnect structure 12 and the capping layer 11 are both metallic materials, while the second dielectric layer 30 is made of a dielectric material. The coefficients of thermal expansion of the materials of the first interconnect structure 12 and the capping layer 11 differ significantly from those of the second dielectric layer 30. During the formation of the intermetallic dielectric layer 15, an annealing process is used. Due to the significant difference in the coefficients of thermal expansion between the materials of the first interconnect structure 12 and the capping layer 11 and the second dielectric layer 30, substantial thermal stress is generated between the first interconnect structure 12 and the capping layer 11 and the second dielectric layer 30. Under this significant thermal stress, the likelihood of delamination or voids 16 (such as...) between the first interconnect structure 12 and the capping layer 11 and the second dielectric layer 30 increases. Figure 3The probability of leakage current generated in the second interconnect structure 21 (as shown in the figure) increases, thereby affecting the performance of the semiconductor structure.

[0022] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first dielectric layer, wherein a first interconnect structure is formed in the first dielectric layer penetrating the first dielectric layer; forming a capping layer on top of the first interconnect structure; after forming the capping layer, forming a stress buffer layer on top of the first dielectric layer and the capping layer; forming a second dielectric layer on top of the stress buffer layer; and after forming the second dielectric layer, forming a second interconnect structure penetrating the second dielectric layer, the stress buffer layer, and the capping layer on top of the first interconnect structure, wherein the bottom of the second interconnect structure is electrically connected to the top of the first interconnect structure.

[0023] In the formation method provided by this embodiment of the invention, after forming a capping layer on top of the first interconnect structure, a stress buffer layer is formed on top of the first dielectric layer and the capping layer, and then a second dielectric layer is formed on top of the stress buffer layer, such that the stress buffer layer is located between the first interconnect structure, the capping layer, and the second dielectric layer. In the subsequent process of forming the second dielectric layer, an annealing process is used. By forming a stress buffer layer between the first interconnect structure, the capping layer, and the second dielectric layer, the stress buffer layer can release or offset the thermal stress generated between the first interconnect structure, the capping layer, and the second dielectric layer, thereby buffering the thermal stress generated between the first interconnect structure, the capping layer, and the second dielectric layer. Correspondingly, the probability of delamination or voids appearing between the first interconnect structure, the capping layer, and the second dielectric layer is reduced, thereby improving the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 7 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0026] The semiconductor structure includes: a substrate, the substrate including a first dielectric layer 200; a first interconnect structure 202 located in and penetrating the first dielectric layer 200; a capping layer 201 located on top of the first interconnect structure 202, and the capping layer 201 exposing a portion of the top of the first interconnect structure 202; a stress buffer layer 203 located on top of the first dielectric layer 200 and the capping layer 203; a second dielectric layer 290 located on top of the stress buffer layer 203; and a second interconnect structure 212 located on the portion of the top of the first interconnect structure 202 exposed by the capping layer 201, and the second interconnect structure 212 penetrating the second dielectric layer 290, the buffer layer 203, and the capping layer 201, the bottom of the second interconnect structure 212 being electrically connected to the top of the first interconnect structure 202.

[0027] In this embodiment, by providing a stress buffer layer 203 on top of the first dielectric layer 200 and the capping layer 201, and between the first dielectric layer 200 and the second dielectric layer 290, the stress buffer layer 203 can release or offset the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290, thereby buffering the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290. Correspondingly, the probability of delamination or voids appearing between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290 is reduced, thereby improving the performance of the semiconductor structure.

[0028] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0029] In this embodiment, depending on the actual process, the substrate includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors, resistor structures, etc.

[0030] The first dielectric layer 200 is used to electrically isolate the first interconnect structure 202.

[0031] The first dielectric layer 200 is made of an insulating material, and the material of the first dielectric layer 200 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 200 is silicon oxide.

[0032] In this embodiment, the first interconnect structure 202 is used to make an electrical connection with the second interconnect structure 212.

[0033] In this embodiment, the first interconnect structure 202 is used as an example of a first interlayer metal structure (i.e., M1layer).

[0034] In other embodiments, when an interlayer metal structure is formed within the substrate, the first interconnect structure is further configured to electrically connect with the interlayer metal structure within the substrate. For example, when a first interlayer metal structure is formed within the substrate, the first interconnect structure is correspondingly a second interlayer metal structure (i.e., M2layer).

[0035] In this embodiment, the material of the first interconnect structure 202 is copper. Specifically, copper has a low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the first interconnect structure 202, thereby reducing power consumption. In other embodiments, the material of the first interconnect structure may also be ruthenium or cobalt.

[0036] When a strong current passes through the first interconnect structure 202, voids are easily generated on the top surface of the first interconnect structure 202, increasing the probability of the first interconnect structure 202 breaking. The cap layer 201 is tightly attached to the top surface of the first interconnect structure 202, reducing the probability of voids being generated on the top surface of the first interconnect structure 202.

[0037] Specifically, the capping layer 201 is located on the top surface of the first interconnect structure 202 exposed by the second interconnect structure 212.

[0038] It should be noted that the thickness of the capping layer 201 should not be too large or too small. If the thickness of the capping layer 201 is too large, due to the significant difference in the coefficients of thermal expansion between the first interconnect structure 202 and the capping layer 201, and between the capping layer 201 and the second dielectric layer 290, a large thermal stress will be generated between the first interconnect structure 202 and the capping layer 201, and between the capping layer 201 and the second dielectric layer 290 during the formation process of the second dielectric layer 290. This increases the probability of delamination or voids occurring between the first interconnect structure 202 and the capping layer 201, and between the capping layer 201 and the second dielectric layer 290. If the thickness of the capping layer 201 is too small, the adhesion between the capping layer 201 and the top surface of the first interconnect structure 202 will be poor, increasing the probability of voids forming on the top surface of the first interconnect structure 202, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the capping layer 201 is 1 nanometer to 5 nanometers.

[0039] In this embodiment, the material of the cap layer 201 is one or more of Co, Ru, W and CoW.

[0040] Specifically, on the one hand, Co, Ru, W and CoW materials have good adhesion to the second dielectric layer 290 and the first interconnect structure 202, reducing the probability of delamination or voids between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290. On the other hand, Co, Ru, W and CoW are all metallic materials, which can reduce the contact resistance between the first interconnect structure 202 and the second interconnect structure 212 and improve the electrical connection performance between the first interconnect structure 202 and the second interconnect structure 212.

[0041] In this embodiment, the thermal expansion coefficient of the stress buffer layer 203 is between the thermal expansion coefficient of the second dielectric layer 290 and the thermal expansion coefficient of the capping layer 201, and is also between the thermal expansion coefficient of the second dielectric layer 290 and the thermal expansion coefficient of the first interconnect structure 202. The stress buffer layer 203 can release or offset the thermal stress generated between the first interconnect structure 202, the capping layer 201, and the second dielectric layer 290.

[0042] In this embodiment, the coefficient of thermal expansion of the bottom material of the stress buffer layer 203 is close to that of the materials of the cap layer 201 and the first interconnect structure 202, and the coefficient of thermal expansion of the top material of the stress buffer layer 203 is close to that of the material of the second dielectric layer 290.

[0043] On the one hand, the coefficient of thermal expansion of the bottom material of the stress buffer layer 203 is close to that of the capping layer 201 and the first interconnect structure 202, that is, the coefficient of thermal expansion of the capping layer 201 and the first interconnect structure 202 is relatively close to that of the bottom material of the stress buffer layer 203, resulting in less thermal stress between the capping layer 201 and the first interconnect structure 202 and the stress buffer layer 203; on the other hand, the coefficient of thermal expansion of the top material of the stress buffer layer 203 is close to that of the second dielectric layer 290, that is, the coefficient of thermal expansion of the bottom material of the stress buffer layer 203 is relatively close to that of the capping layer 201 and the first interconnect structure 202 ... resulting in less thermal stress between the capping layer 201 and the first interconnect structure 202 and the stress buffer layer 203. The coefficient of thermal expansion of the second dielectric layer 290 material is relatively close to that of the top material of the stress buffer layer 103. Therefore, the thermal stress generated between the second dielectric layer 290 and the stress buffer layer 203 is relatively small. In summary, through the above two aspects, the stress buffer layer 203 can release or offset the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290, thereby buffering the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290.

[0044] It should be noted that the coefficient of thermal expansion of the stress buffer layer 203 material should not be too large or too small. If the coefficient of thermal expansion of the stress buffer layer 203 material is too large or too small, the buffering effect on the thermal stress generated between the first interconnect structure 202 and the capping layer 201, and the second dielectric layer 290, will easily decrease. Therefore, in this embodiment, the coefficient of thermal expansion of the stress buffer layer 203 material is between 3.0 x 10⁻⁶. -6 / K to 9.8x10 -6 Between / K.

[0045] In this embodiment, the material of the stress buffer layer 203 contains metallic and non-metallic elements, and the ratio of the atomic content of the metallic and non-metallic elements decreases linearly along the direction from the bottom to the top of the stress buffer layer 203.

[0046] The thermal expansion coefficient of the stress buffer layer 203 can be controlled by adjusting the ratio of the atomic content of metallic and non-metallic elements in the stress buffer layer 203.

[0047] Specifically, the capping layer 201 and the first interconnect structure 202 are both made of metallic elements, while the second dielectric layer 290 is made of non-metallic elements, or a mixture of metallic and non-metallic elements. The capping layer 201 and the first interconnect structure 202 are in contact with the bottom of the stress buffer layer 203, and the top of the stress buffer layer 203 is in contact with the second dielectric layer 290. To ensure that the coefficient of thermal expansion of the bottom material of the stress buffer layer 203 is close to that of the materials of the capping layer 201 and the first interconnect structure 202, and that the coefficient of thermal expansion of the top material of the stress buffer layer 203 is close to that of the material of the second dielectric layer 290, the atomic ratio of metallic to non-metallic elements at the bottom of the stress buffer layer 203 is greater than that at the top of the stress buffer layer 203 in the direction from the bottom to the top.

[0048] Meanwhile, along the direction from the bottom to the top of the stress buffer layer 203, the ratio of the atomic content of the metal element and the non-metal element decreases linearly, which makes the stress buffer layer 203 play a better role in releasing or offsetting thermal stress, thereby improving the performance of the semiconductor structure.

[0049] Therefore, in this embodiment, the stress buffer layer 203 is a single-layer film, and its coefficient of thermal expansion is adjusted by adjusting the atomic ratio of the metallic and non-metallic elements. By forming a single-layer stress buffer layer 203 and only adjusting its atomic ratio, the process steps for forming the stress buffer layer 203 are simplified.

[0050] The stress buffer layer 203 is made of one or more of AlN, Al2O3, TiO2, and ZnO2. Specifically, the stress buffer layer 203 is composed of a combination of metallic and non-metallic elements. Correspondingly, during the formation of the stress buffer layer 203, the atomic ratio of the metallic and non-metallic elements can be easily adjusted to control the coefficient of thermal expansion of the stress buffer layer 203. As an example, the stress buffer layer 203 is made of AlN. In other embodiments, the stress buffer layer may also be made of Al2O3, TiO2, and ZnO2.

[0051] It should be noted that the thickness of the stress buffer layer 203 should not be too large or too small. If the thickness of the stress buffer layer 203 is too large, it is easy to cause excessively high parasitic capacitance between the first interconnect structure 202 and the second interconnect structure 212, thereby reducing the electrical connection performance between the first interconnect structure 202 and the second interconnect structure 212. If the thickness of the stress buffer layer 203 is too small, it is easy to cause the stress buffer layer 203 to be ineffective in releasing or offsetting the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290, thereby weakening the buffering effect on the thermal stress generated between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290. Correspondingly, it increases the probability of delamination or voids appearing between the first interconnect structure 202 and the capping layer 201 and the second dielectric layer 290, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the stress buffer layer 203 is 1 nanometer to 3 nanometers.

[0052] It should also be noted that in other embodiments, by selecting multilayer films with suitable coefficients of thermal expansion and stacking the films, a stress buffer layer that meets the trend of the coefficient of thermal expansion can be obtained. That is, the stress buffer layer is a stacked structure.

[0053] The second dielectric layer 290 is used to insulate the second interconnect structures 212 from each other, and also to provide a process platform for the formation process of the second interconnect structures 212.

[0054] In this embodiment, the second dielectric layer 290 includes an etch stop layer 205 and an inter-metal dielectric layer 206, with the etch stop layer located on top of the stress buffer layer.

[0055] Specifically, in the formation process of the second interconnect structure 212, it is necessary to form an interconnect opening that penetrates the intermetallic dielectric layer 206, the etch stop layer 205, the stress buffer layer 203, and the cap layer 201. The etch stop layer 205 serves as the etch stop point for etching the intermetallic dielectric layer 206, which facilitates the simultaneous etching of the stress buffer layer 203, the etch stop layer 205, and the cap layer 201, so that the depth of the interconnect opening formed on the top of the first interconnect structure 102 is consistent.

[0056] In this embodiment, the etch stop layer 205 is made of a dielectric material. Specifically, the material of the etch stop layer 205 includes one or more of SiCN, SiOC, SiN, SiON, AlN, and Al2O3.

[0057] In this embodiment, the intermetallic dielectric layer 206 is located on top of the etch stop layer 205.

[0058] The intermetallic dielectric layer 206 is used to electrically isolate the second interconnect structure 212.

[0059] In this embodiment, the material of the intermetallic dielectric layer 206 is a dielectric material. Specifically, the material of the intermetallic dielectric layer 206 includes one or more of SiO2, SiN, SiCN, SiCHN, and SiON.

[0060] It should be noted that the thickness of the inter-metal dielectric layer 206 should not be too large or too small. If the thickness of the inter-metal dielectric layer 206 is too large, the etching difficulty of removing the inter-metal dielectric layer 206 during the formation of the second interconnect structure 212 increases; if the thickness of the inter-metal dielectric layer 206 is too small, the longitudinal dimensions of the formed second interconnect structure 212 may not meet the process requirements, affecting the electrical requirements of the second interconnect structure 212 and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the inter-metal dielectric layer 206 is 5 nanometers to 200 nanometers. For example, the thickness of the inter-metal dielectric layer 206 is 50 nanometers or 100 nanometers.

[0061] The bottom of the second interconnect structure 212 is electrically connected to the top of the first interconnect structure 202, enabling the first interconnect structure 202 to be electrically connected to other external circuits.

[0062] In this embodiment, the second interconnect structure 212 includes a first sub-interconnect structure 2121 and a second sub-interconnect structure 2122. The top of the first sub-interconnect structure 2121 is connected to the bottom of the second sub-interconnect structure 2122. The top linewidth of the first sub-interconnect structure 2121 is smaller than the bottom linewidth of the second sub-interconnect structure 2122.

[0063] It should be noted that, with the direction perpendicular to the extension direction of the second interconnect structure 212 as the lateral direction, the line width dimension refers to the lateral dimension of the first sub-interconnect structure 2121 and the second sub-interconnect structure 2122.

[0064] The material of the second interconnect structure 212 includes one or more of Cu, Co and Ru.

[0065] Specifically, Cu, Co, and Ru have good electrical conductivity and good metal filling ability. They also have low resistivity, which helps to improve the signal delay of the later RC circuit and increase the processing speed of the chip. At the same time, they also help to reduce the resistance of the second interconnect structure 212, thereby reducing power consumption.

[0066] In this embodiment, the semiconductor structure further includes a diffusion barrier layer 209 located between the second interconnect structure 212 and the second dielectric layer 290.

[0067] In the process of forming the conductive material layer 210, the diffusion barrier layer 209 is used to prevent the diffusion of the material in the conductive material layer 210.

[0068] In this embodiment, the material of the diffusion barrier layer 209 includes one or more of TiN, TaN, Ti, and Ta.

[0069] Figures 8 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention.

[0070] refer to Figure 8 A substrate is provided, the substrate including a first dielectric layer 100, wherein a first interconnect structure 102 is formed in the first dielectric layer 100 extending through the first dielectric layer 100.

[0071] The substrate is used to provide a process platform for subsequent manufacturing processes.

[0072] In this embodiment, depending on the actual process, the substrate includes a substrate and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors, resistor structures, etc.

[0073] The first dielectric layer 100 is used to electrically isolate the first interconnect structure 102.

[0074] The first dielectric layer 100 is made of an insulating material, and the material of the first dielectric layer 100 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 100 is silicon oxide.

[0075] In this embodiment, the first interconnect structure 102 is used to achieve electrical connection with the second interconnect structure to be formed.

[0076] In this embodiment, the first interconnect structure 102 is used as an example of a first interlayer metal structure (i.e., M1layer).

[0077] In other embodiments, when an interlayer metal structure is formed within the substrate, the first interconnect structure is further configured to electrically connect with the interlayer metal structure within the substrate. For example, when a first interlayer metal structure is formed within the substrate, the first interconnect structure is correspondingly a second interlayer metal structure (i.e., M2layer).

[0078] In this embodiment, the material of the first interconnect structure 102 is copper. Specifically, copper has a low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the first interconnect structure 102, thereby reducing power consumption. In other embodiments, the material of the first interconnect structure may also be tungsten or ruthenium.

[0079] refer to Figure 9 A cap layer 101 is formed on top of the first interconnect structure 102.

[0080] Specifically, when a strong current passes through the first interconnect structure 102, voids are easily generated on the top surface of the first interconnect structure 102, increasing the probability of the first interconnect structure 102 breaking.

[0081] To this end, a capping layer 101 is formed on the top of the first interconnect structure 102. The capping layer 101 is closely attached to the top surface of the first interconnect structure 102, reducing the probability of voids forming on the top surface of the first interconnect structure 102.

[0082] In this embodiment, the process of forming a capping layer 101 on top of the first interconnect structure 102 includes an area-selective-deposition (ASD) process.

[0083] In this embodiment, in the selective deposition process, the capping layer 101 is more difficult to deposit on the surface of the first dielectric layer 100 than on the surface of the first interconnect structure 102, thereby selectively forming the capping layer 101 on the top of the first interconnect structure 102.

[0084] Specifically, the selective deposition process includes: passivating the surface of the first dielectric layer 100; and after the passivation, selectively depositing a capping layer 101 on top of the first interconnect structure 102.

[0085] In this embodiment, NH3 or H2 plasma is used to passivate the surface of the first dielectric layer 100, thereby modifying the surface of the first dielectric layer 100 into dangling bonds (OH). As a result, during the formation of the capping layer 101, the dangling bonds can inhibit the reaction with the precursors used in the deposition process. In other words, the capping layer 101 is difficult to react with the precursors used in the deposition process, thereby increasing the difficulty of depositing the capping layer 101 on the surface of the passivated first dielectric layer 100.

[0086] The selective deposition process features deposition flexibility, with different deposition rates on different materials to meet the required process requirements. It can directly form the capping layer 101 at the target location without patterning (e.g., etching), thereby reducing process steps and lowering process costs.

[0087] It should be noted that the thickness of the capping layer 101 should not be too large or too small. If the thickness of the capping layer 101 is too large, since the thermal expansion coefficients of the first interconnect structure 102 and the capping layer 101 differ significantly from those of the subsequently formed second dielectric layer, large thermal stress will be generated between the first interconnect structure 102 and the capping layer 101, and between the first interconnect structure 102 and the capping layer 101, and between the first interconnect structure 102 and the second dielectric layer during the subsequent formation of the second dielectric layer. This increases the probability of delamination or voids occurring between the first interconnect structure 102 and the capping layer 101, and between the first interconnect structure 102 and the second dielectric layer. If the thickness of the capping layer 101 is too small, the adhesion between the capping layer 101 and the top surface of the first interconnect structure 101 will be poor, increasing the probability of voids occurring on the top surface of the first interconnect structure 102, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the capping layer 101 is 1 nanometer to 5 nanometers.

[0088] In this embodiment, the material of the cap layer 101 is one or more of Co, Ru, W and CoW.

[0089] Specifically, Co, Ru, W, and CoW are all metallic materials. On the one hand, Co, Ru, W, and CoW materials have good adhesion to the subsequently formed second dielectric layer and the first interconnect structure 102, reducing the probability of delamination or voids between the first interconnect structure 102, the capping layer 101, and the second dielectric layer. On the other hand, Co, Ru, W, and CoW are all metallic materials, which can reduce the contact resistance between the first interconnect structure 102 and the subsequently formed second interconnect structure, and improve the electrical connection performance between the first interconnect structure 102 and the second interconnect structure.

[0090] refer to Figure 10After the capping layer 101 is formed, a stress buffer layer 103 is formed on top of the first dielectric layer 100 and the capping layer 101.

[0091] Specifically, by forming a stress buffer layer 103 on top of the first dielectric layer 100 and the capping layer 101, the stress buffer layer 103 can release or offset the thermal stress generated between the first interconnect structure 102 and the capping layer 101 and the subsequently formed second dielectric layer, thereby buffering the thermal stress generated between the first interconnect structure 102 and the capping layer 101 and the second dielectric layer. Correspondingly, the probability of delamination or voids appearing between the first interconnect structure 102 and the capping layer 101 and the second dielectric layer is reduced, thereby improving the performance of the semiconductor structure.

[0092] In this embodiment, the thermal expansion coefficient of the stress buffer layer 103 is between the thermal expansion coefficient of the first dielectric layer 100 and the thermal expansion coefficient of the capping layer 101, and is also between the thermal expansion coefficient of the first dielectric layer 100 and the thermal expansion coefficient of the first interconnect structure 102. The stress buffer layer 103 can release or offset the thermal stress generated between the first interconnect structure 102, the capping layer 101, and the second dielectric layer.

[0093] In this embodiment, the coefficient of thermal expansion of the bottom material of the stress buffer layer 103 is close to that of the materials of the cap layer 101 and the first interconnect structure 102, and the coefficient of thermal expansion of the top material of the stress buffer layer 103 is close to that of the material of the second dielectric layer subsequently formed.

[0094] On the one hand, the coefficient of thermal expansion of the bottom material of the stress buffer layer 103 is close to that of the capping layer 101 and the first interconnect structure 102. That is, the coefficient of thermal expansion of the capping layer 101 and the first interconnect structure 102 is relatively close to that of the bottom material of the stress buffer layer 103, resulting in less thermal stress between the capping layer 101, the first interconnect structure 102, and the stress buffer layer 103. On the other hand, the coefficient of thermal expansion of the top material of the stress buffer layer 103 is close to that of the subsequently formed second dielectric layer. That is, the coefficient of thermal expansion of the second dielectric layer is relatively close to that of the top material of the stress buffer layer 103, resulting in less thermal stress between the second dielectric layer and the stress buffer layer 103. In summary, through these two aspects, the stress buffer layer 103 can release or offset the thermal stress generated between the first interconnect structure 102, the capping layer 101, and the second dielectric layer, thereby buffering the thermal stress generated between the first interconnect structure 102, the capping layer 101, and the second dielectric layer.

[0095] In this embodiment, the material of the stress buffer layer 103 contains metallic and non-metallic elements, and the ratio of the atomic content of the metallic and non-metallic elements decreases linearly along the direction from the bottom to the top of the stress buffer layer 103.

[0096] The coefficient of thermal expansion of metallic elements differs significantly from that of non-metallic elements. By adjusting the ratio of the atomic content of metallic elements to non-metallic elements in the stress buffer layer 103, the coefficient of thermal expansion of the stress buffer layer 103 can be controlled.

[0097] Specifically, the capping layer 101 and the first interconnect structure 102 are both made of metallic elements, while the material of the subsequently formed second dielectric layer is a non-metallic element, or a mixture of metallic and non-metallic elements. The capping layer 101 and the first interconnect structure 102 are in contact with the bottom of the stress buffer layer 103, and the top of the stress buffer layer 103 is in contact with the subsequently formed second dielectric layer. To ensure that the coefficient of thermal expansion of the bottom material of the stress buffer layer 103 is close to that of the materials of the capping layer 101 and the first interconnect structure 102, and that the coefficient of thermal expansion of the top material of the stress buffer layer 103 is close to that of the material of the subsequently formed second dielectric layer, the atomic ratio of metallic to non-metallic elements at the bottom of the stress buffer layer 103 is greater than that at the top of the stress buffer layer 103 in the direction from the bottom to the top of the stress buffer layer 103.

[0098] Meanwhile, along the direction from the bottom to the top of the stress buffer layer 103, the ratio of the atomic content of the metal element and the non-metal element decreases linearly, which makes the stress buffer layer 103 play a better role in releasing or offsetting thermal stress, thereby improving the performance of the semiconductor structure.

[0099] In this embodiment, the stress buffer layer 103 is formed by a deposition process. The reaction gas in the deposition process includes a first reaction gas for providing metallic elements and a second reaction gas for providing non-metallic elements. During the deposition process, the ratio of the gas flow rates of the second reaction gas and the first reaction gas increases with the deposition time.

[0100] Specifically, as described above, in the direction from the bottom to the top of the stress buffer layer 103, the ratio of the atomic content of metal elements to non-metal elements at the bottom of the stress buffer layer 103 is greater than that at the top of the stress buffer layer 103, and the ratio of the atomic content of metal elements to non-metal elements decreases linearly. Therefore, during the deposition process of forming the stress buffer layer 103, as the deposition time gradually increases, the gas flow rate of the second reactive gas used to provide non-metal elements gradually increases, while the gas flow rate of the first reactive gas used to provide metal elements gradually decreases, thereby increasing the ratio of the gas flow rates of the second reactive gas and the first reactive gas with the deposition time.

[0101] In this embodiment, the stress buffer layer 103 is formed using a chemical vapor deposition process.

[0102] Specifically, taking the formation of the stress buffer layer 103 of AlN material using chemical vapor deposition as an example, the first reactant gas is TMA, and the second reactant gas is NH3. In other embodiments, the first reactant gas may also be TDMAT, and the second reactant gas may also be O2.

[0103] In other embodiments, the stress buffer layer can also be formed using atomic layer deposition (ALD) or physical vapor deposition (PVD). It should be noted that ALD involves multiple ALD cycles, providing good step coverage, which helps improve the thickness uniformity of the stress buffer layer 103 and allows it to cover the top of the first dielectric layer 100 and the capping layer 101.

[0104] The stress buffer layer 103 is made of one or more of AlN, Al2O3, TiO2, and ZnO2. Specifically, the stress buffer layer 103 is composed of a combination of metallic and non-metallic elements. Correspondingly, during the formation of the stress buffer layer 103, the atomic ratio of the metallic and non-metallic elements can be easily adjusted to control the coefficient of thermal expansion of the stress buffer layer 103. As an example, the stress buffer layer 103 is made of AlN. In other embodiments, the stress buffer layer may also be made of Al2O3, TiO2, and ZnO2.

[0105] It should also be noted that the thickness of the stress buffer layer 103 should not be too large or too small. If the thickness of the stress buffer layer 103 is too large, it is easy to cause excessively high parasitic capacitance between the first interconnect structure 102 and the subsequently formed second interconnect structure, thereby affecting the electrical connection performance between the first interconnect structure 102 and the second interconnect structure. If the thickness of the stress buffer layer 103 is too small, it is easy to cause the stress buffer layer 103 to fail to completely release or offset the thermal stress generated between the first interconnect structure 102 and the capping layer 101 and the subsequently formed second dielectric layer, thereby weakening the buffering effect on the thermal stress generated between the first interconnect structure 102 and the capping layer 101 and the second dielectric layer. Correspondingly, it increases the probability of delamination or voids between the first interconnect structure 102 and the capping layer 101 and the second dielectric layer, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the stress buffer layer 103 is 1 nanometer to 3 nanometers.

[0106] In other embodiments, the stress buffer layer may also be composed of multiple film layers stacked together, wherein the ratio of the atomic content of metallic elements to non-metallic elements decreases linearly along the direction from the bottom to the top of the stress buffer layer.

[0107] refer to Figures 11 to 12 A second dielectric layer 190 is formed on top of the stress buffer layer 103.

[0108] The second dielectric layer 190 is used to insulate the second interconnect structures that are subsequently formed from each other, and also to provide a process platform for the subsequent formation of the second interconnect structures.

[0109] In this embodiment, the step of forming a second dielectric layer 190 on top of the stress buffer layer 103 includes: as follows Figure 11 As shown, an etching stop layer 105 is formed on top of the stress buffer layer 103; as Figure 12 As shown, an intermetallic dielectric layer 106 is formed on top of the etch stop layer 105, and the intermetallic dielectric layer 106 and the etch stop layer 105 constitute the second dielectric layer 190.

[0110] Specifically, the etching stop layer 105 serves as the etching stop point for the subsequent etching of the inter-metal dielectric layer, which facilitates the simultaneous etching of the stress buffer layer 103 and the capping layer 101, ensuring that the depth of the interconnect openings subsequently formed on the top of the first interconnect structure 102 is consistent.

[0111] In this embodiment, the etch stop layer 105 is made of a dielectric material. Specifically, the material of the etch stop layer 105 includes one or more of SiCN, SiOC, SiN, SiON, AlN, and Al2O3.

[0112] In this embodiment, the process for forming the etching stop layer 105 includes atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0113] The intermetallic dielectric layer 106 is used to electrically isolate the subsequently formed second interconnect structure.

[0114] In this embodiment, the material of the intermetallic dielectric layer 106 is a dielectric material. Specifically, the material of the intermetallic dielectric layer 106 includes one or more of SiO2, SiN, SiCN, SiCHN, and SiON.

[0115] It should be noted that the thickness of the inter-metal dielectric layer 106 should not be too large or too small. If the thickness of the inter-metal dielectric layer 106 is too large, it increases the difficulty of etching away the inter-metal dielectric layer 106 during the subsequent formation of interconnect openings. If the thickness of the inter-metal dielectric layer 106 is too small, it can easily lead to an insufficient depth of the interconnect openings formed subsequently. Consequently, the longitudinal dimensions of the second interconnect structure formed in the interconnect openings cannot meet the process requirements, affecting the electrical requirements of the second interconnect structure and thus the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the inter-metal dielectric layer 106 is 5 nanometers to 200 nanometers. For example, the thickness of the inter-metal dielectric layer 106 is 50 nanometers or 100 nanometers.

[0116] refer to Figures 13 to 17 After the second dielectric layer 190 is formed, a second interconnect structure 112 is formed on the top of the first interconnect structure 102, penetrating the second dielectric layer 190, the stress buffer layer 103 and the cap layer 101. The bottom of the second interconnect structure 112 is electrically connected to the top of the first interconnect structure 102.

[0117] Specifically, the bottom of the second interconnect structure 112 is electrically connected to the top of the first interconnect structure 102, enabling the first interconnect structure 102 to be electrically connected to other external circuits.

[0118] Reference Figures 13 to 17 The steps of forming a second interconnect structure 112 on top of the first interconnect structure 102, penetrating the second dielectric layer 190, the stress buffer layer 103, and the cap layer 101, are described in detail.

[0119] refer to Figures 13 to 14 An interconnection opening 108 is formed on the top of the first interconnection structure 102, penetrating the second dielectric layer 190, the stress buffer layer 103, and the cap layer 101.

[0120] The interconnection opening 108 provides spatial location for the formed second interconnection structure 112.

[0121] In this embodiment, the interconnection opening 108 includes a trench 1081 and a through hole 1082. The bottom of the trench 1081 and the top of the through hole 1082 are connected. The top line width of the through hole 1082 is smaller than the bottom line width of the trench 1081.

[0122] It should be noted that, with the direction perpendicular to the extension direction of the interconnect opening 108 as the lateral direction, the line width dimension refers to the top lateral dimension of the trench 1081 and the through hole 1082 with the direction perpendicular to the extension direction of the first interconnect structure 102 as the lateral direction.

[0123] In this embodiment, the interconnect opening 108 is formed by etching the second dielectric layer 190, stress buffer layer 103, etching stop layer 105 and capping layer 101 using a dual damascene process.

[0124] In this embodiment, a patterned hard mask layer 107 is formed on top of the intermetallic dielectric layer 106 before the interconnect opening 108 is formed.

[0125] The hard mask layer 107 serves as an etching mask during the patterning of the second dielectric layer 190, the stress buffer layer 103, and the cap layer 101.

[0126] In this embodiment, the material of the hard mask layer 107 includes one or more of TiN, WC, Al2O3, SiO2, SiN, SiOC, and SiON, that is, the hard mask layer 107 can be a single-layer structure or a stacked structure. As an example, the material of the hard mask layer 107 is TiN, that is, the hard mask layer 107 is a single-layer TiN layer.

[0127] Specifically, a hard mask layer 107 is formed on the intermetallic dielectric layer 106 using a physical vapor deposition process.

[0128] refer to Figures 15 to 16 A conductive material layer 110 is formed in the interconnection opening 108, and the conductive material layer 110 also covers the top of the second dielectric layer 190.

[0129] Specifically, the conductive material layer 110 provides the technological basis for the formed second interconnect structure 112.

[0130] In this embodiment, the material of the conductive material layer 110 includes one or more of Co, Ru, and Cu.

[0131] Specifically, Co, Ru, and Cu have good electrical conductivity and good metal filling ability, and low resistivity, which helps to improve the signal delay of the later RC circuit and increase the processing speed of the chip. At the same time, they also help to reduce the resistance of the second interconnect structure 112, thereby reducing power consumption.

[0132] In this embodiment, the process for forming the conductive material layer 110 includes chemical vapor deposition or physical vapor deposition.

[0133] refer to Figure 15 Before forming the conductive material layer 110, the method further includes forming a diffusion barrier layer 109 at the bottom and sidewalls of the interconnect opening 108 and at the top of the hard mask layer 107.

[0134] Specifically, during the formation of the conductive material layer 110, the diffusion barrier layer 109 is used to prevent the diffusion of material in the conductive material layer 110.

[0135] In this embodiment, the diffusion barrier layer 109 is formed using physical vapor deposition or atomic layer deposition.

[0136] In this embodiment, the material of the diffusion barrier layer 109 includes one or more of TiN, TaN, Ti, and Ta.

[0137] refer to Figure 17 Using the top of the second dielectric layer 190 as the stopping position, the conductive material layer 110 above the top of the second dielectric layer 190 is planarized, and the remaining conductive material layer 110 in the interconnect opening 108 serves as the second interconnect structure 112.

[0138] Specifically, the conductive material layer 110 above the top of the second dielectric layer 190 is planarized to make the top of the second interconnect structure 112 and the second dielectric layer 190 have a high degree of flatness, which provides a better process foundation for subsequent formation processes.

[0139] In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material layer 110 above the top of the second dielectric layer 190.

[0140] It should be noted that the planarization process of the conductive material layer 110 above the top of the second dielectric layer 190 also includes: removing the diffusion barrier layer 109 above the top of the second dielectric layer 190.

[0141] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first dielectric layer; A first interconnect structure is located in the first dielectric layer and extends through the first dielectric layer; A capping layer is located on top of the first interconnect structure, and the capping layer exposes a portion of the top of the first interconnect structure and is tightly attached to the top surface of the first interconnect structure; A stress buffer layer is located on top of the first dielectric layer and the capping layer; wherein the material of the stress buffer layer contains metallic and non-metallic elements, and the atomic ratio of the metallic and non-metallic elements decreases linearly along the direction from the bottom to the top of the stress buffer layer. The second dielectric layer is located on top of the stress buffer layer; The second interconnect structure is located on top of the portion of the first interconnect structure exposed by the cap layer, and the second interconnect structure extends through the second dielectric layer and the buffer layer, with the bottom of the second interconnect structure electrically connected to the top of the first interconnect structure.

2. The semiconductor structure as described in claim 1, characterized in that, The second dielectric layer includes an etch stop layer and an inter-metal dielectric layer located on top of the etch stop layer.

3. The semiconductor structure as described in claim 1, characterized in that, The second interconnect structure includes a first sub-interconnect structure and a second sub-interconnect structure. The top of the first sub-interconnect structure is connected to the bottom of the second sub-interconnect structure, and the top linewidth of the first sub-interconnect structure is smaller than the bottom linewidth of the second sub-interconnect structure.

4. The semiconductor structure as described in claim 1, characterized in that, The thermal expansion coefficient of the stress buffer layer is between that of the second dielectric layer and the capping layer, and also between that of the second dielectric layer and the first interconnect structure.

5. The semiconductor structure as described in claim 1, characterized in that, The coefficient of thermal expansion of the bottom material of the stress buffer layer is closer to that of the cap layer and the first interconnect structure material, and the coefficient of thermal expansion of the top material of the stress buffer layer is closer to that of the first dielectric layer material.

6. The semiconductor structure as described in claim 1, characterized in that, The coefficient of thermal expansion of the stress buffer layer material is between 3.0 x 10⁻⁶ / K and 9.8 x 10⁻⁶ / K.

7. The semiconductor structure as described in claim 1, characterized in that, The stress buffer layer is made of one or more of AlN, Al2O3, TiO2, and ZnO2.

8. The semiconductor structure as described in claim 1, characterized in that, The thickness of the stress buffer layer is 1 nanometer to 3 nanometers.

9. The semiconductor structure as described in claim 2, characterized in that, The material of the etching stop layer includes one or more of SiCN, SiOC, SiN, SiON, AlN, and Al2O3; the material of the second dielectric layer includes one or more of SiO2, SiN, SiCHN, SiCN, and SiON.

10. The semiconductor structure as claimed in claim 1, characterized in that, The material of the first interconnect structure includes one or more of Cu, Co, and Ru.

11. The semiconductor structure as claimed in claim 1, characterized in that, The material of the capping layer includes one or more of Co, Ru, CoW, and W.

12. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first dielectric layer, wherein a first interconnect structure is formed in the first dielectric layer extending through the first dielectric layer; A capping layer is formed on top of the first interconnect structure; After the capping layer is formed, a stress buffer layer is formed on top of the first dielectric layer and the capping layer. The stress buffer layer contains metallic and non-metallic elements in its material, and the ratio of the atomic content of the metallic and non-metallic elements decreases linearly along the direction from the bottom to the top of the stress buffer layer. A second dielectric layer is formed on top of the stress buffer layer; After the second dielectric layer is formed, a second interconnect structure is formed on top of the first interconnect structure, penetrating the second dielectric layer, the stress buffer layer, and the capping layer. The bottom of the second interconnect structure is electrically connected to the top of the first interconnect structure.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The thermal expansion coefficient of the stress buffer layer is between that of the second dielectric layer and the capping layer, and also between that of the second dielectric layer and the first interconnect structure.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The coefficient of thermal expansion of the bottom material of the stress buffer layer is closer to that of the cap layer and the first interconnect structure material, and the coefficient of thermal expansion of the top material of the stress buffer layer is closer to that of the second dielectric layer material.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The stress buffer layer is formed by a deposition process, wherein the reaction gas in the deposition process includes a first reaction gas for providing metallic elements and a second reaction gas for providing non-metallic elements, and during the deposition process, the ratio of the gas flow rates of the second reaction gas and the first reaction gas increases with the deposition time.

16. The method for forming a semiconductor structure as described in claim 12 or 15, characterized in that, The stress buffer layer is formed using atomic layer deposition or chemical vapor deposition.

17. The method for forming a semiconductor structure as described in claim 12, characterized in that, The step of forming a second dielectric layer on top of the stress buffer layer includes: forming an etch stop layer on top of the stress buffer layer; forming an intermetallic dielectric layer on top of the etch stop layer, wherein the intermetallic dielectric layer and the etch stop layer constitute the second dielectric layer.

18. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process of forming a capping layer on top of the first interconnect structure includes a selective deposition process.

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