A power integration device embedded with three-dimensional stacked Trench MOS

Abstract

The present invention discloses a power integrated device embedded with a three-dimensional stacked TrenchMOS, belonging to the field of semiconductor power devices, which includes a half-bridge structure unit, an independent VDMOS unit, and a control unit integrated on the same chip; the half-bridge structure unit is located on the right side of the chip and has an up-and-down structure, including two vertical VDMOS devices; the independent VDMOS unit is arranged at the lower left of the chip; the control unit is located at the upper left of the chip. By integrating the control unit, the half-bridge structure unit, and the independent VDMOS unit on one chip, compared with using discrete devices to form a circuit, it is beneficial to reduce the circuit area and improve the chip integration degree; the control unit can be designed according to the actual requirements of the chip, and while improving the chip integration degree, the integrated device can be accurately applied.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and particularly to a power integrated device embedded with a three-dimensional stacked Trench MOS. Background Art

[0002] For more than 40 years, semiconductor technology has continuously reduced the chip feature size along the route of Moore's Law. However, current semiconductor technology has reached a bottleneck; as the line width becomes smaller and smaller, the manufacturing cost increases exponentially, and as the line width approaches the nanoscale, quantum effects become more and more obvious, and at the same time, the leakage current of the chip also becomes larger and larger. Therefore, the development of semiconductor technology must consider the problems in the "post-Moore era". Power semiconductor devices and power integration technology play a very important role in "beyond Moore's Law", mainly used in power processing circuits such as frequency conversion, voltage conversion, current conversion, power amplification, and power management in modern electronic systems, and are also one of the key technologies in fields such as consumer electronics, industrial control, and national defense equipment today.

[0003] A power integrated circuit refers to an integrated circuit that integrates high-voltage power devices, control circuits, peripheral interface circuits, and protection circuits on the same chip, and is a bridge between the system signal processing part and the execution part. The rapid progress of the electronics industry has put forward higher and higher requirements for power integration, and the compounding, modularization, and power integration of power electronic devices have gradually become the mainstream demands of the industry.

[0004] Single-chip integrated semiconductor power circuits have always been a research hotspot in the power electronics field. In the prior art, JFET devices, CMOS devices, and DMOS devices are usually used separately to construct power circuits, so the number of components, interconnections, and solder joints in the system is large, resulting in poor system reliability, high power consumption, high cost, large volume, and large weight, and unable to meet the development trend of lightweight and integration in the electronics industry. Therefore, the reduction of the area and the improvement of the performance of single-chip integrated devices have received more and more attention. Summary of the Invention

[0005] The purpose of the present invention is to provide a power integrated device embedded with a three-dimensional stacked Trench MOS to solve the problems of large circuit area and poor integration degree caused by the use of discrete devices at present.

[0006] To solve the above technical problems, the present invention provides a power integrated device embedded with a three-dimensional stacked Trench MOS, including a half-bridge structure unit, an independent VDMOS unit, and a control unit integrated on the same chip;

[0007] The half-bridge structure unit is located on the right side of the chip and has an up-and-down structure, including two vertical VDMOS devices, the upper and the lower; the independent VDMOS unit is disposed at the lower left of the chip; the control unit is located at the upper left of the chip; wherein,

[0008] The half-bridge structure unit includes an N-type substrate, a first N-type lightly doped drift region, a first P-type lightly doped base region, a first N-type heavily doped source / drain region, a second N-type lightly doped drift region, and a second P-type lightly doped base region, which are stacked in sequence from bottom to top; a first P-type heavily doped base region is disposed on the right side of the half-bridge structure unit; a second N-type heavily doped source / drain region and a second P-type heavily doped base region are arranged in parallel in the second P-type lightly doped base region;

[0009] The independent VDMOS unit includes an N-type substrate, a first N-type lightly doped drift region, a third P-type lightly doped base region, and a third N-type heavily doped source / drain region, which are stacked from bottom to top; a third P-type heavily doped base region is disposed on the left side of the independent VDMOS unit;

[0010] The control unit is located in a fourth N-type lightly doped drift region, and the third P-type heavily doped base region is located on the left side of the fourth N-type lightly doped drift region;

[0011] A first trench gate and a second trench gate are disposed between the right sides of the independent VDMOS unit and the control unit and the left side of the half-bridge structure unit.

[0012] In one embodiment, both the first trench gate and the second trench gate are wrapped by silicon dioxide, and the connection points of the two are at the same height as the upper boundaries of the first N-type heavily doped source / drain region and the third N-type heavily doped source / drain region;

[0013] The bottom of the first trench gate is located in the first N-type lightly doped drift region, in contact with the third P-type lightly doped base region and the third N-type heavily doped source / drain region on the left side, and in contact with the first P-type lightly doped base region and the first N-type heavily doped source / drain region on the right side;

[0014] The left side of the second trench gate is in contact with the fourth N-type lightly doped drift region, and the right side is in contact with the second N-type lightly doped drift region, the second P-type lightly doped base region, and the second N-type heavily doped source / drain region.

[0015] In one embodiment, the first P-type heavily doped base region is located on the first P-type lightly doped base region and is in contact with the first N-type heavily doped source / drain region and the second N-type lightly doped drift region on the side; the third P-type heavily doped base region is located on the third P-type lightly doped base region and is in contact with the fourth N-type lightly doped drift region and the third N-type heavily doped source / drain region on the side.

[0016] In one embodiment, in the half-bridge structure unit, the channel lengths of the two longitudinal VDMOS devices are equal.

[0017] In one embodiment, in the half-bridge structure unit, the lower longitudinal VDMOS device shares the first trench gate with the independent VDMOS unit.

[0018] In one embodiment, the first trench gate is a split trench gate, and its electrode is wrapped with silicon dioxide and led out through the inside of the second trench gate.

[0019] In one embodiment, in the half-bridge structure unit, the source of the lower longitudinal VDMOS device and the drain of the upper longitudinal VDMOS device share the first N-type heavily doped source / drain region to form a totem pole structure.

[0020] In one embodiment, in the half-bridge structure unit, the source of the lower longitudinal VDMOS device, that is, the drain of the upper longitudinal VDMOS device, is led out to the surface by etching or epitaxy.

[0021] In one embodiment, the first P-type heavily doped base region serves as the body electrode of the lower longitudinal VDMOS device in the half-bridge structure unit and is led out to the surface by etching or epitaxy.

[0022] A power integration device embedding a three-dimensional stacked TrenchMOS provided by the present invention has the following beneficial effects:

[0023] (1) Integrating the control unit, the half-bridge structure unit, and the independent VDMOS unit on one chip is beneficial to reducing the circuit area and improving the chip integration degree compared with using discrete devices to form a circuit;

[0024] (2) The drain of the three-dimensional trench gate VDMOS is led out from the surface, changing the situation that the drain of the planar VDMOS is led out from the back, and it is easier to be compatible with the integrated circuit process;

[0025] (3) The half-bridge structure of the present invention is a totem pole structure, including two trench gate VDMOS structures, each with an independent gate, and two gates can drive two devices respectively, and the devices can work independently;

[0026] (4) The control unit can be designed according to the actual requirements of the chip. While improving the chip integration degree, the integrated device can be accurately applied. Description of the Drawings

[0027] Figure 1 is a schematic cross-sectional structure diagram of the lateral two-dimensional profile of a power integration device embedding a three-dimensional stacked TrenchMOS provided by the present invention.

[0028] Figure 2 It is a schematic diagram of the longitudinal two-dimensional cross-sectional structure at the trench of a power integration device with embedded three-dimensional stacked TrenchMOS provided by the present invention.

[0029] Figure 3 It is a schematic diagram of another implementation manner of a power integration device with embedded three-dimensional stacked TrenchMOS. Detailed implementation manners

[0030] The following further describes in detail a power integration device with embedded three-dimensional stacked Trench MOS proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0031] The present invention provides a power integration device with embedded three-dimensional stacked TrenchMOS, and its transverse two-dimensional cross-section is as Figure 1 shown, including a half-bridge structure unit 101, an independent VDMOS unit 102, and a control unit 103 integrated on the same chip (i.e., the power integration device); wherein the half-bridge structure unit 101 is located on the right side of the chip, and is an up-and-down structure, including two longitudinal VDMOS devices up and down, and the channel lengths of both are equal; the independent VDMOS unit 102 is disposed at the lower left of the chip; the control unit 103 is located at the upper left of the chip.

[0032] Please continue to refer to Figure 1 , the half-bridge structure unit 101 includes an N-type substrate 1, a first N-type lightly doped drift region 4, a first P-type lightly doped base region 5, a first N-type heavily doped source / drain region 6, a second N-type lightly doped drift region 7, and a second P-type lightly doped base region 8 stacked in sequence from bottom to top; a first P-type heavily doped base region 9 is disposed on the right side of the half-bridge structure unit 101; a second N-type heavily doped source / drain region 11 and a second P-type heavily doped base region 10 are arranged in parallel in the second P-type lightly doped base region 8. The independent VDMOS unit 102 includes an N-type substrate 1, a first N-type lightly doped drift region 4, a third P-type lightly doped base region 15, and a third N-type heavily doped source / drain region 16 stacked from bottom to top; a third P-type heavily doped base region 12 is disposed on the left side of the independent VDMOS unit 102. The control unit 103 is located in a fourth N-type lightly doped drift region 13, and the third P-type heavily doped base region 12 is located on the left side of the fourth N-type lightly doped drift region 13. A first trench gate 2 and a second trench gate 3 are disposed between the right sides of the independent VDMOS unit 102 and the control unit 103 and the left side of the half-bridge structure unit 101.

[0033] The first trench gate 2 and the second trench gate 3 are both wrapped by silicon dioxide 17, and the connection points of the two are at the same height as the upper boundaries of the first N-type heavily doped source / drain region 6 and the third N-type heavily doped source / drain region 16; the bottom of the first trench gate 2 is located in the first N-type lightly doped drift region 4, and the left side contacts the third P-type lightly doped base region 15 and the third N-type heavily doped source / drain region 16, and the right side contacts the first P-type lightly doped base region 5 and the first N-type heavily doped source / drain region 6; the left side of the second trench gate 3 contacts the fourth N-type lightly doped drift region 13, and the right side contacts the second N-type lightly doped drift region 7, the second P-type lightly doped base region 8 and the second N-type heavily doped source / drain region 11.

[0034] The first P-type heavily doped base region 9 is located on the first P-type lightly doped base region 5, and the side contacts the first N-type heavily doped source / drain region 6 and the second N-type lightly doped drift region 7; the third P-type heavily doped base region 12 is located on the third P-type lightly doped base region 15, and the side contacts the fourth N-type lightly doped drift region 13 and the third N-type heavily doped source / drain region 16.

[0035] In the half-bridge structure unit 101, the lower longitudinal VDMOS device shares the first trench gate 2 with the independent VDMOS unit 102. As Figure 2 shown, the first trench gate 2 is a split trench gate, and its electrode is wrapped by silicon dioxide 17 and led out through the inside of the second trench gate 3. In the half-bridge structure unit 101, the source electrode of the lower longitudinal VDMOS device and the drain electrode of the upper longitudinal VDMOS device share the first N-type heavily doped source / drain region 6 to form a totem pole structure; and the source electrode of the lower longitudinal VDMOS device, that is, the drain electrode of the upper longitudinal VDMOS device, is led out to the surface by means of etching or epitaxy. In the half-bridge structure unit 101, the body electrode (i.e., the first P-type heavily doped base region 9) of the lower longitudinal VDMOS device is led out to the surface by means of etching or epitaxy.

[0036] The control unit 103 is located in the fourth N-type lightly doped drift region 13 and can be designed according to the chip requirements. In Figure 3 an embodiment shown, the control unit 103 is a CMOS, i.e., complementary metal oxide semiconductor, which is composed of a PMOS transistor and an NMOS transistor. In the fourth N-type lightly doped drift region 13, a P-well region and an N-well region are sequentially formed, and then a field oxide layer and a gate oxide layer are grown, and an NMOS gate and a PMOS gate are formed on the gate oxide layer, and an N+ region and a P+ region are formed.

[0037] Since the first trench gate 2 is led to the surface through the inside of the second trench gate 3, the power integrated device of the present invention is a three-dimensional structure.

[0038] In the description of the present invention, it should be understood that the directions or positional relationships indicated by terms such as "horizontal", "vertical", "lateral", "longitudinal", "left", "right", "width", "depth", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0039] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A power integrated device embedded with a three-dimensional stacked TrenchMOS, characterized in that, It includes a half-bridge structure unit (101), an independent VDMOS unit (102), and a control unit (103) integrated on the same chip; The half-bridge structure unit (101) is located on the right side of the chip, with an up-and-down structure, including two vertical VDMOS devices; the independent VDMOS unit (102) is arranged at the lower left of the chip; the control unit (103) is located at the upper left of the chip; among them, The half-bridge structure unit (101) includes an N-type substrate (1), a first N-type lightly doped drift region (4), a first P-type lightly doped base region (5), a first N-type heavily doped source / drain region (6), a second N-type lightly doped drift region (7), and a second P-type lightly doped base region (8) stacked in sequence from bottom to top; a first P-type heavily doped base region (9) is arranged on the right side of the half-bridge structure unit (101); a second N-type heavily doped source / drain region (11) and a second P-type heavily doped base region (10) are arranged in parallel in the second P-type lightly doped base region (8); The independent VDMOS unit (102) includes an N-type substrate (1), a first N-type lightly doped drift region (4), a third P-type lightly doped base region (15), and a third N-type heavily doped source / drain region (16) stacked from bottom to top; a third P-type heavily doped base region (12) is arranged on the left side of the independent VDMOS unit (102); The control unit (103) is located in a fourth N-type lightly doped drift region (13), and the third P-type heavily doped base region (12) is located on the left side of the fourth N-type lightly doped drift region (13); A first trench gate (2) and a second trench gate (3) are arranged between the right sides of the independent VDMOS unit (102) and the control unit (103) and the left side of the half-bridge structure unit (101).

2. The power integration device embedded with a three-dimensional stacked TrenchMOS as claimed in claim 1, wherein Both the first trench gate (2) and the second trench gate (3) are wrapped by silicon dioxide (17), and the connection points of the two are at the same height as the upper boundaries of the first N-type heavily doped source / drain region (6) and the third N-type heavily doped source / drain region (16); The bottom of the first trench gate (2) is located in the first N-type lightly doped drift region (4), the left side is in contact with the third P-type lightly doped base region (15) and the third N-type heavily doped source / drain region (16), and the right side is in contact with the first P-type lightly doped base region (5) and the first N-type heavily doped source / drain region (6); The left side of the second trench gate (3) is in contact with the fourth N-type lightly doped drift region (13), and the right side is in contact with the second N-type lightly doped drift region (7), the second P-type lightly doped base region (8), and the second N-type heavily doped source / drain region (11).

3. The power integration device with embedded three-dimensional stacked TrenchMOS as described in claim 1, characterized in that, The first P-type heavily doped base region (9) is located on the first P-type lightly doped base region (5), and the side is in contact with the first N-type heavily doped source / drain region (6) and the second N-type lightly doped drift region (7); The third P-type heavily doped base region (12) is located on the third P-type lightly doped base region (15), and is in contact with the fourth N-type lightly doped drift region (13) and the third N-type heavily doped source / drain region (16) on the side.

4. The power integration device with embedded three-dimensional stacked TrenchMOS as claimed in claim 1, wherein, In the half-bridge structure unit (101), the channel lengths of the two vertical VDMOS devices are equal.

5. The power integration device embedded with a three-dimensional stacked TrenchMOS as claimed in claim 1, wherein In the half-bridge structure unit (101), the lower vertical VDMOS device shares the first trench gate (2) with the independent VDMOS unit (102).

6. The power integration device with embedded three-dimensional stacked TrenchMOS as described in claim 1, characterized in that, The first trench gate (2) is a split trench gate, and its electrode is wrapped with silicon dioxide (17) and led out through the inside of the second trench gate (3).

7. The power integration device embedded with three-dimensional stacked TrenchMOS as claimed in claim 1, wherein In the half-bridge structure unit (101), the source electrode of the lower vertical VDMOS device and the drain electrode of the upper vertical VDMOS device share the first N-type heavily doped source / drain region (6) to form a totem pole structure.

8. The power integration device with embedded three-dimensional stacked TrenchMOS according to claim 7, wherein In the half-bridge structure unit (101), the source electrode of the lower vertical VDMOS device, that is, the drain electrode of the upper vertical VDMOS device, is led out to the surface by etching or epitaxy.

9. The power integration device embedded with three-dimensional stacked TrenchMOS as claimed in claim 1, wherein The first P-type heavily doped base region (9) serves as the body electrode of the lower vertical VDMOS device in the half-bridge structure unit (101), and is led out to the surface by etching or epitaxy.

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