Semiconductor structure and its fabrication process

Abstract

This invention discloses a semiconductor structure and its fabrication process. The semiconductor structure includes a substrate, a thin-film transistor (TFT) on the substrate, the TFT including a TFT channel layer, a first source and a first drain in the TFT channel layer, a first capping layer on the TFT channel layer, a metal-oxide-semiconductor field-effect transistor (MOSFET) on the substrate, a second gate, a second source and a second drain on both sides of the second gate, and a second capping layer on the second gate, wherein the second capping layer is at the same height as the top surface of the first capping layer, and a first interlayer dielectric layer is located on the first capping layer and the second capping layer, wherein the first interlayer dielectric layer and the first capping layer together serve as the gate dielectric layer of the TFT.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its fabrication method, and more particularly to a semiconductor structure and its fabrication method (fabrication process) integrated with a complementary metal-oxide-semiconductor (CMOS) fabrication process. Background Technology

[0002] With the rapid and continuous evolution of thin-film transistor (TFT) technology over the past few years, TFT display panels have been developed for applications beyond screens, such as flexible electronics, biomedical sensors, non-volatile memory, and 3D chips. Among these, the booming development of industries such as automotive electronics, wireless communication devices, and data processing in recent years has led to a mainstream focus on using TFTs as power ICs in these innovative applications, resulting in a continuously growing market demand for high-power, high-frequency, and high-speed transistor components. Against this backdrop, integrating TFT components with traditional metal-oxide-semiconductor (CMOS) logic fabrication processes to simplify the overall manufacturing process and reduce costs has become a pressing research and development challenge for those skilled in the art. Summary of the Invention

[0003] Based on the aforementioned market demands, this invention proposes a novel semiconductor structure and its fabrication method (process), characterized by integrating the fabrication of high-voltage thin-film transistor (TFT) devices into the CMOS logic front-end fabrication process (FEOL), which significantly reduces the overall fabrication process steps and lowers manufacturing costs. Furthermore, the active region of the TFT device is defined before the formation of the well region of the CMOS logic device, allowing for effective control of the overall thermal budget.

[0004] One aspect of the present invention is to provide a semiconductor structure comprising a substrate, a thin-film transistor (TFT) located on the substrate, the TFT including a TFT channel layer, a first source and a first drain located in the TFT channel layer and a first capping layer located on the TFT channel layer, a metal-oxide-semiconductor field-effect transistor (MOSFET) located on the substrate, the TFT including a second gate, a second source and a second drain located on both sides of the second gate and a second capping layer located on the second gate, wherein the second capping layer is at the same height as the top surface of the first capping layer, and a first interlayer dielectric layer located on the first capping layer and the second capping layer, wherein the first interlayer dielectric layer and the first capping layer together serve as the gate dielectric layer of the TFT.

[0005] Another aspect of the present invention is to provide a semiconductor fabrication process comprising the steps of forming a thin-film transistor channel layer on a substrate, and after the thin-film transistor channel layer is formed, fabricating a metal-oxide-semiconductor field-effect transistor on the substrate, the metal-oxide-semiconductor field-effect transistor comprising a first gate, a first source, and a first drain, after the metal-oxide-semiconductor field-effect transistor is fabricated, forming a second source and a second drain on the thin-film transistor channel layer, and after the second source and the second drain are formed, forming a first interlayer dielectric layer on the thin-film transistor channel layer and the metal-oxide-semiconductor field-effect transistor, and forming a second gate on the first interlayer dielectric layer, the second gate, the thin-film transistor channel layer, the second source, and the second drain constituting a thin-film transistor.

[0006] These and other objects of the present invention should become more apparent to the reader upon reading the detailed description of the preferred embodiments, which are illustrated in various accompanying drawings and figures. Attached Figure Description

[0007] This specification includes accompanying drawings, which form part of the document, to provide the reader with a further understanding of the embodiments of the invention. These drawings depict some embodiments of the invention and, together with the description herein, illustrate its principles. In these drawings:

[0008] Figures 1 to 8 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor structure according to a preferred embodiment of the present invention.

[0009] It should be noted that all the drawings in this specification are exemplary. For clarity and convenience of illustration, the dimensions and scale of the components in the drawings may be exaggerated or reduced. Generally, the same reference numerals in the drawings are used to indicate corresponding or similar element features in modified or different embodiments.

[0010] Explanation of main component symbols

[0011] 100 base

[0012] 100a Thin Film Transistor Region

[0013] 100b CMOS area

[0014] 102 Shallow trench isolation structure

[0015] 104 Hard mask layers

[0016] 106 Buffer Layer

[0017] 108 Thin-film transistor channel layer

[0018] 110 Covering Layer

[0019] 111 Thin-film transistor body

[0020] 112 Gate Dielectric Layer

[0021] 114 polycrystalline silicon layers

[0022] 116 Covering layer

[0023] 117 gate

[0024] 118 First partition wall

[0025] 120 lightly doped drain

[0026] 122 Second partition wall

[0027] 123 partition wall

[0028] 124 Source / Drain

[0029] 125 CMOS transistor device

[0030] 126 Source / Drain

[0031] 128 Contact Etching Stop Layer

[0032] 130 interlayer dielectric layer

[0033] 132 interlayer dielectric layer

[0034] 134 Upper Gate

[0035] 136 interlayer dielectric layer

[0036] 138 contacts

[0037] 140 Thin-film transistor device Detailed Implementation

[0038] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are by way of example only and are not intended to limit the scope of the invention. Various embodiments of the invention and various features in the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the scope of protection of the invention, and are intended to be included within the scope of the invention.

[0039] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" implies not only being "directly" on something but also includes being "on" something with an intervening feature or layer. Similarly, "above" or "above" implies not only being "above" or "above" something but also being "above" or "above" something without an intervening feature or layer (i.e., directly on something). Furthermore, spatially related terms such as "below," "under," "lower part," "above," and "upper part" are used herein for descriptive convenience to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0040] As used herein, the term "substrate" refers to the material on which subsequent material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0041] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0042] Readers can generally understand terms at least partially from their usage in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a single sense, or it can be used to describe a combination of features, structures, or characteristics in multiple senses. Similarly, depending at least partially on the context, terms such as "a," "an," "the," or "the" can also be understood to convey a single usage or multiple usages. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partially on the context.

[0043] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0044] Please refer to now. Figures 1 to 8 This is a cross-sectional schematic diagram of the fabrication process of a semiconductor structure according to a preferred embodiment of the present invention. In a preferred embodiment of the present invention, the semiconductor structure includes a thin-film transistor (TFT) using indium gallium zinc oxide (IGZO) as the channel layer. Its characteristic is that the thin-film transistor element can be integrated into the front end of line (FEOL) fabrication process of CMOS (complementary metal oxide semiconductor) and fabricated together with CMOS transistor elements (logic elements, such as PMOS or NMOS), which can significantly reduce the overall fabrication process steps and lower the fabrication cost. It should be noted that for the sake of simplicity... Figures 1 to 3 Only the thin-film transistor portion of the semiconductor structure is shown. Figures 4 to 8 It will simultaneously draw and explain the thin-film transistor portion and the metal-oxide-semiconductor portion of the semiconductor structure.

[0045] First, please refer to... Figure 1A substrate 100 is provided as the basis for the overall semiconductor structure. In this embodiment of the invention, since it needs to be integrated with CMOS fabrication processes, the substrate 100 is preferably a silicon substrate, such as a single-crystal silicon substrate, or a silicon-containing substrate, such as a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. Shallow trench isolation structures (STIs) 102 made of silicon oxide can be formed on the substrate 100 to define the active regions where transistor elements are to be formed. After defining the active regions, deep n-well regions (DNW, not shown) can also be formed in the substrate 100 by ion implantation to isolate the various active regions of the metal-oxide-semiconductor (MOS) region. A patterned hard mask layer 104 is formed on the substrate 100. In this embodiment of the invention, the material of the hard mask layer 104 can be silicon nitride, which can be patterned by photolithography. The function of the hard mask layer 104 is to define the regions in the thin-film transistor region where epitaxial growth is to be performed. Since no epitaxy is formed on the metal-oxide-semiconductor region, the entire region is covered by the hard mask layer 104. The hard mask layer 104 essentially exposes the active region in the thin-film transistor region.

[0046] Please refer to Figure 2 After the hard mask layer 104 is formed, a buffer layer 106, a thin-film transistor channel layer 108, and a capping layer 110 are sequentially formed on the substrate 100 and the hard mask layer 104. The buffer layer 106, as its name suggests, serves as a buffer layer between the substrate 100 and the thin-film transistor channel layer 108 during epitaxial growth. In a preferred embodiment of the present invention, the thin-film transistor channel layer 108 is preferably indium gallium zinc oxide (IGZO), and the material of the buffer layer 106 can be zinc oxide (ZnO), which can be formed on the entire substrate 100 and the hard mask layer 104 using a sputtering process. The zinc oxide buffer layer 106 can serve as a seed layer during the epitaxial growth of indium gallium zinc oxide and as a gradient buffer layer between the buffer layer and the silicon substrate 100. It can accelerate the crystal growth rate of the thin-film transistor channel layer 108, control its crystal orientation, and reduce defects such as lattice mismatch.

[0047] Rereference Figure 2After the buffer layer 106 is formed, an epitaxial fabrication process is performed to form a thin-film transistor channel layer 108 on the buffer layer 106. In a preferred embodiment of the present invention, the material of the thin-film transistor channel layer 108 is indium gallium zinc oxide (IGZO), especially amorphous indium gallium zinc oxide (α-IGZO), which has advantages such as high electron mobility, good uniformity, and low fabrication cost, making it very suitable as a material for high-voltage thin-film transistor devices. The indium gallium zinc oxide thin-film transistor channel layer 108 can be formed using methods such as molecular beam epitaxy or reactive solid-state epitaxy. In other embodiments, the material of the thin-film transistor channel layer 108 can also be a III-V group material such as silicon or germanium, which may also be formed by radio frequency sputtering. After the thin-film transistor channel layer 108, a capping layer 110 is formed on the thin-film transistor channel layer 108. In a preferred embodiment of the present invention, the capping layer 110 is made of silicon oxide. Besides protecting the underlying thin-film transistor channel layer 108, it also serves as a gate dielectric layer between the thin-film transistor channel layer 108 and the upper gate (not yet formed). Since the doped regions of the CMOS area have not yet been fabricated at this stage, the capping layer 110 can be annealed after its formation to improve the interface state between the silicon oxide capping layer 110 and the indium gallium zinc oxide thin-film transistor channel layer 108, thereby improving the stability and performance of the device. This fabrication sequence allows for good control of the overall thermal budget of the fabrication process.

[0048] Please refer to Figure 3 After the buffer layer 106, the thin-film transistor channel layer 108, and the capping layer 110 are formed, a photolithography process is performed to pattern these layer structures, thus forming individual thin-film transistor bodies 111. In this step, the buffer layer 106, the thin-film transistor channel layer 108, and the capping layer 110 located above the hard mask layer 104 (containing the entire CMOS logic region) are removed to prevent them from affecting the fabrication of subsequent components. At this point, the thin-film transistor channel layer 108 and the hard mask layer in the thin-film transistor body 111 constitute its active region; other components such as the gate, source, and drain will be fabricated in subsequent processes.

[0049] Please refer to Figure 4 The subsequent manufacturing process will also include the fabrication of transistors for the CMOS logic region. For example... Figure 4As shown, the left half of the figure depicts the thin-film transistor region 100a, and the right half depicts the CMOS region 100b. After patterning the thin-film transistor, the following steps are performed to fabricate the metal-oxide-semiconductor field-effect transistor device on the CMOS region 100b: (1) removing the remaining hard mask layer 104 to expose the active region on the CMOS region 100b; (2) performing an ion implantation process to form a corresponding well region in the active region of the CMOS region 100b, such as an n-type well of PMOS or a p-type well of NMOS (not shown); (3) sequentially forming a gate layer structure such as a silicon oxide gate dielectric layer 112, a polysilicon layer 114, and a silicon nitride capping layer 116; (4) patterning these layer structures to define the gate 117 of the CMOS transistor device; (5) forming a first spacer 118 and a lightly doped drain (LDD) 120 on both sides of the gate 117; and (6) forming a second spacer 122 and a source / drain 124 on both sides of the gate 117. Thus, the fabrication of the CMOS transistor device 125 is completed. Since the aforementioned CMOS fabrication process is a well-known technology and not the focus of this invention, its details will not be elaborated here. It should be noted that in the embodiments of this invention, the step of forming the first spacer 118 or the second spacer 122 can also simultaneously form spacers 123 on the sidewalls of the individual thin-film transistors defined on the thin-film transistor region 100a to protect the thin-film transistor structure. Furthermore, in a preferred embodiment of this invention, the top surface of the capping layer 116 of the gate structure is at the same level as the top surface of the capping layer 110 of the thin-film transistor structure, to facilitate subsequent planarization fabrication processes and process integration.

[0050] Please refer to Figure 5 After fabricating the CMOS transistor device, the source / drain 126 of the thin-film transistor is then formed on the thin-film transistor channel layer 108 in the thin-film transistor region 100a. In this embodiment of the invention, the thin-film transistor adopts a self-aligned coplanar design, and the source / drain 126 can be formed by forming heavily n-type (N+) doped regions on both sides of the thin-film transistor channel layer 108 by performing plasma treatment with fluorine, helium, argon, or hydrogen on the thin-film transistor channel layer 108 made of indium gallium zinc oxide. This fabrication method can reduce the parasitic capacitance of the thin-film transistor device and maintain a good interface state.

[0051] Rereference Figure 5After the source / drain 126 of the thin-film transistor is formed, a contact etch stop layer (CESL) 128 and an inter-dielectric layer (ILD0) 130 are sequentially formed on the substrate 100. In a preferred embodiment of the present invention, the contact etch stop layer 128 is conformally formed on the thin-film transistor body 111 and the CMOS transistor element 125. The contact etch stop layer 128 is made of silicon nitride and can be formed by PECVD (plasma-assisted chemical vapor deposition) to apply stress to the gate. In addition, before forming the contact etch stop layer 128, a metal silicide fabrication process can be performed on the CMOS transistor element to form a silicide layer (not shown) on the surface of its silicon gate, source, and drain to reduce contact resistance. The interlayer dielectric layer 130 covers the entire substrate surface and fills the gaps and spaces between components. Its material can be phosphosilicate glass (PSG), borosilicate glass (BPSG), or tetraethoxysilane (TEOS), and it can be formed by SACVD (sub-atmospheric pressure chemical vapor deposition) or HDPCVD (high density plasma chemical vapor deposition).

[0052] Please refer to Figure 6 After forming the contact etch stop layer 128 and the interlayer dielectric layer 130, a CMP (chemical mechanical planarization) process is then performed to remove the contact etch stop layer 128 and the interlayer dielectric layer 130 from the thin-film transistor body 111 and the CMOS transistor element 125. This step exposes the capping layer 110 of the thin-film transistor body 111 and the capping layer 116 of the CMOS transistor element 125. In a preferred embodiment of the present invention, the top surfaces of the capping layer 110 of the thin-film transistor body 111 and the top surfaces of the capping layer 116 of the CMOS transistor element 125 are designed to be at the same level, so that the top surfaces of the two structures can be exposed simultaneously by performing a single CMP process.

[0053] Please refer to Figure 7 After exposing the capping layer 110 of the thin-film transistor body 111 and the capping layer 116 of the CMOS transistor element 125, another interlayer dielectric layer (ILD1) 132 is then formed on the substrate surface. In a preferred embodiment of the invention, the interlayer dielectric layer 132 simultaneously covers the exposed capping layer 110 of the thin-film transistor body 111 and the capping layer 116 of the CMOS transistor element 125. Furthermore, in this embodiment, the interlayer dielectric layer 132, together with the underlying capping layer 110, serves as the gate dielectric layer of the thin-film transistor element; its material can be silicon oxide, and its thickness can be controlled within a desired range.

[0054] Please refer to Figure 8After the interlayer dielectric layer 132 is formed, an upper gate 134 is formed on the interlayer dielectric layer 132 above the thin-film transistor body 111, which is located between the source / drain 126 of the thin-film transistor. The material of the upper gate 134 can be a metal, such as titanium or titanium nitride. Thus, the upper gate 134, the source / drain 126, and the thin-film transistor channel layer 108 together constitute a thin-film transistor element 140. After the upper gate 134 is formed, another interlayer dielectric layer (ILD2) 136 is then covered on the upper gate 134 and the interlayer dielectric layer 132, and then a contact 138 is formed through the interlayer dielectric layer 132 and / or the interlayer dielectric layer 136 to connect the upper gate 134 and the source / drain 126 of the thin-film transistor element 140 and the gate 117 and the source / drain 124 of the CMOS transistor element 125. The material of the contact 138 can be a metal, such as tungsten, molybdenum, or copper. Subsequently, back-end CMOS fabrication (BEOL) can be performed over the interlayer dielectric layer 136 and the contact 138. Since these fabrication processes are well-known technologies and are not the focus of this invention, their details will not be described here.

[0055] In summary, the key point of this invention is to integrate high-voltage thin-film transistor (TFT) devices into the CMOS fabrication process, fabricating them together with the CMOS transistor devices. The active region of the TFT is defined before the fabrication of the CMOS transistor devices, while the source / drain of the TFT employs a self-aligned coplanar design, forming only after the CMOS transistor devices are fabricated. This approach allows for good control over the thermal budget of the fabrication process. Furthermore, the upper gate of the TFT is formed on one of the interlayer dielectric layers, and this interlayer dielectric layer serves as the gate dielectric layer, which facilitates integration with the CMOS fabrication process.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure, comprising: a substrate; a thin film transistor on the substrate, the thin film transistor comprising a thin film transistor channel layer, a first source and a first drain in the thin film transistor channel layer, and a first cap layer on the thin film transistor channel layer; a metal oxide semiconductor field effect transistor on the substrate, the metal oxide semiconductor field effect transistor comprising a second gate, a second source and a second drain on both sides of the second gate, and a second cap layer on the second gate, wherein the second cap layer is flush with a top surface of the first cap layer; and a first interlayer dielectric layer on the first cap layer and the second cap layer, wherein the first interlayer dielectric layer and the first cap layer together serve as a gate dielectric layer of the thin film transistor.

2. The semiconductor structure of claim 1, further comprising a first gate on the first interlayer dielectric layer.

3. The semiconductor structure of claim 2, further comprising a second interlayer dielectric layer on the first gate and the first interlayer dielectric layer, and a contact through the second interlayer dielectric layer and the first interlayer dielectric layer and connecting the first gate, the first source, the first drain, the second gate, the second source, and the second drain.

4. The semiconductor structure of claim 1, further comprising spacers on both sides of the thin film transistor channel layer and the second gate.

5. The semiconductor structure of claim 4, further comprising a contact etch stop layer on an outer side of the spacers.

6. The semiconductor structure of claim 5, further comprising a third interlayer dielectric layer on the contact etch stop layer, a top surface of the third interlayer dielectric layer, the contact etch stop layer, the first cap layer, and the second cap layer being flush, and the first interlayer dielectric layer being on the third interlayer dielectric layer, the contact etch stop layer, the first cap layer, and the second cap layer.

7. The semiconductor structure of claim 1, further comprising a buffer layer between the thin film transistor channel layer and the substrate.

8. A semiconductor fabrication process, comprising: forming a thin film transistor channel layer on a substrate; after the thin film transistor channel layer is formed, fabricating a metal oxide semiconductor field effect transistor on the substrate, the metal oxide semiconductor field effect transistor comprising a first gate, a first source, and a first drain; after the metal oxide semiconductor field effect transistor is fabricated, forming a second source and a second drain on the thin film transistor channel layer; after the second source and the second drain are formed, forming a first interlayer dielectric layer on the thin film transistor channel layer and the metal oxide semiconductor field effect transistor; and forming a second gate on the first interlayer dielectric layer, the second gate, the thin film transistor channel layer, the second source, and the second drain constituting a thin film transistor.

9. The semiconductor fabrication process of claim 8, further comprising simultaneously forming spacers on sidewalls of the thin film transistor channel layer and the first gate of the metal oxide semiconductor field effect transistor. ​ 10. The semiconductor fabrication process of claim 8, wherein the first gate of the metal oxide semiconductor field effect transistor further comprises a first cap layer, and the thin film transistor channel layer further comprises a second cap layer, the semiconductor fabrication process further comprising: forming a contact etch stop layer on the thin film transistor channel layer and the metal oxide semiconductor field effect transistor; performing a chemical mechanical planarization fabrication process to remove portions of the contact etch stop layer to expose the first cap layer and the second cap layer; and forming the first interlayer dielectric layer on the thin film transistor channel layer and the metal oxide semiconductor field effect transistor after the chemical mechanical planarization fabrication process.

11. The semiconductor fabrication process of claim 8, further comprising: forming a patterned hard mask layer on the substrate prior to forming the thin film transistor channel layer, the patterned hard mask layer exposing epitaxial regions of the substrate; performing an epitaxial fabrication process to grow the thin film transistor channel layer; performing a photolithography fabrication process to pattern the thin film transistor channel layer to define active regions of the thin film transistor; and removing the hard mask layer.

12. The semiconductor fabrication process of claim 11, further comprising: forming a second interlayer dielectric layer on the first interlayer dielectric layer after forming the second gate; and forming contacts through the second interlayer dielectric layer and the first interlayer dielectric layer to connect the first gate, the first source, the first drain, the second gate, the second source, and the second drain.

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