Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate comprising a first region, an isolation region, and a second region arranged along a first direction, the first region having a plurality of first active regions and the second region having a plurality of second active regions; a first gate structure located on the second region; an isolation structure located on the first region, the isolation structure being separate from the first gate structure; and a first conductive plug, the first conductive plug covering the sidewalls and a portion of the top surface of the first gate structure and not contacting the isolation structure. Since the first gate structure and the isolation structure are separate, redundant capacitance formed by the connection between the first gate structure and the isolation structure is avoided, thereby effectively reducing dynamic power consumption and increasing circuit speed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As the integration density of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as transistor dimensions decrease dramatically, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the short channel effect still exists in the Fin Field-Effect Transistor.

[0004] Furthermore, to further reduce the impact of the short channel effect on semiconductor devices and lower channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The strained silicon technology method includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doped regions in the grooves through an epitaxial growth process.

[0005] In order to prevent the source and drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin. At the same time, in order to reduce the area of ​​the isolation layer and improve the integration of the formed semiconductor structure, the existing technology introduces SDB (Single Diffusion Break) technology.

[0006] However, existing methods still have many problems in the process of forming semiconductor structures. Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can reduce dynamic power consumption and improve circuit speed.

[0008] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region, an isolation region, and a second region arranged along a first direction, the isolation region being located between the first region and the second region, the first region having a plurality of first active regions, the second region having a plurality of second active regions, the plurality of first active regions and the plurality of second active regions being respectively parallel to a second direction, and the first direction being perpendicular to the second direction; a first gate structure located on the second region and a portion of the isolation region, the first gate structure spanning the second active region; an isolation structure located on the first region and a portion of the isolation region, the isolation structure spanning the first active region, and the isolation structure and the first gate structure being separate from each other; and a first conductive plug, the first conductive plug covering the sidewalls and a portion of the top surface of the first gate structure, and the first conductive plug not contacting the isolation structure.

[0009] Optionally, it also includes: a dielectric layer, which covers the side walls of the first gate structure and the side walls of the isolation structure; a second opening, which is located in the dielectric layer and between the first gate structure and the isolation structure, so that the isolation structure and the first gate structure are separated from each other.

[0010] Optionally, it further includes: a plurality of second gate structures located on the substrate, wherein the second gate structures respectively span the first active region and the second active region.

[0011] Optionally, it also includes: a plurality of first source-drain doped layers located in the first active area, the first source-drain doped layers are located between adjacent second gate structures or between adjacent isolation structures and second gate structures, and the first source-drain doped layers have first source-drain ions; a plurality of second source-drain doped layers located in the second active area, the second source-drain doped layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the second source-drain doped layers have second source-drain ions.

[0012] Optionally, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

[0013] Optionally, the method further includes: a plurality of second conductive plugs, the second conductive plugs being electrically connected to the second gate structure; and a first conductive layer, the first conductive layer being electrically connected to the first conductive plug and the second conductive plug respectively.

[0014] Optionally, the material of the isolation structure includes silicon nitride.

[0015] Optionally, the first active region is a first fin; and the second active region is a second fin.

[0016] Optionally, it also includes: an isolation layer located on the substrate, the isolation layer covering part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the top surface of the second fin.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region, an isolation region, and a second region arranged along a first direction, the isolation region being located between the first region and the second region, the first region having a plurality of first active regions, the second region having a plurality of second active regions, the plurality of first active regions and the plurality of second active regions being respectively parallel to a second direction, and the first direction being perpendicular to the second direction; forming an initial first gate structure on the substrate, the initial first gate structure spanning the plurality of first active regions and the plurality of second active regions respectively; removing the initial first gate structure located on the first region and a portion of the isolation region, and the exposed first active region, so that the initial first gate structure forms a first gate structure; forming an isolation structure on the first region and a portion of the isolation region, the isolation structure being connected to the first gate structure; removing a portion of the first gate structure located on the isolation region and a portion of the isolation structure located on the isolation region, so that the isolation structure and the first gate structure are separated from each other; forming a first conductive plug, the first conductive plug covering the sidewalls and a portion of the top surface of the first gate structure, and the first conductive plug not contacting the isolation structure.

[0018] Optionally, before forming the isolation structure, it also includes: forming a dielectric layer on the substrate, the dielectric layer covering the side walls of the initial first gate structure; the method for forming the isolation structure includes: removing the initial first gate structure located on the first region and a portion of the isolation region, and the exposed first active region, forming a first opening in the dielectric layer; forming the isolation structure in the first opening; after removing a portion of the first gate structure located on the isolation region and a portion of the isolation structure located on the isolation region, forming a second opening in the dielectric layer, the second opening separating the isolation structure and the first gate structure from each other.

[0019] Optionally, the method for forming the isolation structure includes: forming an initial isolation structure in the first opening, and on the first gate structure and the dielectric layer; and flattening the initial isolation structure until the top surface of the first gate structure and the dielectric layer is exposed to form the isolation structure.

[0020] Optionally, the process of forming the initial first gate structure further includes: forming a plurality of second gate structures on the substrate, wherein the second gate structures respectively span the first active region and the second active region.

[0021] Optionally, before forming the initial first gate structure and the second gate structure, it also includes: forming a plurality of first source-drain doped layers in the first active area, the first source-drain doped layers are located between adjacent second gate structures or between adjacent initial first gate structures and second gate structures, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second active area, the second source-drain doped layers are located between adjacent second gate structures or between adjacent initial first gate structures and second gate structures, and the second source-drain doped layers have second source-drain ions.

[0022] Optionally, the first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

[0023] Optionally, the process of forming the first conductive plug also includes: forming a plurality of second conductive plugs, the second conductive plugs being electrically connected to the second gate structure; after forming the plurality of second conductive plugs, forming a first conductive layer, the first conductive layer being electrically connected to the first conductive plug and the second conductive plug, respectively.

[0024] Optionally, the first active region is a first fin; and the second active region is a second fin.

[0025] Optionally, before forming the initial first gate structure, it also includes: forming an isolation layer on the substrate, the isolation layer covering part of the side wall of the first fin and part of the side wall of the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the top surface of the second fin.

[0026] Optionally, the material of the isolation structure includes silicon nitride.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the method for forming a semiconductor structure according to the technical solution of the present invention, the isolation structure and the first gate structure are separated from each other by removing a portion of the first gate structure located on the isolation region and a portion of the isolation structure located on the isolation region; and a first conductive plug is formed, the first conductive plug covering the sidewalls and a portion of the top surface of the first gate structure and not contacting the isolation structure. This prevents the first gate structure from forming redundant capacitance when connected to the isolation structure, thereby effectively reducing dynamic power consumption and increasing circuit speed.

[0029] The semiconductor structure of the present invention includes: an isolation structure located on the first region and a portion of the isolation region, the isolation structure spanning the first active region and separated from the first gate structure; and a first conductive plug covering the sidewalls and a portion of the top surface of the first gate structure and not in contact with the isolation structure. Since the first gate structure and the isolation structure are separated, redundant capacitance formed by the connection between the first gate structure and the isolation structure is avoided, thereby effectively reducing dynamic power consumption and increasing circuit speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural diagram of a semiconductor structure;

[0031] Figures 2 to 13 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, existing methods still have many problems in the process of forming semiconductor structures, which will be described in detail below with reference to the accompanying drawings.

[0033] Figure 1 It is a structural diagram of a semiconductor structure.

[0034] Please refer to Figure 1, providing a substrate 100, the substrate 100 including an isolation region A1 and a plurality of device regions B1 arranged along a first direction X, the isolation region A1 being located between adjacent device regions B1, the isolation region A1 including a first region I and a second region II arranged along a second direction Y, the second direction X being perpendicular to the first direction Y; forming a plurality of first fins 101 and a plurality of second fins 102 on the device region B1, the first fins 101 and the second fins 102 being arranged in parallel along the second direction Y, and the first fins 101 and the second fins 102 also spanning the isolation region A1; forming an initial first gate structure (not shown) on the isolation region A1, the initial first gate structure spanning The first fin 101 and the second fin 102; forming a dielectric layer (not shown) on the substrate 100, the dielectric layer covering the sidewalls of the initial first gate structure; removing the initial first gate structure located on the first region I and the exposed first fin 101, forming a first opening (not shown) in the dielectric layer, and making the initial first gate structure form a first gate structure 103; forming an isolation structure 104 in the first opening, the isolation structure 104 being connected to the first gate structure 103; forming a first conductive plug 105 in the dielectric layer, the first conductive plug 105 being respectively connected to the first gate structure 103 and the isolation structure 104.

[0035] Power consumption in CMOS chips can be divided into static and dynamic sources. Dynamic power accounts for the majority of total power consumption. Dynamic power can be divided into two types: 1. The switching power consumption that charges and discharges the load capacitor when the gate flips; 2. The internal power consumption caused by short-circuit current when the series-parallel configuration of PMOS and NMOS transistors is partially conductive. The majority of this power consumption is caused by switching power.

[0036] In this embodiment, since the first gate structure 103 is connected to the isolation structure 104, a redundant capacitor with a large capacitance is formed, and the first conductive plug 105 is connected to the first gate structure 103 and the isolation structure 104 respectively, so that the redundant capacitor is involved in the calculation of the flip power consumption, resulting in a decrease in circuit speed.

[0037] Based on this, the present invention provides a semiconductor structure and a method for forming the same. By removing a portion of the first gate structure and the isolation structure located above the isolation region, a second opening is formed in the dielectric layer. A first conductive plug is formed within the second opening, covering the sidewalls and a portion of the top surface of the first gate structure and not contacting the isolation structure. This prevents the first gate structure from forming redundant capacitance when connected to the isolation structure, thereby effectively reducing dynamic power consumption and increasing circuit speed.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 13 It is a structural schematic diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0040] Please refer to Figure 2 and Figure 3 , Figure 2 It is a top view of the semiconductor structure. Figure 3 yes Figure 2 In the cross-sectional schematic diagram along line AA, a substrate 200 is provided. The substrate 200 includes a first region I, an isolation region III, and a second region II arranged along a first direction X. The isolation region III is located between the first region I and the second region II. The first region I has a plurality of first active regions 201, and the second region II has a plurality of second active regions 202. The plurality of first active regions 201 and the plurality of second active regions 202 are respectively parallel to a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0041] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0042] In this embodiment, the first active region 201 and the second active region 202 are used to subsequently form transistors of different types.

[0043] In this embodiment, the first active region 201 may be a first fin; and the second active region 202 may be a second fin.

[0044] In this embodiment, the method for forming the substrate 200, the first fin and the second fin may include: providing an initial substrate (not shown), forming a patterned layer (not shown) on the substrate, the patterned layer exposing the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200, the first fin and the second fin.

[0045] In this embodiment, the material of the first fin and the second fin may be silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0046] Please refer to Figure 4 , Figure 4 and Figure 3In accordance with the viewing direction, an isolation layer 203 is formed on the substrate 200, the isolation layer 203 covers part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer 203 is lower than the top surface of the first fin and the top surface of the second fin.

[0047] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing part of the initial isolation layer to form the isolation layer 203, and the top surface of the isolation layer 203 is lower than the top surface of the first fin and the second fin.

[0048] The isolation layer 203 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 203 is made of silicon oxide.

[0049] After forming the isolation layer 203, the process further includes: forming an initial first gate structure on the substrate 200, wherein the initial first gate structure spans across a plurality of the first active regions 201 and a plurality of the second active regions 202; forming a plurality of second gate structures on the substrate 200, wherein the second gate structures span across the first active regions 201 and the second active regions 202; and forming a dielectric layer on the substrate 200, wherein the dielectric layer covers the sidewalls of the initial first gate structure. For detailed formation process, please refer to Figures 5 to 9 .

[0050] Please refer to Figure 5 A first dummy gate structure 204 and several second dummy gate structures 205 are formed on the substrate 200 . The first dummy gate structure 204 and the second dummy gate structure 205 respectively cross the first active area 201 and the second active area 202 .

[0051] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously. The first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0052] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 respectively include: a dummy gate dielectric layer (not labeled) located on the isolation layer 203; a dummy gate layer (not labeled) located on the dummy gate dielectric layer; and sidewalls (not labeled) formed between the dummy gate layer and the sidewalls of the dummy gate dielectric layer.

[0053] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0054] In this embodiment, the material of the dummy gate layer is polysilicon.

[0055] In this embodiment, the sidewall spacer is made of silicon nitride.

[0056] Please refer to Figure 6 The first active area 201 is etched using the first dummy gate structure 204 and the second dummy gate structure 205 as masks to form a plurality of first source-drain openings (not shown) in the first active area 201; the second active area 202 is etched using the first dummy gate structure 204 and the second dummy gate structure 205 as masks to form a plurality of second source-drain openings (not shown) in the second active area 202; the first source-drain doped layer 206 is formed in the first source-drain openings; and the second source-drain doped layer 207 is formed in the second source-drain openings.

[0057] In this embodiment, the first source-drain doped layer 206 contains first source-drain ions, and the second source-drain doped layer 207 contains second source-drain ions. The first source-drain ions and the second source-drain ions are of different electrical types.

[0058] In this embodiment, the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions. In one embodiment, the first source-drain ions are N-type ions, and the second source-drain ions are P-type ions.

[0059] Please refer to Figure 7 An initial dielectric layer (not shown) is formed on the substrate 200, and the initial dielectric layer covers the first source-drain doped layer 206, the second source-drain doped layer 207, the first dummy gate structure 204, and the second dummy gate structure 205; the initial dielectric layer is planarized until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, thereby forming the dielectric layer 208.

[0060] In this embodiment, the material of the dielectric layer 208 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0061] Please refer to Figure 8 , remove the first dummy gate structure 204, and form a first gate opening (not marked) in the dielectric layer 208; form the initial first gate structure 209 in the first gate opening; remove the second dummy gate structure 205, and form a second gate opening (not marked) in the dielectric layer; and form the second gate structure 210 in the second gate opening.

[0062] In this embodiment, the dummy gate dielectric layer and the dummy gate layer of the first dummy gate structure 204 and the second dummy gate structure 205 are specifically removed.

[0063] In this embodiment, the initial first gate structure 209 and the second gate structure 210 respectively include: a gate dielectric layer (not labeled) and a gate layer (not labeled) located on the gate dielectric layer.

[0064] In this embodiment, the gate dielectric layer is made of a high-K dielectric material.

[0065] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0066] In this embodiment, the first source-drain doped layer 206 is located between adjacent second gate structures 210 or between adjacent initial first gate structures 209 and the second gate structure 210; the second source-drain doped layer 207 is located between adjacent second gate structures 210 or between adjacent initial first gate structures 209 and the second gate structure 210.

[0067] Please refer to Figure 9 , remove the initial first gate structure 209 located on the first region I and part of the isolation region III, and the exposed first active region 201, form a first opening 211 in the dielectric layer 208, and form the initial first gate structure 209 into a first gate structure 212.

[0068] In this embodiment, a wet etching process is used to remove the initial first gate structure 209 located on the first region I and the exposed first active region 201. In other embodiments, a dry etching process may also be used to remove the initial first gate structure located on the first region and the exposed first active region.

[0069] Please refer to Figure 10 , an isolation structure 213 is formed in the first opening 211 , and the isolation structure 213 is connected to the first gate structure 212 .

[0070] In this embodiment, the method for forming the isolation structure 13 includes: forming an initial isolation structure (not shown) in the first opening 211 and on the first gate structure 212 and the dielectric layer 208; and flattening the initial isolation structure until the top surfaces of the first gate structure 212 and the dielectric layer 208 are exposed to form the isolation structure 213.

[0071] In this embodiment, the isolation structure 213 is made of silicon nitride.

[0072] Please refer to Figure 11 , removing a portion of the first gate structure 212 located on the isolation region III and a portion of the isolation structure 213 located on the isolation region III, and forming a second opening 214 in the dielectric layer 208 .

[0073] In this embodiment, the first gate structure 212 and the isolation structure 213 are separated by the second opening 214, so that the isolation structure 213 and the first gate structure 212 are separated from each other, which can avoid the first gate structure 212 and the isolation structure 213 being connected to form a redundant capacitor, thereby effectively reducing dynamic power consumption and improving the speed of the circuit.

[0074] It should be noted that when removing part of the first gate structure 212 located on the isolation region III and part of the isolation structure 213 located on the isolation region III, due to limitations of the etching process, the sidewalls of the first gate structure 212 will be etched into an inclined shape.

[0075] Please refer to Figure 12 , Figure 12 is a top view of the semiconductor structure. Figure 13 for Figure 12 Schematic diagram of the cross section along line BB, Figure 13 The substrate 200, the first active area 201, the second active area 202, the isolation layer 203, the dielectric layer 208 and the first conductive layer 217 are omitted, and a first conductive plug 215 is formed in the second opening 214. The first conductive plug 215 covers the sidewalls and part of the top surface of the first gate structure 212, and the first conductive plug 215 does not contact the isolation structure 213.

[0076] In this embodiment, the first conductive plug 215 is only electrically connected to the first gate structure 212 and does not contact the isolation structure 213 , in order to prevent the first gate structure 212 and the isolation structure 213 from being connected again to form a redundant capacitor.

[0077] It should be noted that since the side walls of the first gate structure 212 are inclined, the contact area between the first gate structure 212 and the first conductive plug 215 can be increased, thereby reducing the contact resistance between the first gate structure 212 and the first conductive plug 215, effectively improving the electrical performance of the semiconductor structure finally formed.

[0078] In this embodiment, the process of forming the first conductive plug 215 also includes: forming a plurality of second conductive plugs 216, and the second conductive plugs 216 are electrically connected to the second gate structure 210; after forming the plurality of second conductive plugs 216, forming a first conductive layer 217, and the first conductive layer 217 is electrically connected to the first conductive plug 215 and the second conductive plug 216 respectively.

[0079] Accordingly, a semiconductor structure is also provided in an embodiment of the present invention, please continue to refer to Figure 12 , comprising: a substrate 200, the substrate 200 comprising a first region I, an isolation region III, and a second region II arranged along a first direction X, the isolation region III being located between the first region I and the second region II, the first region I having a plurality of first active regions 201, the second region II having a plurality of second active regions 202, the plurality of first active regions 201 and the plurality of second active regions 202 being respectively parallel to a second direction Y, the first direction X being perpendicular to the second direction Y; a first gate structure 212 located on the second region II, the first gate structure 212 spanning the second active region 202; an isolation structure 213 located on the first region I, the isolation structure 213 spanning the first active region 201, and the isolation structure 213 and the first gate structure 212 being separate from each other; a first conductive plug 215, the first conductive plug 215 covering a sidewall and a portion of a top surface of the first gate structure 212, and the first conductive plug 215 not contacting the isolation structure 213.

[0080] In this embodiment, it also includes: a dielectric layer 208, which covers the sidewalls of the first gate structure 212 and the sidewalls of the isolation structure 213; a second opening 214, which is located in the dielectric layer 208 and between the first gate structure 212 and the isolation structure 213, so that the isolation structure 213 and the first gate structure 212 are separated from each other.

[0081] In this embodiment, since the first gate structure 212 and the isolation structure 213 are separated from each other, the first gate structure 212 and the isolation structure 213 are prevented from being connected to form redundant capacitance, thereby effectively reducing dynamic power consumption and improving circuit speed.

[0082] In this embodiment, the present invention further includes: a plurality of second gate structures 210 located on the substrate 200 , wherein the second gate structures 210 respectively span the first active region 201 and the second active region 202 .

[0083] In this embodiment, it also includes: a plurality of first source-drain doped layers 206 located in the first active area 201, the first source-drain doped layers 206 are located between adjacent second gate structures 210 or between adjacent isolation structures 213 and second gate structures 210, and the first source-drain doped layers 206 have first source-drain ions; a plurality of second source-drain doped layers 207 located in the second active area 202, the second source-drain doped layers 207 are located between adjacent second gate structures 210 or between adjacent first gate structures 212 and second gate structures 210, and the second source-drain doped layers 207 have second source-drain ions.

[0084] In this embodiment, the first source and drain ions are of different electrical types from the second source and drain ions; the first source and drain ions include N-type ions or P-type ions; and the second source and drain ions include P-type ions or N-type ions. In one embodiment, the first source and drain ions are N-type ions, and the second source and drain ions are P-type ions.

[0085] In this embodiment, the structure further includes: a plurality of second conductive plugs 216 electrically connected to the second gate structure 210 ; and a first conductive layer 217 electrically connected to the first conductive plugs 215 and the second conductive plugs 216 .

[0086] In this embodiment, the isolation structure 213 is made of silicon nitride.

[0087] In this embodiment, the first active region 201 is a first fin; the second active region 202 is a second fin.

[0088] In this embodiment, it also includes: an isolation layer 203 located on the substrate 200, the isolation layer 203 covers part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer 203 is lower than the top surface of the first fin and the top surface of the second fin.

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate, the substrate comprising a first region, an isolation region, and a second region arranged along a first direction, the isolation region being located between the first region and the second region, the first region having a plurality of first active regions, the second region having a plurality of second active regions, the plurality of first active regions and the plurality of second active regions being parallel to a second direction, and the first direction being perpendicular to the second direction; a first gate structure located on the second region and a portion of the isolation region, the first gate structure spanning the second active region; an isolation structure located on the first region and a portion of the isolation region, the isolation structure spanning the first active region, the first gate structure and the isolation structure being adjacently arranged in the first direction, and the isolation structure and the first gate structure being separate from each other; A first conductive plug covers a sidewall and a portion of a top surface of the first gate structure, and the first conductive plug is not in contact with the isolation structure.

2. The semiconductor structure according to claim 1, wherein: Also includes: a dielectric layer, wherein the dielectric layer covers the sidewalls of the first gate structure and the sidewalls of the isolation structure; The second opening is located in the dielectric layer and between the first gate structure and the isolation structure, so that the isolation structure and the first gate structure are separated from each other.

3. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of second gate structures are located on the substrate, wherein the second gate structures respectively cross the first active region and the second active region.

4. The semiconductor structure according to claim 3, wherein: Also includes: a plurality of first source-drain doped layers located in the first active area, the first source-drain doped layers being located between adjacent second gate structures or between adjacent isolation structures and second gate structures, and having first source-drain ions therein; a plurality of second source-drain doped layers located in the second active area, the second source-drain doped layers being located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and having second source-drain ions therein.

5. The semiconductor structure according to claim 4, wherein: The first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

6. The semiconductor structure according to claim 3, wherein: Also includes: a plurality of second conductive plugs, wherein the second conductive plugs are electrically connected to the second gate structure; A first conductive layer is electrically connected to the first conductive plug and the second conductive plug respectively.

7. The semiconductor structure according to claim 1, wherein: The material of the isolation structure includes silicon nitride.

8. The semiconductor structure according to claim 1, wherein: The first active region is a first fin; the second active region is a second fin.

9. The semiconductor structure according to claim 8, wherein: Also includes: An isolation layer is located on the substrate, the isolation layer covers a portion of the sidewall of the first fin and a portion of the sidewall of the second fin, and a top surface of the isolation layer is lower than a top surface of the first fin and a top surface of the second fin.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, an isolation region, and a second region arranged along a first direction, the isolation region being located between the first region and the second region, the first region having a plurality of first active regions, the second region having a plurality of second active regions, the plurality of first active regions and the plurality of second active regions being respectively parallel to a second direction, and the first direction being perpendicular to the second direction; forming an initial first gate structure on the substrate, wherein the initial first gate structure respectively spans across a plurality of the first active regions and a plurality of the second active regions; removing the initial first gate structure located on the first region and a portion of the isolation region, and the exposed first active region, so that the initial first gate structure forms a first gate structure; forming an isolation structure on the first region and a portion of the isolation region, wherein the isolation structure is connected to the first gate structure; removing a portion of the first gate structure located on the isolation region and a portion of the isolation structure located on the isolation region, so that the isolation structure and the first gate structure are separated from each other, and the first gate structure and the isolation structure are adjacently arranged in the first direction; A first conductive plug is formed, where the first conductive plug covers a sidewall and a portion of a top surface of the first gate structure and does not contact the isolation structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: Before forming the isolation structure, it also includes: forming a dielectric layer on the substrate, the dielectric layer covering the side walls of the initial first gate structure; the method for forming the isolation structure includes: removing the initial first gate structure located on the first region and part of the isolation region, and the exposed first active region, forming a first opening in the dielectric layer; forming the isolation structure in the first opening; after removing part of the first gate structure located on the isolation region and part of the isolation structure located on the isolation region, forming a second opening in the dielectric layer, the second opening making the isolation structure and the first gate structure separate from each other.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the isolation structure includes: forming an initial isolation structure in the first opening and on the first gate structure and the dielectric layer; and flattening the initial isolation structure until the top surfaces of the first gate structure and the dielectric layer are exposed to form the isolation structure.

13. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the initial first gate structure further includes: forming a plurality of second gate structures on the substrate, wherein the second gate structures respectively span the first active region and the second active region.

14. The method for forming a semiconductor structure according to claim 13, wherein: Before forming the initial first gate structure and the second gate structure, it also includes: forming a plurality of first source-drain doped layers in the first active area, the first source-drain doped layers are located between adjacent second gate structures or between adjacent initial first gate structures and second gate structures, and the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second active area, the second source-drain doped layers are located between adjacent second gate structures or between adjacent initial first gate structures and second gate structures, and the second source-drain doped layers have second source-drain ions.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first source-drain ions and the second source-drain ions are of different electrical types; the first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

16. The method for forming a semiconductor structure according to claim 13, wherein: The process of forming the first conductive plug also includes: forming a plurality of second conductive plugs, the second conductive plugs being electrically connected to the second gate structure; and after forming the plurality of second conductive plugs, forming a first conductive layer, the first conductive layer being electrically connected to the first conductive plug and the second conductive plug, respectively.

17. The method for forming a semiconductor structure according to claim 10, wherein: The first active region is a first fin; the second active region is a second fin.

18. The method for forming a semiconductor structure according to claim 17, wherein: Before forming the initial first gate structure, it also includes: forming an isolation layer on the substrate, the isolation layer covering part of the sidewall of the first fin and part of the sidewall of the second fin, and the top surface of the isolation layer is lower than the top surface of the first fin and the top surface of the second fin.

19. The method for forming a semiconductor structure according to claim 10, wherein: The material of the isolation structure includes silicon nitride.

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