A transistor and a method of fabricating the same

Abstract

The embodiment of the application provides a transistor and a preparation method thereof, and relates to the technical field of semiconductor devices, to solve the problem that the accuracy of the channel length of the transistor is affected by etching precision, the stability is poor, and it is difficult to adapt to the miniaturization demand of semiconductor devices. The transistor comprises: a substrate layer; a first electrode arranged on one side of the substrate layer; a second electrode arranged on the side of the first electrode away from the substrate layer; an active layer arranged between the first electrode and the second electrode, the active layer comprising a first structure part, a second structure part and a third structure part, the first structure part being electrically connected with the first electrode, the third structure part being electrically connected with the second electrode, the second structure part being connected between the first structure part and the third structure part, the first structure part, the second structure part and the third structure part forming a first groove structure, the opening of the first groove structure being perpendicular to the thickness direction of the first electrode; and a first gate electrode arranged in the first groove structure and insulated from the active layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a transistor and its fabrication method. Background Technology

[0002] To meet the demands of semiconductor device miniaturization, the size of semiconductor devices continues to shrink. Current transistors are typically planar layer transistors, with the source and drain electrodes fabricated through etching processes. The channel length is determined by the horizontal length of the gate or the horizontal distance between the source and drain electrodes. Therefore, during the etching process, the smaller the transistor size, the more significantly the distance between the source and drain electrodes is affected by the etching precision, resulting in lower accuracy of the channel length. This leads to poorer transistor stability, making it difficult to adapt to the miniaturization requirements of semiconductor devices. Summary of the Invention

[0003] This application provides a transistor and its fabrication method, relating to the field of semiconductor device technology, to solve the problem that current transistors are usually planar layer transistors, and the accuracy of the transistor channel length is affected by the etching precision, resulting in poor transistor stability and difficulty in meeting the miniaturization requirements of semiconductor devices.

[0004] A first aspect of this application provides a transistor, including:

[0005] Substrate layer;

[0006] The first electrode is disposed on one side of the substrate layer;

[0007] The second electrode is disposed on the side of the first electrode away from the substrate layer;

[0008] An active layer is disposed between the first electrode and the second electrode. The active layer includes a first structural portion, a second structural portion, and a third structural portion. The first structural portion is electrically connected to the first electrode, the third structural portion is electrically connected to the second electrode, and the second structural portion is connected between the first structural portion and the third structural portion. The first structural portion, the second structural portion, and the third structural portion form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0009] A first gate is disposed within the first groove structure, and the first gate is insulated from the active layer.

[0010] In some embodiments, the transistor further includes:

[0011] The second groove structure penetrates the second electrode, and one end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part.

[0012] A second gate is disposed within the second groove structure. The second gate is insulated from the active layer and from the first electrode.

[0013] In some embodiments, the active layer includes a first active layer and a second active layer, and the orthographic projections of the first active layer and the second active layer on the substrate layer do not overlap, and the first active layer and the second active layer are respectively located on both sides of the second groove structure.

[0014] The second electrode includes a first sub-electrode and a second sub-electrode, and the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate do not overlap. The first sub-electrode and the second sub-electrode are respectively located on both sides of the second groove structure.

[0015] In some embodiments, the orthogonal projection of the active layer onto the substrate surrounds the orthogonal projection of the second groove structure onto the substrate.

[0016] In some embodiments, one end of the second gate covers the side of the first sub-electrode away from the substrate, and the other end of the second gate covers the side of the second sub-electrode away from the substrate.

[0017] In some embodiments, the transistor further includes:

[0018] The second gate covers the side of the second structure that is away from the first structure.

[0019] In some embodiments, the first gate includes a fourth structural portion, a fifth structural portion, and a sixth structural portion. The fourth structural portion is disposed on the side of the first structural portion away from the substrate layer, and the sixth structural portion is disposed on the side of the third structural portion away from the second electrode. The fifth structural portion is connected between the fourth structural portion and the sixth structural portion. The fourth structural portion, the fifth structural portion, and the sixth structural portion form a third groove structure, and the opening of the third groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0020] An insulating layer is disposed between the first gate and the active layer.

[0021] A second aspect of this application also provides a method for fabricating a transistor, comprising:

[0022] A first electrode and a second electrode are sequentially disposed on one side of the substrate layer;

[0023] An active layer is disposed between the first electrode and the second electrode, wherein the active layer includes a first structural portion, a second structural portion and a third structural portion, the first structural portion is electrically connected to the first electrode, the third structural portion is electrically connected to the second electrode, the second structural portion is connected between the first structural portion and the third structural portion, the first structural portion, the second structural portion and the third structural portion form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode;

[0024] A first gate is disposed within the first groove structure, and the first gate is insulated from the active layer.

[0025] In some embodiments, the provision of an active layer between the first electrode and the second electrode includes:

[0026] A first insulating layer is disposed on the side of the first electrode away from the substrate layer;

[0027] A second electrode layer is disposed on the side of the insulating layer away from the substrate layer;

[0028] At least a portion of the second electrode layer and at least a portion of the insulating layer are removed sequentially to obtain the second electrode and the insulating structure;

[0029] Remove the insulation structure;

[0030] The active layer structure is disposed at the location of the insulating structure;

[0031] A portion of the active layer structure is removed to form the first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0032] In some embodiments, prior to the step of removing the insulation structure, the method further includes:

[0033] A second groove structure is provided, which penetrates the second electrode, and one end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part.

[0034] A second insulating layer is provided within the second groove structure;

[0035] A second gate is disposed within the second groove structure, and a second insulating layer is spaced between the second gate and the first electrode.

[0036] This application provides a transistor and its fabrication method. By vertically arranging the first electrode, second electrode, and active layer in the transistor, and setting the active layer as a first groove structure, and placing the first gate within the first groove structure, the contact area between the active layer and the first gate can be increased. This further increases the channel length, improves the carrier mobility in the active layer, and also increases the contact area between the active layer and the source and drain electrodes, enhancing the conductivity between the source / drain electrodes and the active layer, thereby improving the transistor's performance. Furthermore, the first electrode, second electrode, and active layer can be directly fabricated using more controllable processes such as thin-film growth, improving the accuracy of the channel length and facilitating the reduction of transistor size to meet the miniaturization requirements of semiconductor devices. Attached Figure Description

[0037] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic structural diagram of a transistor provided for an embodiment of this application;

[0039] Figure 2 A schematic structural diagram of another transistor provided in an embodiment of this application;

[0040] Figure 3 A schematic structural diagram of another transistor provided in an embodiment of this application;

[0041] Figure 4 A schematic cross-sectional view of a transistor provided for an embodiment of this application;

[0042] Figure 5 A schematic structural diagram of another transistor provided in an embodiment of this application;

[0043] Figure 6 A schematic structural diagram of a transistor provided for an embodiment of this application;

[0044] Figure 7 A schematic structural diagram of another transistor provided in an embodiment of this application;

[0045] Figure 8 A schematic flowchart illustrating a method for fabricating a transistor according to an embodiment of this application;

[0046] Figure 9 A schematic flowchart illustrating another method for fabricating a transistor according to an embodiment of this application;

[0047] Figure 10 This is a schematic flowchart illustrating another method for fabricating a transistor, as provided in an embodiment of this application. Detailed Implementation

[0048] The embodiments will now be described in detail, with examples illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims. In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways, and the apparatus embodiments described below are merely exemplary. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0049] Figure 1 This is a schematic structural diagram of a transistor provided for an embodiment of this application. For example... Figure 1 As shown, this application embodiment provides a transistor 100, including: a substrate layer 110; a first electrode 120 disposed on one side of the substrate layer 110; a second electrode 130 disposed on the side of the first electrode 120 away from the substrate layer 110; and an active layer 140 disposed between the first electrode 120 and the second electrode 130. The active layer 140 includes a first structural portion 141, a second structural portion 142, and a third structural portion 143. The first structural portion 141 is electrically connected to the first electrode 120, the third structural portion 143 is electrically connected to the second electrode 130, and the second structural portion 142 is connected between the first structural portion 141 and the third structural portion 143. The first structural portion 141, the second structural portion 142, and the third structural portion 143 form a first groove structure. The opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode. For example, the first electrode 120 and the second electrode 130 can serve as the source and drain of the transistor, and the active layer can be used to form a channel. The first gate 150 is disposed within the first groove structure, and the first gate 150 is insulated from the active layer 140.

[0050] For example, a first insulating layer is disposed between the first gate and the active layer. The first insulating layer may be disposed within a first recess structure, and the first gate may also be disposed on the side of the first insulating layer away from the second structure portion, and the orthogonal projection of the first gate on the substrate may not overlap with the orthogonal projection of at least one of the first electrode, the second electrode, and the active layer on the substrate.

[0051] By vertically arranging the first electrode, second electrode, and active layer of a transistor, and setting the active layer as a first groove structure with a first gate disposed within the groove structure, the contact area between the active layer and the first gate can be increased. This allows for a further increase in channel length, improving carrier mobility in the active layer. It also increases the contact area between the active layer and the source and drain electrodes, enhancing conductivity between the source / drain electrodes and the active layer, thereby improving transistor performance. The channel length of the transistor is less affected by the contact area between the source / drain electrodes and the active layer. Therefore, the short-channel effect can be suppressed by increasing the thickness of the second structure, and the transistor volume can be reduced by decreasing the surface area of ​​at least one of the first electrode, second electrode, first structure, and second structure, thus reducing manufacturing costs. Furthermore, the first electrode, second electrode, and active layer can be directly fabricated using more controllable processes such as thin-film growth, improving the accuracy of the channel length and facilitating transistor size reduction to meet the miniaturization requirements of semiconductor devices.

[0052] In some feasible implementations, the transistor further includes:

[0053] The second groove structure penetrates the second electrode, and one end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part.

[0054] A second gate is provided within the second groove structure. The second gate is insulated from the active layer and from the first electrode.

[0055] For example, a second insulating layer is disposed between the second gate and the active layer. One end of the second insulating layer covers the side of the second electrode away from the substrate layer, and the other end of the second insulating layer covers the side of the first electrode away from the substrate layer. The orthogonal projection of the second electrode on the substrate layer falls on the orthogonal projection of the first electrode on the substrate layer.

[0056] Figure 2 This is a schematic structural diagram of another transistor provided in an embodiment of this application. (See diagram below.) Figure 2 As shown, the transistor includes a substrate layer 210, a first electrode 220, a second electrode 230, and an active layer 240, wherein the active layer 240 includes a first structural portion 241, a second structural portion 242, a third structural portion 243, a first gate 250, and a second gate 260.

[0057] A second gate is disposed within the second recessed structure, which, together with the first gate, forms a dual-gate transistor. Since the transistor generates an electric field by applying a voltage to the gate, the carrier concentration within the channel can be controlled by this electric field, thereby enabling control of the transistor's on / off states. Therefore, compared to a single-gate transistor, the dual-gate transistor has a larger channel region. When an electric field is generated by applying a voltage, the control force of the electric field on the carriers can be effectively improved, thus enhancing the transistor's gate control capability, mitigating short-channel effects, and ultimately improving the transistor's practicality and conductivity.

[0058] In some feasible implementations, the active layer includes a first active layer and a second active layer, and the orthographic projections of the first active layer and the second active layer onto the substrate layer do not overlap.

[0059] The second electrode includes a first sub-electrode and a second sub-electrode, and the orthogonal projections of the first sub-electrode and the second sub-electrode onto the substrate layer do not overlap.

[0060] For example, the first gate includes a first sub-gate and a second sub-gate. The first active layer and the second active layer belong to the first transistor and the second transistor, respectively.

[0061] For example, Figure 3 This is a schematic structural diagram of yet another transistor provided in an embodiment of this application. (See diagram below.) Figure 3 As shown, the transistor includes a substrate layer 310, a first electrode 320, a first sub-electrode 331, a second sub-electrode 332, a first active layer 341, a second active layer 342, a first sub-gate 351, a second sub-gate 352, and a second gate 360.

[0062] It is understandable that, such as Figure 3 As shown, the second groove structure is disposed between two transistors to connect them and provide insulation between them. When at least two transistors are disposed on the same substrate layer, the distance between them can be reduced, thus meeting the miniaturization requirements of semiconductor devices. At least two transistors can be connected via this interconnection method, allowing them to share a first electrode and a second gate. Therefore, during fabrication, only the first electrode and second gate need to be fabricated once, reducing fabrication difficulty, simplifying fabrication steps, improving fabrication efficiency, reducing fabrication costs, and enhancing the practicality of the transistors.

[0063] In some feasible implementations, the orthogonal projection of the active layer onto the substrate surrounds the orthogonal projection of the second groove structure onto the substrate.

[0064] Figure 4 This is a schematic cross-sectional view of a transistor provided in an embodiment of this application. Figure 4As shown in the cross-sectional view of the transistor, it includes a substrate layer 410, a first electrode 420, a second electrode 430, an active layer 440, a first gate 450, and a second gate 460.

[0065] For example, the orthogonal projection of the active layer onto the substrate can partially surround the orthogonal projection of the second recess structure onto the substrate. The shape of the transistor can be changed by altering the way the active layer surrounds the second recess structure, and / or by changing the shape of the second recess structure, thereby increasing the diversity of transistor shapes to adapt to different semiconductor devices.

[0066] For example, the size of the transistor can be adjusted by changing the shape of the second gate within the second recessed structure. For instance, the second gate can be a columnar structure or a recessed structure. A columnar structure occupies less space than a recessed structure; therefore, the size of the transistor can be reduced by setting the second gate to a columnar structure. However, a recessed structure has a larger contact area with the active layer; therefore, the control capability of the second gate over the transistor can be increased by using a recessed structure.

[0067] For example, by increasing the projected area of ​​the second gate on the second electrode, the contact area between the second gate and the active layer can be increased, thereby improving the control capability of the second gate over the carriers in the active layer and improving the gate control capability and performance of the transistor.

[0068] By surrounding the active layer with the second groove structure, the carriers in the entire active layer can be controlled solely through the second gate within the second groove structure. This reduces the volume of the second gate, saves on its fabrication cost, meets the requirements for miniaturization of semiconductor devices, and increases the diversity of transistor shapes to adapt to the structures of different semiconductor devices.

[0069] In some feasible implementations, one end of the second gate covers the side of the first sub-electrode away from the substrate, and the other end of the second gate covers the side of the second sub-electrode away from the substrate.

[0070] Figure 5 This is a schematic structural diagram of another transistor provided in an embodiment of this application. Figure 5 As shown, Figure 5 Based on Figure 4 The provided transistor features an improvement on the second gate. The transistor includes a substrate layer 510, a first electrode 520, a second electrode 530, an active layer 540, a first gate 550, and a second gate 560.

[0071] By covering the first and second sub-electrodes on the side away from the substrate, the overlap area of ​​the orthogonal projection of the second gate onto the substrate and the orthogonal projection of the third structure onto the substrate can be increased. This increases the contact area between the second gate and the active layer, enhances the control of the second gate over the carriers in the active layer, improves the gate control capability of the transistor, alleviates the short-channel effect, and ultimately improves the practicality and conductivity of the transistor.

[0072] In some feasible implementations, the transistor further includes:

[0073] The second gate covers the side surface of the second structure in the vertical direction.

[0074] Figure 6 This is a schematic structural diagram of a transistor provided for an embodiment of this application. For example... Figure 6 As shown, the transistor includes a substrate layer 610, a first electrode 620, a second electrode 630, an active layer 640, a first gate 650, and a second gate 660.

[0075] By covering the side surface of the second structure in the vertical direction with the second gate, a dual-gate transistor can be formed together with the first gate. Compared with a single-gate transistor, the channel region of a dual-gate transistor is larger. When an electric field is formed by applying a voltage, the control force of the electric field on the charge carriers can be effectively improved, thereby improving the gate control capability of the transistor, mitigating the short-channel effect, and thus improving the practicality and conductivity of the transistor.

[0076] In some feasible implementations, the first gate includes a fourth structural portion, a fifth structural portion, and a sixth structural portion. The fourth structural portion is disposed on the side of the first structural portion away from the substrate layer, the sixth structural portion is disposed on the side of the third structural portion away from the second electrode, and the fifth structural portion is connected between the fourth structural portion and the sixth structural portion. The fourth structural portion, the fifth structural portion, and the sixth structural portion form a third groove structure, and the opening of the third groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0077] An insulating layer is disposed between the first gate and the active layer.

[0078] Figure 7 This is a schematic structural diagram of another transistor provided in an embodiment of this application. (See diagram below.) Figure 7 As shown, the transistor includes a substrate layer 710, a first electrode 720, a second electrode 730, and an active layer 740, wherein the active layer 740 includes a first structural portion 741, a second structural portion 742, and a third structural portion 743, and a first gate 750, wherein the first gate 750 includes a fourth structural portion 751, a fifth structural portion 752, and a sixth structural portion 753.

[0079] By setting the first gate as a third groove structure, the contact area between the first gate and the active layer can be further increased, thereby expanding the channel region, accelerating the channel formation speed, improving the gate control capability of the transistor, and thus improving the practicality of the transistor.

[0080] Figure 8 This is a schematic flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application. Figure 8 As shown in the embodiments of this application, a method for fabricating a transistor is also provided, comprising:

[0081] Step S810: Sequentially deposit a first electrode and a second electrode on one side of the substrate layer;

[0082] Step S820: An active layer is provided between the first electrode and the second electrode, wherein the active layer includes a first structural portion, a second structural portion and a third structural portion, the first structural portion is electrically connected to the first electrode, the third structural portion is electrically connected to the second electrode, the second structural portion is connected between the first structural portion and the third structural portion, the first structural portion, the second structural portion and the third structural portion form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0083] Step S830: A first gate is disposed in the first groove structure, and the first gate is insulated from the active layer.

[0084] The transistor fabrication method involves vertically arranging the first electrode, second electrode, and active layer, with the active layer configured as a first recessed structure and the first gate disposed within this recessed structure. This increases the contact area between the active layer and the first gate, thereby further increasing the channel length and improving carrier mobility in the active layer. It also increases the contact area between the active layer and the source and drain electrodes, enhancing conductivity between the source / drain electrodes and the active layer, thus improving transistor performance. The channel length is less affected by the contact area between the source / drain electrodes and the active layer, allowing for the suppression of short-channel effects by increasing the thickness of the second structure. Furthermore, reducing the surface area of ​​at least one of the first electrode, second electrode, first structure, and second structure can decrease the transistor's size and fabrication cost. Moreover, the first electrode, second electrode, and active layer can be fabricated directly using more controllable processes such as thin-film growth, improving the accuracy of the channel length and facilitating transistor size reduction to meet the miniaturization requirements of semiconductor devices.

[0085] In some feasible implementations, an active layer is disposed between the first electrode and the second electrode, including:

[0086] A first insulating layer is disposed on the side of the first electrode away from the substrate layer;

[0087] A second electrode layer is disposed on the side of the insulating layer away from the substrate layer;

[0088] At least a portion of the second electrode layer and at least a portion of the insulating layer are removed sequentially to obtain a second electrode and an insulating structure;

[0089] Remove the insulation structure;

[0090] An active layer structure is placed at the location of the insulation structure;

[0091] A portion of the active layer structure is removed to form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode.

[0092] For example, at least a portion of the second electrode layer and at least a portion of the insulating layer can be removed sequentially by an etching process. The insulating structure can be photoresist, and the insulating structure can be removed by dissolving the photoresist. The active layer structure, the first gate dielectric layer, and the first gate can be prepared sequentially by a thin-film deposition process that maintains the three-dimensional morphology, for example, an atomic layer deposition process. The first gate, the first gate dielectric layer, and the active layer structure can be removed sequentially by a directional etching process to obtain an active layer with a first groove structure.

[0093] First, an insulating structure is prepared to occupy space for the active layer structure, which makes it easier to set the thickness of the active layer. Since the second electrode is a metal electrode, it is usually set by magnetron sputtering. Therefore, setting the active layer after the second electrode is set can avoid the large energy carried by metal atoms falling into the surface of the active layer when the second electrode is set on the side of the active layer away from the substrate, which can easily cause interface state defects. This can improve the integrity of the interface between the active layer and the second electrode, thereby improving the conductivity and practicality of the transistor.

[0094] In some feasible implementations, the method further includes the following steps prior to the removal of the insulation structure:

[0095] A second groove structure is provided, which penetrates the second electrode, and the end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part.

[0096] A second insulating layer is provided within the second groove structure;

[0097] A second gate is disposed within the second groove structure, and a second insulating layer is spaced between the second gate and the first electrode.

[0098] By first setting the second groove structure, the positions of the first and second electrodes can be fixed before the insulation structure is removed, preventing the second electrode from shifting without support and avoiding the second electrode from shifting during the fabrication of the active layer. This would reduce the controllability of the transistor's channel length, thereby improving the accuracy of the transistor's channel length and enhancing the effectiveness and practicality of the fabrication method.

[0099] For example, Figure 9 This is a schematic flowchart illustrating another method for fabricating a transistor according to an embodiment of this application. Figure 9 As shown, a method is provided as follows Figure 6 The diagram illustrates a schematic flowchart of the transistor fabrication method. First, a first electrode layer is deposited on one side of a substrate 910, and the first electrode layer is etched to obtain a first electrode structure. An insulating layer and a second electrode layer are sequentially disposed on the side of the first electrode away from the substrate 910, and the first electrode structure, the second electrode layer, and the insulating layer are sequentially etched to obtain a first electrode 920, a second electrode 930, and an insulating structure. A second insulating layer is disposed on the surfaces of the first electrode 920 and the second electrode 930 away from the substrate 910, and on the side surfaces of the insulating structure in the thickness direction. A second gate 960 is disposed on the side of the second insulating layer away from the insulating structure. The insulating structure is removed, and an active layer structure is disposed within the region of the insulating structure. The active layer structure is etched to obtain an active layer 940 with a first groove structure. A third insulating layer structure and a first gate structure are sequentially disposed within the first groove structure, and the third insulating layer structure and the first gate structure are sequentially etched to obtain a third insulating layer with a groove structure and a first gate 950.

[0100] For example, Figure 10 This is a schematic flowchart illustrating another method for fabricating a transistor, as provided in an embodiment of this application. Figure 10 As shown, a method is provided as follows Figure 5The diagram shows a schematic flowchart of the transistor fabrication method. First, a first electrode layer is deposited on one side of the substrate layer 1010, and the first electrode layer is etched to obtain a first electrode structure. An insulating layer and a second electrode layer are sequentially disposed on the side of the first electrode away from the substrate layer 1010, and the first electrode structure, the second electrode layer, and the insulating layer are sequentially etched to obtain a first electrode 1020, a first sub-electrode 1030, a second sub-electrode 1030, a first insulating structure, and a second insulating structure. A second insulating layer is disposed on the surface of the first electrode, the first electrode, and the first sub-electrode away from the substrate layer, and on the side surface of the insulating structure in the thickness direction. A second gate 1060 is disposed on the side of the second insulating layer away from the insulating structure. The insulating structure is removed, and a first active layer structure and a second active layer structure are disposed in the regions of the first and second insulating structures. The first and second active layer structures are etched to obtain a first active layer 1040 and a second active layer 1040 with a first groove structure. A third insulating layer structure and a first gate structure are sequentially disposed within the first groove structure, and the third insulating layer structure and the first gate structure are sequentially etched to obtain a third insulating layer and a first gate 1050 with a groove structure.

[0101] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0102] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0103] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A transistor, characterized in that, include: Substrate layer; The first electrode is disposed on one side of the substrate layer; The second electrode is disposed on the side of the first electrode away from the substrate layer; An active layer is disposed between the first electrode and the second electrode. The active layer includes a first structural portion, a second structural portion, and a third structural portion. The first structural portion is electrically connected to the first electrode, the third structural portion is electrically connected to the second electrode, and the second structural portion is connected between the first structural portion and the third structural portion. The first structural portion, the second structural portion, and the third structural portion form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode. A first gate is disposed within the first groove structure, and the first gate is insulated from the active layer; Wherein, the first structural portion is located between the first electrode and the first gate, and the third structural portion is located between the second electrode and the first gate; The second groove structure penetrates the second electrode, and one end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part. A second gate is disposed within the second groove structure. The second gate and the first gate together form a dual-gate transistor. The second gate is insulated from the active layer and from the first electrode. The second groove structure is disposed between two transistors to connect the two transistors, wherein, in the case where at least two transistors are disposed on the same substrate layer, the at least two transistors share a first electrode and a second gate.

2. The transistor as claimed in claim 1, characterized in that, The active layer includes a first active layer and a second active layer, and the orthographic projections of the first active layer and the second active layer on the substrate layer do not overlap. The first active layer and the second active layer are respectively located on both sides of the second groove structure. The second electrode includes a first sub-electrode and a second sub-electrode, and the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate do not overlap. The first sub-electrode and the second sub-electrode are respectively located on both sides of the second groove structure.

3. The transistor as claimed in claim 1, characterized in that, The orthogonal projection of the active layer on the substrate surrounds the orthogonal projection of the second groove structure on the substrate.

4. The transistor as claimed in claim 2, characterized in that, One end of the second gate covers the side of the first sub-electrode away from the substrate, and the other end of the second gate covers the side of the second sub-electrode away from the substrate.

5. The transistor as claimed in claim 1, characterized in that, Also includes: The second gate covers the side of the second structure that is away from the first structure.

6. The transistor as claimed in claim 1, characterized in that, The first gate includes a fourth structural portion, a fifth structural portion, and a sixth structural portion. The fourth structural portion is disposed on the side of the first structural portion away from the substrate layer, and the sixth structural portion is disposed on the side of the third structural portion away from the second electrode. The fifth structural portion is connected between the fourth structural portion and the sixth structural portion. The fourth structural portion, the fifth structural portion, and the sixth structural portion form a third groove structure. The opening of the third groove structure faces a direction perpendicular to the thickness direction of the first electrode. An insulating layer is disposed between the first gate and the active layer.

7. A method for fabricating a transistor, characterized in that, include: A first electrode and a second electrode are sequentially disposed on one side of the substrate layer; An active layer is disposed between the first electrode and the second electrode, wherein the active layer includes a first structural portion, a second structural portion and a third structural portion, the first structural portion is electrically connected to the first electrode, the third structural portion is electrically connected to the second electrode, the second structural portion is connected between the first structural portion and the third structural portion, the first structural portion, the second structural portion and the third structural portion form a first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode; A first gate is disposed within the first groove structure, and the first gate is insulated from the active layer; Wherein, the first structural portion is located between the first electrode and the first gate, and the third structural portion is located between the second electrode and the first gate; A second groove structure is provided, which penetrates the second electrode, and one end of the second groove structure near the substrate abuts against the side of the first electrode away from the substrate. The sidewall of the second groove structure is connected to the second structural part. A second insulating layer is provided within the second groove structure; A second gate is disposed within the second groove structure, and the second gate and the first gate together form a dual-gate transistor. A second insulating layer is spaced between the second gate and the first electrode. The second groove structure is disposed between two transistors to connect the two transistors, wherein, in the case where at least two transistors are disposed on the same substrate layer, the at least two transistors share a first electrode and a second gate.

8. The method for fabricating a transistor as described in claim 7, characterized in that, The provision of an active layer between the first electrode and the second electrode includes: A first insulating layer is disposed on the side of the first electrode away from the substrate layer; A second electrode layer is disposed on the side of the insulating layer away from the substrate layer; At least a portion of the second electrode layer and at least a portion of the insulating layer are removed sequentially to obtain the second electrode and the insulating structure; Remove the insulation structure; The active layer structure is disposed at the location of the insulating structure; A portion of the active layer structure is removed to form the first groove structure, and the opening of the first groove structure faces a direction perpendicular to the thickness direction of the first electrode.

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