Timer circuit for reducing the effects of transmission delay

Abstract

The application discloses a Timer circuit for reducing transmission delay influence, comprising a reset module and a comparator module; the reset module and the comparator module are respectively provided with two-stage inverters and switch tubes to form a pre-bias starting circuit.When a synchronous signal recovers from an abnormal state to a normal state, a logic circuit of a driver can generate a reset signal again, and after the Timer receives the reset signal, two-stage inverting logic in the pre-bias starting circuit can make a switch tube of the comparator module conductive, so that the level of an output end can be quickly reversed, and the time required for the driver to recover to work again can be greatly reduced. Since the pre-bias starting technology directly acts on the output end of the Timer, the delay influence caused by the discharge time of a large capacitor and the transistor parasitic effect of a logic link can be directly avoided.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to a Timer circuit for reducing the influence of transmission delay. BACKGROUND

[0002] As an important component in an isolated DC / DC switching power supply, a driver receives a pulse synchronization signal of a PWM controller, and outputs a signal for driving and controlling a switch tube and a freewheeling tube. A timer applied in the driver is a circuit for detecting whether the synchronization signal is correct. When the synchronization signal (SYNC) is correct, a logic part in the driver periodically transmits a reset signal to the timer. When the synchronization signal (SYNC) is incorrect or has a level lower than a requirement, the logic part in the driver stops outputting the reset signal, the timer enters a timeout state, and then indicates the driver to stop. When the synchronization signal recovers from an abnormal state to a normal state, the logic circuit of the driver generates a reset signal again, and the leakage tube of the reset module of the timer is turned on to make the charge in a large capacitor leak to the ground. If the abnormal state of the synchronization signal lasts for a long time, the timer in the timeout mode continuously charges the capacitor, which leads to a long discharging time of the capacitor when the timer re-enters the normal mode.

[0003] Due to the problems of a long discharging time of a large capacitor and a parasitic capacitance effect of a transistor in a multi-stage logic gate in a traditional structure, the timer cannot timely and effectively realize a level inversion of an output signal, which leads to a long delay of the stop state of the driver and affects the working efficiency and reliability of the isolated power supply. The existing technology also improves the circuit for the problem, but there are still some problems. For the problem of a long discharging time of a large capacitor, the existing technology selects a larger size leakage tube to accelerate the discharging of the capacitor, but this is not the best choice. First, the large size leakage tube improves the charge leakage capability and shortens the discharging time of the capacitor, but increases the additional power consumption of the chip in a high-voltage and large-current case. Second, if the overcurrent of the leakage tube is too strong and the capacitor discharges too fast, a current surge phenomenon occurs at the input end of the timer, and if the situation is serious, the overall circuit of the timer fails or is burned out. For the problem of the parasitic capacitance effect of the transistor in the multi-stage logic gate, the existing technology selects a smaller size process to reduce the parasitic capacitance effect of the transistor, and of course, the delay of the signal transmission link also becomes smaller, but this not only increases the cost of the circuit product, but also does not improve the problem of the large capacitor in the timer affecting the response speed of the output end of the timer. SUMMARY

[0004] The purpose of the present application is to reduce the influence of transmission delay by using pre-biased starting technology, eliminate the influence of capacitor discharge time and link delay on the response speed of the output end of the Timer, and quickly convert the output end of the Timer from low to high when the synchronization signal is restored to normal, so that the driver can quickly recover from the protection shutdown state.

[0005] To achieve the above purpose, the Timer circuit for reducing the influence of transmission delay comprises a reset module and a comparator module; the reset module comprises an RC charging and discharging network and an inverter, the RC charging and discharging network comprises a capacitor C1, a resistor R2 and a transistor MN15; the first end of the resistor R2 is connected to the power supply voltage VCC, the second end is connected to the first end of the capacitor C1; the second end of the capacitor C1 is grounded; the second end of the resistor R2 and the drain of the transistor MN15 are connected to the input signal V TIMER ; the gate of the transistor MN15 is connected to the inverter; the source of the transistor MN15 is grounded; the comparator module comprises a comparator circuit and a switch tube MP6 connected in series, the gate of the switch tube MP6 is connected to the Reset_bar port, the source is connected to the power supply, and the drain is connected to the comparator circuit; the inverter is a two-stage inverter; the comparator circuit comprises transistors MP8, MP9, MN7, MN8, MN10, MP10 and MN12; the gate of the transistor MP8 is connected to the first end of the capacitor C1, the source is connected to node f, and the drain is connected to node g; the gate of the transistor MN7 is connected to node g, the source is grounded, and the drain is connected to node g; the gate of the transistor MP9 is connected to the timeout threshold voltage, the source is connected to node f, and the drain is connected to node j; the gate of the transistor MN8 is connected to node g, the drain is connected to the drain of the transistor MP9, and the source is connected to the ground; the gate of the transistor MN10 is connected to node j, the drain is connected to node h, and the source is connected to the ground; the gate of the transistor MP10 is connected to node h, the source is connected to the input signal Vg, and the drain is connected to the output V OUT1 ; the gate of the transistor MN12 is connected to node h, the drain is connected to the output V OUT1 , and the source is grounded; node e is connected to the power supply voltage VCC.

[0006] Further, the two-stage inverter comprises a transistor MP11, a transistor MP12, a transistor MN13 and a transistor MN14, the gate of the transistor MP11 and the transistor MN13 is connected with an input signal Reset, the drain of the transistor MP11 is connected with the drain of the transistor MN13, and the source of the transistor MP11 and the transistor MN13 is connected with a power supply VCC and a ground terminal GND respectively; the gate of the transistor MP12 and the transistor MN14 is connected with a Reset_bar port and the drain of the transistor MP11 and MN13, the drain of the transistor MP12 is connected with the drain of the transistor MN14, and the source of the transistor MP12 and MN14 is connected with the power supply VCC and the ground terminal GND respectively, and the gate of the transistor MN15 is connected with the drain of the transistor MP12 and MN14.

[0007] Further, the drain of the transistor MN15 is connected with the negative electrode of a clamping diode, and the positive electrode of the clamping diode is connected with the ground.

[0008] Further, the current source module for providing a mirror reference current for the comparator module is further included.

[0009] Further, the current source module comprises a transistor MP1, a transistor MP4 and a transistor MP5, and the transistor MP1, the transistor MP4 and the transistor MP5 constitute a current mirror structure.

[0010] Further, the source of the transistor MP1 is connected with a node e, the gate and the drain are connected with an input signal Vg; the source of the transistor MP4 is connected with the node e, the gate is connected with the input signal Vg, and the drain is connected with a node f; the source of the transistor MP5 is connected with the node e, the gate is connected with the input signal Vg, and the drain is connected with a node h.

[0011] Compared with the prior art, the present application has at least the following beneficial technical effects:

[0012] The present application comprises a reset module and a comparator module for reducing the influence of transmission delay and a current source module for providing a reference mirror current, and the reset module and the comparator module are respectively added with a two-stage inverter and a switch tube to constitute a pre-bias starting circuit. When a synchronous signal recovers from an abnormal state to a normal state, the logic circuit of the driver can generate a reset signal again, and after the reset signal is received by the Timer, the two-stage inverter logic in the pre-bias starting circuit can make the switch tube of the comparator module conduct, and the level of the output end can be quickly reversed, so that the time required for the driver to recover to work is greatly reduced. Since the pre-bias starting technology directly acts on the output end of the Timer, the delay influence caused by the discharge time of the large capacitor and the transistor parasitic effect of the logic link is directly avoided, and the working efficiency and the reliability of the synchronous rectifier driver in the isolated DC / DC power supply are improved. In addition, in most of the working cycle time, the pre-bias starting circuit will automatically enter the sleep mode, and will not cause additional power consumption and functional influence to the Timer as a whole. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of a Timer that uses pre-biased startup technology. Detailed Implementation

[0014] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0015] The following detailed description is exemplary and intended to provide further detailed explanation of the invention. Unless otherwise specified, all technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this invention is for describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention.

[0016] like Figure 1 As shown, the Timer circuit involved in this invention consists of three modules: a reset module to reduce the impact of transmission delay, a comparator module, and a current source module to provide a reference mirror current. The reset module and comparator module incorporate multi-stage inverting circuits and switching control circuits to achieve pre-biased startup technology based on the traditional structure. This eliminates the influence of capacitor discharge time and link delay on the Timer's output response speed. When the synchronization signal returns to normal, the Timer output can quickly transition from low to high level, enabling the driver to recover from the protection shutdown state more quickly and improving the efficiency and reliability of the synchronous rectifier driver in the isolated DC / DC power supply.

[0017] The reset module includes an RC charging network, a two-stage inverter, and a clamping diode. The RC charging network consists of a capacitor C1, a resistor R2, and a transistor MN15. The two-stage inverter consists of transistors MP11, MP12, MN13, and MN14. The clamping diode consists of diode D. Z constitute.

[0018] The first terminal of resistor R2 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of capacitor C1; the second terminal of capacitor C1 is grounded; the second terminal of resistor R2 and the first terminal of capacitor C1 are connected to the input signal V. TIMER; the gate of transistor MP11 and transistor MN13 is connected with input signal Reset, the drain of transistor MP11 is connected with the drain of transistor MN13, and the source of transistor MP11 and transistor MN13 is connected with power supply VCC and ground terminal GND respectively; the gate of transistor MP12 and transistor MN14 is connected with reset feedback control Reset_bar port and the drain of transistor MP11 and MN13, the drain of transistor MP12 is connected with the drain of transistor MN14, and the source of transistor MP12 and MN14 is connected with power supply VCC and ground terminal GND respectively; the source of transistor MN15 is connected with ground, the drain is connected with the cathode of diode D Z , and the gate is connected with the drain of transistor MP12 and MN14; the anode of diode D Z is connected with ground.

[0019] The reset module is used for providing input voltage V TIMER for the comparator module and providing Reset_bar gate control signal for switch transistor MP6.

[0020] The power supply voltage VCC, capacitor C1 and resistor R2 in the reset module constitute a charging network, when the gate of transistor MN15 has no reset signal pulse, the power supply voltage VCC generates current through resistor R2 to directly charge capacitor C1, and the voltage of capacitor C1 is equal to the input voltage V TIMER of Timer, which will slowly rise; MP11, MP12, MN13 and MN14 constitute two-stage inverters, which are part of the pre-bias starting circuit. When Reset reset signal comes, the gate of transistor MP11 and transistor MN13 receives Reset reset signal, and after the first-stage inverter, the signal output is respectively given to the second-stage inverter composed of MP12 and transistor MN14 and the gate of switch transistor MP6 of the comparator module. After the Reset reset signal passes through the two-stage inverters, it acts on the gate of the leakage transistor MN15, and after the leakage transistor MN15 is turned on, the charge in the large capacitor C1 is leaked to the ground, and the voltage of the capacitor will also decrease rapidly. As the receiving end of the reset signal in the Timer circuit, the two-stage inverters not only play a buffering and isolating role in the logic module and Timer, but also increase the driving capacity of the reset signal and automatically synchronize the turn-on and turn-off of switch transistor MP6. When the synchronization signal recovers to normal, this is the first time when the Reset reset signal is established, and Timer can make the output end quickly respond through transistor MP11, transistor MP12 and switch transistor MP6 of the comparator module, realize the fast level inversion, and eliminate the influence of the discharge time of large capacitor C1 and the delay of transmission link; the main function of diode D Z is to provide V TIMERThe voltage clamping effect, because when the synchronization signal is abnormal, the driver logic part will no longer produce Reset reset signal, large capacitor C1 will continue to charge resulting in its voltage V TIMER Very high, it is necessary to introduce diode D Z The limit, avoid the next Reset reset signal to come when the capacitor C1 discharge time too long, this will improve the response speed of the Timer in normal state.

[0021] The comparator module is composed of comparator circuit and pre-biased switch MP6, such as P-channel enhancement MOSFET; the comparator is composed of transistor MP8, transistor MP9, transistor MN7, transistor MN8, transistor MN10, transistor MP10, transistor MN12.

[0022] The gate of transistor MP8 is connected to node c, the source is connected to node f, and the drain is connected to node g; the gate of transistor MN7 is connected to node g, the source is connected to ground, and the drain is connected to node g; the gate of transistor MP9 is connected to the timeout threshold voltage, the source is connected to node f, and the drain is connected to node j; the gate of transistor MN8 is connected to node g, the drain is connected to the drain of transistor MP9, and the source is connected to ground; the gate of transistor MN10 is connected to node j, the drain is connected to node h, and the source is connected to ground; the gate of transistor MP10 is connected to node h, the source is connected to node e, and the drain is connected to output V OUT1 ; the gate of MN12 is connected to node h, the drain is connected to output V OUT1 , and the source is connected to ground; node e is connected to power voltage VCC; the gate of switch MP6 is connected to Reset_bar port, the source is connected to node e, and the drain is connected to node h.

[0023] The comparator module is used to compare the size of input voltage V TIMER and timeout threshold voltage, and output high or low level signal according to the comparison result.

[0024] Since the gate of transistor MP9 is connected to the timer timeout threshold voltage, which is 0.2VCC, and the input voltage V TIMER is connected to the transistor MP8, the comparator will compare the two voltages, and with the change of V TIMER , transistor MN10 will output digital signals of high and low levels; the inverter composed of transistor MP10 and transistor MN12 mainly plays the role of isolation and shaping. When V TIMER < 0.2VCC, the gate potential of transistor MN10 is low, and transistor MN10 is cut off, at this time the potential of point h of the drain of MN10 is high, and after passing through the inverter composed of MP10 and MN12, it is low level, which represents that the synchronization signal is completely normal, and the driver will not be turned off; when V TIMERWhen the voltage is greater than 0.2VCC, the gate potential of transistor MN10 is high, the transistor is turned on, the potential of point h is low, and the high level is obtained when passing through the inverter, at this time, the synchronization signal is abnormal, the reset pulse of Timer is not obtained, and the timeout phenomenon of Timer occurs, that is, V TIMER When the voltage is greater than the timeout threshold voltage, the driver is turned off. When the comparator is in the above working state, the switch transistor MP6 is in the dormant mode, and does not affect the normal work of the Timer. When the synchronization signal recovers from the abnormality, the gate of the switch transistor MP6 receives the Reset_bar signal output by the reset module, and then turns on, the output end V OUT1 of the Timer is forced to be low, the high level to low level is quickly reversed, and the driver can be restarted in time and effectively.

[0025] The current source module is composed of three transistors: transistor MP1, transistor MP4 and transistor MP5. The transistor MP1, the transistor MP4 and the transistor MP5 constitute a current mirror structure. The source of the transistor MP1 is connected to node e, the gate is connected to the drain input signal Vg; the source of the transistor MP4 is connected to node e, the gate is connected to the input signal Vg, and the drain is connected to node f; the source of the transistor MP5 is connected to node e, the gate is connected to the input signal Vg, and the drain is connected to node h; the gate of the transistor MP1 is connected to the reference voltage Vg, the gates of the transistor MP4 and the transistor MP5. The gate of the transistor MP1 is connected to the reference voltage Vg, the transistor MP4 and the transistor MP5, the mirror current of the transistor MP1 is provided to the transistor MP8, the transistor MP9, the transistor MN7 and the transistor MN8, and the transistor MN10 provides a reference current.

[0026] According to the above description, it can be known that the pre-bias starting technology adopted by the application greatly improves the response rate of the output end of the Timer when recovering from the timeout mode to the normal mode, so that the driver recovers from the protection shutdown state more quickly, which effectively solves the problem that the large-capacitance discharge time and the parasitic capacitance effect of the transistors in the multi-stage logic gate in the traditional Timer circuit architecture cause the slow recovery of the driver.

[0027] The above is the preferred embodiment of the application, and is not used to limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A timer circuit for reducing the impact of transmission delay, characterized in that, Includes a reset module and a comparator module; The reset module includes an RC charging and discharging network and an inverter. The RC charging and discharging network includes a capacitor C1, a resistor R2, and a transistor MN15. The first terminal of resistor R2 is connected to the power supply voltage VCC, and the second terminal is connected to the first terminal of capacitor C1; the second terminal of capacitor C1 is grounded; the second terminal of resistor R2 and the drain of transistor MN15 are connected to the input signal V. TIMER The gate of transistor MN15 is connected to an inverter; the source of transistor MN15 is grounded. The comparator module includes a comparator circuit and a switching transistor MP6 that are electrically connected. The gate of the switching transistor MP6 is connected to the Reset_bar port, the source is connected to the power supply, and the drain is connected to the comparator circuit. The inverter is a two-stage inverter; The comparator circuit includes transistors MP8, MP9, MN7, MN8, MN10, MP10, and MN12; the gate of transistor MP8 is connected to the first terminal of capacitor C1, the source is connected to node f, and the drain is connected to node g. The gate of transistor MN7 is connected to node g, the source is grounded, and the drain is connected to node g. Transistor MP9 has its gate connected to the timeout threshold voltage, its source connected to node f, and its drain connected to node j; transistor MN8 has its gate connected to node g, its drain connected to the drain of transistor MP9, and its source connected to ground; transistor MN10 has its gate connected to node j, its drain connected to node h, and its source connected to ground; transistor MP10 has its gate connected to node h, its source connected to the input signal Vg, and its drain connected to the output Vg. OUT1 The gate of MN12 is connected to node h, and the drain is connected to the output V. OUT1 The source is grounded; node e is connected to the power supply voltage VCC.

2. The timer circuit for reducing transmission delay according to claim 1, characterized in that, The two-stage inverter includes transistors MP11, MP12, MN13, and MN14. The gates of transistors MP11 and MN13 are connected to the input signal Reset, the drain of transistor MP11 is connected to the drain of transistor MN13, and the sources of transistors MP11 and MN13 are connected to the power supply VCC and the ground terminal GND, respectively. The gates of transistors MP12 and MN14 are connected to the Reset_bar port and the drains of transistors MP11 and MN13. The drain of transistor MP12 is connected to the drain of transistor MN14. The sources of transistors MP12 and MN14 are connected to the power supply VCC and the ground terminal GND, respectively. The gate of transistor MN15 is connected to the drains of transistors MP12 and MN14.

3. The timer circuit for reducing transmission delay according to claim 1, characterized in that, The drain of the transistor MN15 is connected to the negative terminal of the clamping diode, and the positive terminal of the clamping diode is connected to ground.

4. The timer circuit for reducing transmission delay according to claim 1, characterized in that, It also includes a current source module for providing a mirror reference current to the comparator module.

5. The timer circuit for reducing transmission delay according to claim 4, characterized in that, The current source module includes transistor MP1, transistor MP4 and transistor MP5, which together form a current mirror structure.

6. The timer circuit for reducing transmission delay according to claim 5, characterized in that, The source of transistor MP1 is connected to node e, and its gate and drain are connected to the input signal Vg; the source of transistor MP4 is connected to node e, its gate is connected to the input signal Vg, and its drain is connected to node f; the source of transistor MP5 is connected to node e, its gate is connected to the input signal Vg, and its drain is connected to node h.

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