Semiconductor structure and method of making the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises: a plurality of memory cells, a plurality of word lines and a plurality of bit lines; the plurality of memory cells form an array, each memory cell comprises a memory structure and a transistor located above the memory structure; the transistor comprises a columnar gate, a dielectric layer and an active layer, the dielectric layer covers at least part of the sidewall and the bottom surface of the columnar gate, the active layer covers the sidewall of the dielectric layer, and the bottom surface of the active layer is electrically connected to the memory structure; each bit line extends along a second direction and is electrically connected to the active layers in the same column; each word line extends along a first direction and is electrically connected to the columnar gates in the same row; the first direction and the second direction intersect and are both perpendicular to the direction in which the columnar gate extends; the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor structure, a manufacturing method thereof and a memory. BACKGROUND

[0002] With the continuous reduction of the size of semiconductor devices such as memory, the storage cells (including transistors and storage structures) in the memory are facing process challenges and miniaturization challenges, and it is difficult to further miniaturize. How to optimize the structure of the storage cell and further miniaturize the size of the storage cell has become a problem to be solved. SUMMARY

[0003] Therefore, the present disclosure provides a semiconductor structure, a manufacturing method thereof and a memory.

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a plurality of storage cells, a plurality of word lines, and a plurality of bit lines; wherein,

[0005] The plurality of storage cells form an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, each of the storage cells comprising a storage structure and a transistor located above the storage structure; the transistor comprises a columnar gate, a dielectric layer, and an active layer, the dielectric layer covering at least part of the sidewall and the bottom surface of the columnar gate, the active layer covering the sidewall of the dielectric layer, and the bottom surface of the active layer being electrically connected to the storage structure.

[0006] Each of the bit lines extends along the second direction and is electrically connected to the sidewall of the active layer of the same column;

[0007] Each of the word lines extends along the first direction and is electrically connected to the top surface of the columnar gate of the same row; the first direction and the second direction intersect and are both perpendicular to the direction in which the columnar gate extends; the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or, the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction.

[0008] In the above scheme, the outer contour shape of the first cross section and / or the second cross section of the active layer comprises two legs and a bottom edge of a trapezoid; the first cross section comprises a cross section of the active layer along a plane in which the first direction and a third direction lie, the second cross section comprises a cross section of the active layer along a plane in which the second direction and the third direction lie, and the third direction is parallel to the direction in which the columnar gate extends.

[0009] In the above scheme, the size of the active layer along the third direction is less than the size of the columnar gate along the third direction.

[0010] In the above aspect, one of the source or the drain of the transistor is located at a top sidewall of the active layer, and the other of the source or the drain of the transistor is located at a bottom surface of the active layer.

[0011] In the above aspect,

[0012] The size of the columnar gate along the first direction decreases with the increase of the height of the columnar gate, and the size of the columnar gate along the second direction decreases with the increase of the height of the columnar gate.

[0013] Alternatively,

[0014] The size of the columnar gate along the first direction increases with the increase of the height of the columnar gate, and the size of the columnar gate along the second direction decreases with the increase of the height of the columnar gate.

[0015] In the above aspect, the storage structure comprises one of a capacitor, a thin film transistor, and a magnetic storage unit.

[0016] In the above aspect, the semiconductor structure further comprises a bit line isolation structure and a word line isolation structure; wherein,

[0017] The bit line isolation structure is located between the active layers of two adjacent columns arranged along the first direction.

[0018] The word line isolation structure is located between two adjacent word lines arranged along the second direction.

[0019] According to a second aspect of the present disclosure, a memory is provided, comprising a substrate, and at least one semiconductor structure as in any one of the above aspects above the substrate.

[0020] In the above aspect, the memory comprises a plurality of semiconductor structures, and the plurality of semiconductor structures are stacked in a direction perpendicular to the substrate.

[0021] In the above aspect, the substrate comprises a peripheral circuit, and the semiconductor structure is electrically connected to the peripheral circuit.

[0022] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0023] providing a substrate; and forming a plurality of storage structures in the substrate;

[0024] Forming a plurality of transistors on the memory structure, each of the memory structure corresponding to a transistor, the plurality of transistors constituting an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction; wherein the transistor comprises a columnar gate, a dielectric layer and an active layer, the dielectric layer covering at least part of the sidewall and the bottom surface of the columnar gate, the active layer covering the sidewall of the dielectric layer, and the bottom surface of the active layer being electrically connected to the memory structure;

[0025] Forming a bit line, the bit line extending along the second direction and being electrically connected to the sidewall of the active layer of the same column;

[0026] Forming a word line, the word line extending along the first direction and being electrically connected to the top surface of the columnar gate of the same row; the first direction and the second direction intersect and are both perpendicular to the direction in which the columnar gate extends; the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or, the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction.

[0027] In the above solution, before forming the transistor, the method further comprises:

[0028] Forming a sacrificial layer on the memory structure;

[0029] Forming a plurality of first grooves spaced along the first direction and filling the first grooves with a first insulating material; the first grooves penetrating the sacrificial layer;

[0030] Forming a plurality of second grooves alternately spaced along the second direction and filling the second grooves with a second insulating material; the second grooves penetrating the sacrificial layer;

[0031] Removing the remaining sacrificial layer to obtain an array of recesses having a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction, the bottom of each of the recesses exposing the top surface of each of the memory structures; the size of the bottom of each of the recesses along the first direction is greater than the size of the top of each of the recesses along the first direction, and the size of the bottom of each of the recesses along the second direction is greater than the size of the top of each of the recesses along the second direction.

[0032] In the above solution, before forming the transistor, the method further comprises:

[0033] Forming an insulating layer on the memory structure;

[0034] Forming a plurality of third grooves spaced along the first direction and filling the third grooves with a sacrificial material; the third grooves penetrating the insulating layer;

[0035] forming a plurality of fourth trenches alternatingly and spacedly arranged along the second direction and filling the fourth trenches with a third insulating material; the fourth trenches penetrating through the sacrificial material;

[0036] removing the remaining sacrificial material to obtain an array of recesses arranged along the first direction and along the second direction, each bottom of the recess exposing a top surface of each of the memory structures; a dimension of each of the recess bottoms along the second direction is greater than a dimension of each of the top surfaces along the second direction.

[0037] In the above aspect, forming the transistor comprises:

[0038] forming a semiconductor material covering sidewalls and a bottom wall of the recess;

[0039] forming a dielectric material covering sidewalls and a bottom wall of the semiconductor material;

[0040] forming the columnar gate covering sidewalls and a bottom wall of the dielectric material;

[0041] back-etching part of the dielectric material and part of the semiconductor material along a direction in which the columnar gate extends to form the active layer and the dielectric layer; the dielectric layer is between the columnar gate and the active layer and covers at least a surface of the active layer.

[0042] In the above aspect, forming the bit line comprises:

[0043] forming a first conductive material in a gap between the top portions of the active layer; the first conductive material surrounds sidewalls of and electrically connects the top portions of the active layer;

[0044] removing part of the first conductive material along the second direction to form a plurality of bit line isolation trenches spacedly arranged along the first direction, the bit line isolation trenches penetrating through the first conductive material along a direction in which the columnar gate extends; the first conductive material not removed constitutes the bit line.

[0045] In the above aspect, forming the word line comprises:

[0046] forming a second conductive material on top of the columnar gate; the second conductive material contacts and electrically connects a top surface of the columnar gate;

[0047] removing part of the second conductive material along the first direction to form a plurality of word line isolation trenches spacedly arranged along the second direction, the word line isolation trenches penetrating through the second conductive material along a direction in which the columnar gate extends; the second conductive material not removed constitutes the word line.

[0048] In the embodiments of the present disclosure, the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or, the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction. That is, the size of the bottom surface of the active layer is relatively large, so that the contact area between the bottom surface of the active layer and the storage structure can be larger, which is beneficial for better contact between the active layer and the storage structure to reduce the resistance; and the size of the top of the active layer is relatively small, so that the top of the active layer is more easily contacted by the bit line, and because the size of the top of the active layer is relatively small, the spacing between the top of the active layer is relatively large, which can reduce the parasitic capacitance between the subsequently formed bit lines and the word lines, can reduce the process difficulty of forming the bit line isolation trench and the word line isolation trench, and is more conducive to the formation of the bit line and the bit line isolation structure and the word line and the word line isolation structure, and thus the semiconductor structure can be further miniaturized. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 A circuit connection schematic diagram of a transistor of a dynamic random access memory provided in the embodiments of the present disclosure;

[0050] Figures 2a to 2d A sectional view schematic diagram of a semiconductor structure provided in the embodiments of the present disclosure;

[0051] Figures 3a to 3d A sectional view schematic diagram of another semiconductor structure provided in the embodiments of the present disclosure;

[0052] Figure 4 A flowchart schematic diagram of a manufacturing method of a semiconductor structure provided in the embodiments of the present disclosure;

[0053] Figures 5a to 13d A sectional view schematic diagram of a manufacturing process of a semiconductor structure provided in the embodiments of the present disclosure;

[0054] Figures 14a to 19d A sectional view schematic diagram of another manufacturing process of a semiconductor structure provided in the embodiments of the present disclosure;

[0055] Figure 20 A planar structure schematic diagram of a memory provided in the embodiments of the present disclosure.

[0056] In the above drawings (which are not necessarily drawn to scale), like numerals can describe similar components throughout the various figures. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0057] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to convey the scope of the present disclosure to those skilled in the art.

[0058] The present disclosure will be described in more detail with reference to the drawings in the following paragraphs. The advantages and features of the present disclosure will be more clearly understood from the following description and claims. It should be noted that the drawings are very simplified and all use non-precise proportions, only to facilitate, clear and assist in the purpose of illustrating the embodiments of the present disclosure.

[0059] It can be understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" something and there is no intervening feature or layer between them (i.e. directly on something), but also includes the meaning of "on" something and there is an intervening feature or layer between them.

[0060] In addition, for ease of description, spatial relative terms such as "on", "above", "over", "upper", "top" and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can likewise be interpreted accordingly.

[0061] In the embodiments of the present disclosure, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, arsenic, phosphorus, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic or sapphire wafer.

[0062] In embodiments of the disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Additionally, a layer can be a region of a continuous structure having a thickness that is less than the thickness of the continuous structure, whether the continuous structure is homogenous or heterogeneous. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0063] In embodiments of the disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence.

[0064] Embodiments of the disclosure relate to a semiconductor structure that is to be used in subsequent processes to form at least a portion of a final device structure. Here, the final device can include a memory, which includes but is not limited to a dynamic random access memory (DRAM). Hereinafter, only a dynamic random access memory is taken as an example for description.

[0065] It should be noted that the following embodiments described with respect to a dynamic random access memory are only used to illustrate the disclosure, and are not used to limit the scope of the disclosure.

[0066] With the development of dynamic random access memory technology, the size of a memory cell is getting smaller and smaller, and the array architecture thereof is evolving from an 8F 2 to a 6F 2 to a 4F 2 ; the architecture of the memory is evolving from a planar array transistor to a recess gate array transistor, from the recess gate array transistor to a buried channel array transistor, and from the buried channel array transistor to a vertical channel array transistor.

[0067] In some embodiments of the present disclosure, whether it is a planar transistor or a buried transistor, the dynamic random access memory includes a plurality of memory cells, each of which is mainly composed of a transistor and a storage structure (storage capacitor) controlled by the transistor, that is, the dynamic random access memory includes a 1 transistor (T) and 1 capacitor (C) (1T1C) architecture; the main principle of action is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0068] Figure 1 A control circuit schematic diagram using the 1T1C architecture provided in the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the drain of the transistor T is electrically connected to the bit line (BL), the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C can be connected to a reference voltage, which can be a ground voltage or other voltage, and the gate of the transistor T is connected to the word line (WL); the transistor T is controlled to be turned on or turned off by applying a voltage to the word line WL, and the bit line BL is used to perform read or write operations on the transistor T when the transistor T is turned on. Figure 1

[0069] However, in order to realize the miniaturization development of the memory, the size of the dynamic random access memory is continuously reduced, and the memory cells (including transistors and storage structures) in the memory cell array of the memory are facing process challenges and miniaturization challenges, and it is difficult to further miniaturize. For example, how to properly match the transistor with the bit line, the word line, and the storage structure to further miniaturize the size of the memory cell becomes a technical problem to be solved.

[0070] Based on this, in order to solve one or more of the above problems, according to an aspect of the present disclosure, as shown in FIG. 2, a semiconductor structure is provided, which includes a plurality of memory cells, a plurality of word lines 310, and a plurality of bit lines 307; wherein, Figures 2a to 3d

[0071] The plurality of memory cells constitute an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, each of the memory cells including a storage structure 201 and a transistor located above the storage structure 201; the transistor includes a columnar gate 306, a dielectric layer 305, and an active layer 304, the dielectric layer 305 covers at least part of the sidewall and the bottom surface of the columnar gate 306, the active layer 304 covers the sidewall of the dielectric layer 305, and the bottom surface of the active layer 304 is electrically connected to the storage structure 201;

[0072] Each of the bit lines 307 extends along the second direction and is electrically connected to the sidewall of the active layer 304 of the same column; ​​

[0073] Each of the word lines 310 extends along a first direction and is electrically connected to top surfaces of the columnar gates 306 in a same row; the first direction and the second direction are perpendicular to a direction in which the columnar gates 306 extend; a dimension of the active layer 304 bottom surface along the first direction is greater than a dimension of the active layer 304 top surface along the first direction; and / or, a dimension of the active layer 304 bottom surface along the second direction is greater than a dimension of the active layer 304 top surface along the second direction.

[0074] Here and hereinafter, the active layer bottom surface can also be understood as an active layer bottom portion, and the active layer top surface can also be understood as an active layer top portion.

[0075] In some embodiments, the dimension of the active layer bottom portion along the first direction is greater than the dimension of the active layer top portion along the first direction; and / or, the dimension of the active layer bottom portion along the second direction is greater than the dimension of the active layer top portion along the second direction. Here, the dimension of the active layer bottom portion along the first direction or the second direction can be understood as a minimum dimension of an outer contour of the active layer bottom portion along the first direction or the second direction, and the dimension of the active layer top portion along the first direction or the second direction can be understood as a maximum dimension of an outer contour of the active layer top portion along the first direction or the second direction.

[0076] Here and hereinafter, the first direction and the second direction are represented as two orthogonal directions perpendicular to a direction of the substrate thickness; and the third direction is parallel to the direction of the substrate thickness, that is, the third direction is a direction in which the columnar gates extend.

[0077] In some embodiments, an included angle between the first direction and the second direction ranges from 0 degree to 90 degree. In some specific embodiments, the first direction can be perpendicular to the second direction. It can be understood that the included angle between the first direction and the second direction establishes a positional relationship of an array of a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction.

[0078] Exemplarily, the first direction is represented as an X direction in the drawings; the second direction is represented as a Y direction in the drawings; and the third direction is represented as a Z direction in the drawings.

[0079] Figures 2a to 2d FIG. 1 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure; Figures 3a to 3d FIG. 2 is a schematic cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure.

[0080] The semiconductor structure provided in the embodiment of the present disclosure will be described in detail below. Figures 2a to 2d And Figures 3b to 3d , the semiconductor structure provided in the embodiment of the present disclosure will be described in detail.

[0081] For the purpose of clear description of the present disclosure, the following embodiments are described with the first direction being perpendicular to the second direction as an example. For example, Figures 2a to 2d the first direction is the X-axis direction shown in Figure 2c and Figure 2d the second direction is the Y-axis direction shown in Figure 2a and Figure 2b the third direction is the Z-axis direction shown in Figures 2a to 2d It should be noted that the description of the direction in the following embodiments is only for the purpose of illustrating the present disclosure, and does not limit the scope of the present disclosure.

[0082] It should be noted that Figures 2a to 3d each figure with the same number in the figures represents a schematic view of a plurality of cross-sectional planes of the same semiconductor structure; for example, Figures 2a to 2d , the A-A, B-B, C-C, and D-D cross-sectional views shown in Figures 2a to 2d respectively are cross-sectional schematic views along the A-A, B-B, C-C, and D-D cross-sectional directions of the same semiconductor structure, the A-A cross-section can be understood as a Y-Z plane that does not pass through the active layer 304, the B-B cross-section can be understood as a Y-Z plane that passes through the active layer 304, the C-C cross-section can be understood as an X-Z plane that passes through the active layer 304, and the D-D cross-section can be understood as an X-Z plane that does not pass through the active layer 304.

[0083] It can be understood that the semiconductor structure in the embodiments of the present disclosure is a transistor structure on the storage structure 201. For example, the storage structure 201 includes a capacitor, and the semiconductor structure in the above embodiments is a transistor on capacitor (TOC) structure.

[0084] It can be understood that the active layer 304 of the transistor in the above embodiments surrounds the columnar gate 306, forming a channel all around (GAA) structure.

[0085] It should be noted that the source S and the drain D are arranged at the opposite ends of the active layer 304 along the third direction, and the positions of the source S and the drain D can be interchanged; the source S and the drain D can be arranged according to actual needs.

[0086] Referring to Figures 2a to 2d , the size W1 of the bottom surface of the active layer 304 along the first direction is greater than the size W2 of the top surface of the active layer 304 along the first direction; and the size W3 of the bottom surface of the active layer 304 along the second direction is greater than the size W4 of the top surface of the active layer 304 along the second direction. That is, the size of the active layer 304 along the first direction is "narrow at the top and wide at the bottom", and the size of the active layer 304 along the second direction is "narrow at the top and wide at the bottom".

[0087] Reference Figures 3a to 3d , the size W5 of the active layer 304 bottom surface along the first direction is smaller than the size W6 of the active layer 304 top surface along the first direction; while the size W7 of the active layer 304 bottom surface along the second direction is larger than the size W8 of the active layer 304 top surface along the second direction. Alternatively, the size of the active layer bottom surface along the first direction is larger than the size of the active layer top surface along the first direction; while the size of the active layer bottom surface along the second direction is smaller than the size of the active layer top surface along the second direction (not shown in the embodiment of the present disclosure, which can be understood with reference to Figures 2a to 2d , specifically, replacing the active layer with "narrow on top and wide on bottom" in Figure 2b , Figure 2a , Figure 2c , Figure 2d may not change). That is, the size of the active layer 304 along the first direction is "narrow on top and wide on bottom", or the size of the active layer 304 along the first direction is "narrow on top and wide on bottom".

[0088] In practical applications, under the condition that the lithography pattern capable of achieving 1 / 2 minimum size (1 / 2Pitch) is certain, if it is desired to further reduce the minimum size to meet the requirements of higher density semiconductor structure, more suitable process technology can be developed. Exemplarily, as shown in Figures 2a to 2d , the minimum size P (the sum of the bit line minimum size P1 and the bit line isolation structure minimum size P2) is certain, due to the relatively small size of the top of the active layer 304, the relatively larger spacing between the top of the active layer 304, the top of the active layer 304 is more easily contacted by the bit line 307, that is, the bit line minimum size P1 can be as small as possible; relatively, the spacing between the top of the active layer 304 is relatively large, which is beneficial to increase the process window for forming the bit line isolation structure, that is, the bit line isolation structure minimum size P2 can be as large as possible. Similarly, the minimum size P (the sum of the word line minimum size P3 and the word line isolation structure minimum size P4) is certain, the word line minimum size P3 can be appropriately made as small as possible, and the word line isolation structure minimum size P4 can be made as large as possible. In this way, the parasitic capacitance between the subsequently formed bit lines and the word lines can be reduced, the process difficulty of forming the bit line isolation trench and the word line isolation trench can be reduced, and the formation of the bit line 307 and the bit line isolation structure and the word line 310 and the word line isolation structure is more beneficial.

[0089] In the embodiments of the present disclosure, the active layer has a size that is "narrow at the top and wide at the bottom" along the first direction, and / or the active layer has a size that is "narrow at the top and wide at the bottom" along the second direction, that is, the bottom size of the active layer is relatively large, so that the contact area between the bottom of the active layer and the storage structure can be larger, which is beneficial for better contact between the active layer and the storage structure to reduce the resistance; and the top size of the active layer is relatively small, so that the top of the active layer is more easily contacted by the bit line, and because the top size of the active layer is relatively small, the spacing between the top of the active layer is relatively large, which can reduce the parasitic capacitance between the subsequently formed bit lines and the word lines, can reduce the process difficulty of forming the bit line isolation groove and the word line isolation groove, and is more conducive to the formation of the bit line and the bit line isolation structure and the word line and the word line isolation structure, and thus the semiconductor structure can be further miniaturized.

[0090] In some embodiments, the outer contour shape of the first cross section and / or the second cross section of the active layer 304 includes two legs and a bottom of a trapezoid; the first cross section includes a cross section of the active layer 304 along a plane in which the active layer 304 extends along the first direction and a third direction, and the second cross section includes a cross section of the active layer 304 along a plane in which the active layer 304 extends along the second direction and the third direction, and the third direction is parallel to the direction in which the columnar gate 306 extends.

[0091] Here, the second cross section can be understood as a B-B cross section, and the B-B cross section can be understood as a Y-Z plane passing through the active layer 304. The first cross section can be understood as a C-C cross section, and the C-C cross section can be understood as an X-Z plane passing through the active layer 304.

[0092] The outer contour shape of the first cross section and / or the second cross section of the active layer 304 can also be other regular or irregular shapes, for example, the two legs of the trapezoid can be changed from straight lines to curves.

[0093] In some embodiments, the outer contour shape of the third cross section of the active layer 304 includes an ellipse or an elongated strip. The third cross section includes a cross section of the active layer 304 along a plane in which the active layer 304 extends along the first direction and the second direction, and can be understood as an X-Y plane passing through the active layer 304.

[0094] Here and in the following embodiments, the description of the cross section shape of the active layer 304 is only used to illustrate the present disclosure, and does not limit the scope of the present disclosure.

[0095] In some embodiments, the size of the active layer 304 along the third direction is smaller than the size of the columnar gate 306 along the third direction.

[0096] In some embodiments, one of the source or drain of the transistor is located at the top sidewall of the active layer 304, and the other of the source or drain of the transistor is located at the bottom surface of the active layer 304.

[0097] In some embodiments,

[0098] The size of the columnar gate 306 along the first direction decreases as the columnar gate height increases, and the size of the columnar gate 306 along the second direction decreases as the columnar gate height increases.

[0099] Alternatively,

[0100] The size of the columnar gate 306 along the first direction increases as the columnar gate height increases, and the size of the columnar gate 306 along the second direction decreases as the columnar gate height increases.

[0101] Here, the columnar gate height can be understood as the direction of the transistor pointed by the storage structure 201 along the third direction.

[0102] In some embodiments, the storage structure 201 comprises one of a capacitor, a thin film transistor, and a magnetic storage unit.

[0103] In some specific embodiments, the storage structure 201 comprises a capacitor (not shown). One transistor (Transistor) and one capacitor (Capacitor) constitute a 1T1C DRAM structure, wherein the capacitor serves as the storage structure 201 and constitutes a 1T1C structure with the transistor. The capacitor comprises a columnar second electrode, a dielectric layer covering the sidewall and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode can be connected to the source or drain of a transistor in the transistor array, and the first electrode can be grounded. The capacitor is used to store written data.

[0104] In some specific embodiments, the storage structure 201 comprises a thin film transistor (not shown). Two transistors (Transistor) and zero capacitors (Capacitor) constitute a 2T0C embedded DRAM structure, wherein the thin film transistor serves as the storage structure 201 and constitutes a 2T0C structure with the transistor. Here, the thin film transistor can also accommodate a small amount of charge without any capacitor under certain size and appropriate dopant, because the gate of the thin film transistor is a natural capacitor that can store a small amount of charge.

[0105] In some embodiments, the storage structure 201 comprises a magnetic storage unit (not shown). A magnetic random access memory (MRAM) specifically uses a magnetic tunnel junction (MTJ) as the magnetic storage unit, which reads and writes and stores information ("0" or "1") through the MTJ, and each MTJ can be driven through the transistor.

[0106] In some embodiments, the semiconductor structure further comprises a bit line isolation structure and a word line isolation structure; wherein,

[0107] The bit line isolation structure is located between the active layers 304 of two adjacent columns arranged along the first direction;

[0108] The word line isolation structure is located between two adjacent word lines 310 arranged along the second direction.

[0109] Figure 4 A flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided.

[0110] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, which comprises the following steps:

[0111] S401, providing a substrate; forming a plurality of storage structures in the substrate;

[0112] S402, forming a plurality of transistors on the storage structures, each of the storage structures corresponding to one transistor, and the plurality of transistors forming an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction; wherein the transistor comprises a columnar gate, a dielectric layer, and an active layer, the dielectric layer covering at least part of the sidewall and bottom surface of the columnar gate, and the active layer covering the sidewall of the dielectric layer, and the bottom surface of the active layer being electrically connected to the storage structure;

[0113] S403, forming a bit line, which extends along the second direction and is electrically connected to the sidewall of the active layer in the same column;

[0114] S404, forming a word line, which extends along the first direction and is electrically connected to the top surface of the columnar gate in the same row; the first direction and the second direction intersect and are both perpendicular to the direction in which the columnar gate extends; the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or, the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction.

[0115] It should be understood that,Figure 4 The steps shown in the flowchart are not exclusive and other steps can be performed before, after, or in between steps shown in the flowchart; Figure 4 The steps shown in the flowchart can be adjusted in sequence according to actual needs.

[0116] Figures 5a to 13d A cross-sectional view of a semiconductor structure manufacturing process is provided for the embodiments of the present disclosure. The following will be described in detail with reference to the embodiments of the present disclosure. Figure 4 、 Figures 5a to 13d The semiconductor structure manufacturing method provided by the embodiments of the present disclosure will be described in detail.

[0117] It should be noted that, Figures 5a to 13d Each figure with the same number in the flowchart represents a schematic diagram of multiple view planes under at least one process step; for example, Figures 13a to 13d For example, Figures 13a to 13d are cross-sectional schematic diagrams along the A-A, B-B, C-C, and D-D cross-sectional directions, respectively. The A-A cross-section can be understood as a Y-Z plane that does not pass through the active layer, the B-B cross-section can be understood as a Y-Z plane that passes through the active layer, the C-C cross-section can be understood as an X-Z plane that passes through the active layer, and the D-D cross-section can be understood as an X-Z plane that does not pass through the active layer. Figures 14a to 19d The cross-sectional direction of each figure with the same number in the flowchart can correspond to the cross-sectional direction described with reference to Figures 13a to 13d The cross-sectional direction described above and hereinafter will not be repeated.

[0118] Step S401 is performed to form a storage structure.

[0119] Referring to Figures 5a to 5d , a substrate 101 is provided, which can include elemental semiconductor materials such as silicon (Si), germanium (Ge), etc., or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc. The substrate 101 can include doped or include doped regions and undoped regions in the substrate. The substrate 101 can also include silicon-on-insulator (SOI), germanium-on-insulator (GOI), silicon-germanium-on-insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0120] A plurality of memory structures 201 are formed in the substrate 101, which constitute an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction. In practical applications, fourth insulating material 202 is also included between the memory structures 201. The fourth insulating material 202 can include, but is not limited to, silicon oxide.

[0121] In some embodiments, the memory structure 201 includes one of a capacitor, a thin film transistor, a magnetic memory cell. The memory structure 201 is used to store written data.

[0122] Reference Figures 5a to 9d In some embodiments, before forming the transistor, the method further includes:

[0123] a. forming a sacrificial layer on the memory structure;

[0124] b. forming a plurality of first trenches spaced apart along the first direction and filling the first trenches with a first insulating material; the first trenches penetrate the sacrificial layer;

[0125] c. forming a plurality of second trenches alternately spaced apart along the second direction and filling the second trenches with a second insulating material; the second trenches penetrate the sacrificial layer;

[0126] d. removing the remaining sacrificial layer to obtain an array of recesses having a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction, the bottom of each recess exposing the top surface of each memory structure; the size of the bottom of each recess along the first direction is greater than the size of the top of each recess along the first direction, and the size of the bottom of each recess along the second direction is greater than the size of the top of each recess along the second direction.

[0127] Continuing to refer to Figures 5a to 5d Step a is performed to form a sacrificial layer 301.

[0128] The sacrificial layer 301 can be deposited by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc.

[0129] Here, the material of the sacrificial layer 301 can include, but is not limited to, silicon nitride.

[0130] Reference Figures 6a to 6d Step b is performed to form a first trench T1.

[0131] The top surface of the sacrificial layer 301 can be first etched by a photolithography-etching process (LE) to form a plurality of first trenches T1 spaced apart along a first direction in the sacrificial layer 301; here, each of the first trenches T1 extends along a second direction and penetrates the sacrificial layer 301 along a third direction, dividing the sacrificial layer 301 into a plurality of strip structures.

[0132] It should be noted that the top dimension of each of the first trenches formed by the first etching along the first direction is greater than the bottom dimension of each of the first trenches along the first direction (the dimension of the first trench along the first direction is "wider at the top and narrower at the bottom"). Correspondingly, the top dimension of each of the strip structures along the first direction is smaller than the bottom dimension of each of the strip structures along the first direction (the dimension of the strip structure along the first direction is "narrower at the top and wider at the bottom").

[0133] Here, the first etching includes, but is not limited to, dry plasma etching processes.

[0134] Continue to refer to Figures 6a to 6d After the first trench T1 is formed, the first insulating material 302 is filled into the first trench T1 through processes such as PVD, CVD, and ALD.

[0135] Here, the first insulating material 302 may include, but is not limited to, silicon oxide.

[0136] In some embodiments, the first trench T1 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0137] refer to Figures 7a to 8d Execute step c to form the second trench T2.

[0138] refer to Figures 7a to 7d The top surface of the multiple strip-shaped sacrificial layers 301 and the first insulating material 302 can be etched a second time using the LE process to form multiple second trenches T2 arranged at intervals along the second direction; here, each second trench T2 extends along the first direction and penetrates the sacrificial layer 301 along the third direction, dividing the multiple strip-shaped sacrificial layers 301 into multiple columnar structures.

[0139] It is to be noted that the size of the top of each of the second trenches along the second direction is greater than the size of the bottom of each of the second trenches along the second direction (the size of the second trench along the second direction is "wide at the top and narrow at the bottom"), and correspondingly, the size of the top of each of the columnar structures along the second direction is less than the size of the bottom of each of the columnar structures along the second direction, and the size of the top of each of the columnar structures along the first direction is less than the size of the bottom of each of the columnar structures along the first direction (the size of the columnar structure along the second direction is "narrow at the top and wide at the bottom", and the size of the columnar structure along the first direction is "narrow at the top and wide at the bottom").

[0140] Here, the second etching includes but is not limited to a dry plasma etching process.

[0141] Referring to Figures 8a to 8d After the second trenches T2 are formed, a second insulating material 303 is filled in the second trenches T2 by a PVD, CVD, ALD or other process.

[0142] Here, the second insulating material 303 can include but is not limited to silicon oxide.

[0143] In some embodiments, the second trenches T2 include but are not limited to STI structures.

[0144] Referring to Figures 8a to 9d Step d is performed to form the recesses R.

[0145] The remaining sacrificial layers (such as the sacrificial layers 301 of the plurality of columnar structures shown in Figures 8a to 8d ) can be removed by an etching process to obtain a recess array (such as the plurality of recesses R shown in Figures 9a to 9d ) arranged in a plurality of columns along the first direction and a plurality of rows along the second direction, the top surface of each of the memory structures is exposed at the bottom of each of the recesses R (for understanding, refer to the structure in which no active layer 304 is formed in the recess R in Figures 9a to 9d ); the size W1 of the bottom of each of the recesses along the first direction is greater than the size W2 of the top of each of the recesses along the first direction, and the size W3 of the bottom of each of the recesses along the second direction is greater than the size W4 of the top of each of the recesses along the second direction.

[0146] Here, the etching process used can include a wet etching process, a dry etching process, etc.

[0147] Step S402 is performed to form a transistor.

[0148] Referring to Figures 9a to 12d In some embodiments, forming a transistor includes:

[0149] i. forming a semiconductor material covering the sidewall and the bottom wall of the recess;

[0150] ii. forming a dielectric material covering the sidewall and the bottom wall of the semiconductor material;

[0151] iii. forming the columnar gate covering the sidewall and the bottom wall of the dielectric material;

[0152] iv. etching back part of the dielectric material and part of the semiconductor material along the direction of the columnar gate extension, forming the active layer and the dielectric layer; the dielectric layer is between the columnar gate and the active layer and covers at least the surface of the active layer.

[0153] Referring to Figures 9a to 9d , step i is performed to form a semiconductor material 304'.

[0154] The semiconductor material 304' can be deposited on at least the bottom surface and the sidewall of the recess R by PVD, CVD, ALD, etc. In practical applications, the semiconductor material 304' can be conformally deposited on the bottom surface and the sidewall of the recess R, as well as the top surface of the first insulating material 302 and the second insulating material 303.

[0155] Here, the semiconductor material 304' can be a silicon-based material; further, it can be a polysilicon material, for example, including elemental polysilicon or doped polysilicon; in addition, the semiconductor material 304' can also include at least one of a polygermanium silicon, a carbon silicon, a germanium, etc.

[0156] Referring to Figures 10a to 10d , step ii is performed to form a dielectric material 305'.

[0157] The dielectric material 305' covering the sidewall and the bottom wall of the semiconductor material 304' can be formed by PVD, CVD, ALD, etc. The forming method of the dielectric material 305' includes but is not limited to in-situ oxidation. In practical applications, the semiconductor material 304' can be conformally deposited on the surface of the semiconductor material 304'.

[0158] Here, the dielectric material 305' can include but is not limited to silicon oxide.

[0159] Referring to Figures 11a to 11d , step iii is performed to form a columnar gate 306.

[0160] The recess R formed with the semiconductor material 304' and the dielectric material 305' can be filled by PVD, CVD, ALD, etc. to form the columnar gate 306.

[0161] Here, the material of the pillar gate 306 may include metal and / or polysilicon, etc.

[0162] refer to Figures 12a to 12d Step iv is executed to form the active layer 304 and the dielectric layer 305.

[0163] A portion of the dielectric material and a portion of the semiconductor material can be removed along the direction of the columnar gate by an etch-back process to obtain the active layer 304 and the dielectric layer 305 (see reference). Figures 12a to 12d (This is to understand the structure of bit line 307 that has not yet been formed).

[0164] The etching process used here can include wet etching, dry etching, etc.

[0165] In some embodiments, a source and a drain are formed at opposite ends of the active layer along the third direction. In some specific embodiments, the methods for forming the source and drain include, but are not limited to, ion implantation and diffusion processes.

[0166] In practical applications, after depositing the semiconductor material 304' on the bottom surface and sidewalls of the groove R, refer to Figures 9a to 9d The portion of the semiconductor material 304' located at the bottom of the groove R is subjected to ion implantation and diffusion processes to form a source or drain electrode; this can be done after the formation of the active layer 304 and the dielectric layer 305, referring to... Figures 12a to 12d The structure of bit line 307 is not formed in the middle. Further etching exposes the sidewalls on the top of the active layer 304. Ion implantation and diffusion processes are performed on the exposed sidewalls on the top of the active layer 304 to form the drain or source.

[0167] It should be noted that the positions of the source and drain can be interchanged; in practice, the selection and setting can be made according to actual needs.

[0168] Perform step S403 to form a bit line.

[0169] refer to Figures 12a to 12d In some embodiments, forming bit line 307 includes:

[0170] A first conductive material is formed in the gap between the tops of the active layers 306; the first conductive material surrounds and electrically connects to the sidewalls of the tops of the active layers 306.

[0171] A portion of the first conductive material is removed along the second direction to form a plurality of bit line isolation trenches spaced apart along the first direction. The bit line isolation trenches penetrate the first conductive material along the direction in which the columnar gate extends. The first conductive material that is not removed constitutes the bit line 307.

[0172] The medium material between the top of the active layer 304 can be further removed by etching back to expose the sidewall of the top of the active layer 304. A first conductive material can be deposited in the gap between the top of the active layer 306 by PVD, CVD, ALD, or the like.

[0173] A plurality of bit line isolation trenches spaced along the first direction can be formed by directly etching and removing part of the first conductive material by LE process. A plurality of bit line isolation trenches spaced along the first direction can also be formed by etching and removing part of the first conductive material using a self-aligned spacer process, taking the self-aligned spacer as a mask.

[0174] A fifth insulating material 308 can be filled in the bit line isolation trenches by PVD, CVD, ALD, or the like to form a bit line isolation structure. Here, the fifth insulating material 308 can include, but is not limited to, silicon oxide.

[0175] Here, the material of the bit line 307 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the bit line 307 includes TiN.

[0176] Here, each of the bit lines 307 contacts and is electrically connected to the drain D or the source S of a column of transistors arranged along the first direction in the transistor array through the sidewall of the top of the active layer 304, respectively. The bit line 307 is used to perform read or write operation on the storage structure 201 when the transistor is turned on.

[0177] Reference Figures 13a to 13d In some embodiments, forming the word line 310 includes:

[0178] A second conductive material is formed on the top of the columnar gate 306; the second conductive material contacts and is electrically connected to the top surface of the columnar gate 306;

[0179] Part of the second conductive material is removed along the first direction to form a plurality of word line isolation trenches spaced along the second direction, the word line isolation trenches extending through the second conductive material along the direction in which the columnar gate extends; the second conductive material that is not removed constitutes the word line 310.

[0180] A plurality of word line isolation trenches spaced along the second direction can be formed by directly etching and removing part of the second conductive material by LE process.

[0181] A seventh insulating material 311 can be filled in the word line isolation trenches by PVD, CVD, ALD, or the like to form a word line isolation structure. Here, the seventh insulating material 311 can include, but is not limited to, silicon oxide.

[0182] Here, the material of the word line 310 includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof. Exemplarily, the material of the word line 310 includes TiN.

[0183] It can be understood that the bit line 307 and the word line 310 are spaced apart by the sixth insulating material 309 along the direction in which the columnar gate extends. Here, the sixth insulating material 309 can include, but is not limited to, silicon oxide.

[0184] Here, each of the word lines 310 is in contact with and electrically connected to the columnar gates 306 of a row of transistors arranged along the second direction in the transistor array through the top surface of the columnar gate 306. The word line 310 is used to control the transistor to be turned on or turned off.

[0185] In the embodiments of the present disclosure, the size of the bottom surface of the active layer 304 along the first direction is greater than the size of the top surface of the active layer 304 along the first direction; and the size of the bottom surface of the active layer 304 along the second direction is greater than the size of the top surface of the active layer 304 along the second direction.

[0186] Reference Figures 13a to 13d In some embodiments, the outer contour shape of the first cross section and the second cross section of the active layer includes two legs and a bottom edge of a trapezoid; the first cross section includes a cross section of a plane in which the active layer is located along the first direction and a third direction, the second cross section includes a cross section of a plane in which the active layer is located along the second direction and the third direction, and the third direction is parallel to the direction in which the columnar gate extends.

[0187] In some embodiments, the size of the columnar gate along the first direction and the size of the columnar gate along the second direction both decrease as the height of the columnar gate increases.

[0188] In some embodiments, the size of the active layer along the third direction is less than the size of the columnar gate along the third direction.

[0189] Figures 14a to 19d A cross-sectional schematic view of another process of manufacturing a semiconductor structure is provided for the embodiments of the present disclosure.

[0190] Reference Figures 14a to 18d In some embodiments, before forming the transistor, the method further includes:

[0191] I. forming an insulating layer on the storage structure;

[0192] II. forming a plurality of third trenches spaced along the first direction and filling the third trenches with a sacrificial material; the third trenches extending through the insulating layer;

[0193] III. forming a plurality of fourth trenches alternately spaced along the second direction and filling the fourth trenches with a third insulating material; the fourth trenches extending through the sacrificial material;

[0194] IV. removing the remaining sacrificial material to obtain an array of recesses arranged along the first direction and along the second direction, each of the recesses exposing a top surface of each of the memory structures; a dimension of each of the recesses along the second direction is greater than a dimension of each of the top surfaces along the second direction.

[0195] Referring to Figures 14a to 14d , performing step I to form an insulating layer 321.

[0196] The insulating layer 321 can be deposited by PVD, CVD, ALD, or the like.

[0197] Here, the material of the insulating layer 321 can include, but is not limited to, silicon oxide.

[0198] Referring to Figures 15a to 15d , performing step II to form third trenches T3.

[0199] A third etching can be performed on a top surface of the insulating layer 321 by an LE process to form a plurality of third trenches T3 spaced along the first direction in the insulating layer 321; here, each of the third trenches T3 extends along the second direction and through the insulating layer 321 along the third direction.

[0200] Here, the third etching includes, but is not limited to, a dry plasma etching process.

[0201] Continuing to refer to Figures 14a to 14d , after forming the third trenches T3, a sacrificial material 322 is filled in the third trenches T3 by PVD, CVD, ALD, or the like.

[0202] Here, the sacrificial material 322 can include, but is not limited to, silicon nitride.

[0203] In some embodiments, the third trenches T3 include, but are not limited to, STI structures.

[0204] It is to be noted that each of the third trenches has a top portion with a dimension along the first direction larger than a dimension along the first direction of a bottom portion of each of the third trenches (the third trenches have a dimension along the first direction that is "wider at the top and narrower at the bottom"), and correspondingly, the sacrificial material 322 filled in each of the third trenches has a dimension along the first direction that is "wider at the top and narrower at the bottom".

[0205] Referring to Figures 16a to 17d , step III is performed to form fourth trenches T4.

[0206] Referring to Figures 16a to 16d , the fourth etching can be performed on the sacrificial material 322 having a plurality of strip structures by a LE process to form a plurality of fourth trenches T4 spaced along a second direction; here, each of the fourth trenches T4 extends along the first direction and penetrates the sacrificial material 322 along the third direction to divide the sacrificial material 322 to include a plurality of columnar structures.

[0207] It is to be noted that each of the fourth trenches has a top portion with a dimension along the second direction larger than a dimension along the second direction of a bottom portion of each of the fourth trenches (the fourth trenches have a dimension along the second direction that is "wider at the top and narrower at the bottom"), and correspondingly, each of the columnar structures has a dimension along the second direction of a top portion smaller than a dimension along the second direction of a bottom portion and a dimension along the first direction larger than a dimension along the first direction of the bottom portion (the columnar structures have a dimension along the second direction that is "narrower at the top and wider at the bottom" and a dimension along the first direction that is "wider at the top and narrower at the bottom").

[0208] Here, the fourth etching includes but is not limited to a dry plasma etching process.

[0209] Referring to Figures 17a to 17d , after the fourth trenches T4 are formed, a third insulating material 323 is filled in the fourth trenches T4 by a PVD, CVD, ALD or other process.

[0210] Here, the third insulating material 323 can include but is not limited to silicon oxide.

[0211] In some embodiments, the fourth trenches T4 include but are not limited to STI structures.

[0212] Referring to Figures 17a to 18d , step IV is performed to form recesses R.

[0213] The remaining sacrificial material (e.g., the sacrificial material 322 of the plurality of columnar structures) can be removed by an etching process to obtain a recess array (e.g., the recess array 300) having a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction. Figures 17a to 17d Figures 18a to 18d ​The plurality of recesses R shown, the bottom of each recess R exposing the top surface of each of the storage structures (see reference). Figures 18a to 18d (Understanding that the active layer 304 is not formed in the groove R); the dimension W5 of the bottom of each groove along the first direction is smaller than the dimension W6 of the top of each groove along the first direction, and the dimension W7 of the bottom of each groove along the second direction is larger than the dimension W8 of the top of each groove along the second direction.

[0214] The etching process used here may include wet etching process, dry etching process, etc.

[0215] Here, semiconductor material 304' (e.g., ...) can be conformally deposited on the bottom surface, sidewalls, top surface of insulating layer 321, and top surface of third insulating material 323 of the groove R. Figures 18a to 18d (As shown).

[0216] exist Figures 18a to 18d Based on the semiconductor structure shown, subsequent processes are performed to form transistors, bit lines, and word lines, resulting in the structure shown. Figures 19a to 19d The semiconductor structure is shown. Here, the detailed process of forming transistors, bit lines, and word lines in subsequent processes can be understood by referring to the process of forming transistors, bit lines, and word lines in the above-described execution steps S402 to S404, which will not be repeated here.

[0217] In this embodiment of the disclosure, the dimension of the bottom surface of the active layer 304 in the semiconductor structure along the second direction is greater than the dimension of the top surface of the active layer 304 along the second direction.

[0218] refer to Figures 19a to 19d In some embodiments, the outer contour shape of the second cross section of the active layer includes two waists and a base of a trapezoid; the second cross section includes a cross section of the active layer along the second direction and the third direction, the third direction being parallel to the direction in which the columnar gate extends.

[0219] In some embodiments, the dimension of the pillared gate along the first direction increases with the increase of the pillared gate height, and the dimension of the pillared gate along the second direction decreases with the increase of the pillared gate height.

[0220] In some embodiments, the dimension of the active layer along the third direction is smaller than the dimension of the pillar gate along the third direction.

[0221] In other embodiments, the above can be applied... Figures 14a to 19dThe embodiment shown in the steps of the embodiment are slightly changed, i.e., the above step II is replaced by "forming a plurality of third trenches spaced along the second direction and filling the third trenches with a sacrificial material; the third trenches penetrate the insulating layer", the above step III is replaced by "forming a plurality of fourth trenches alternately spaced along the first direction and filling the fourth trenches with a third insulating material; the fourth trenches penetrate the sacrificial material", the above step IV is replaced by "removing the remaining sacrificial material to obtain a recess array of a plurality of columns along the first direction and a plurality of rows along the second direction, each recess bottom exposes a top surface of each memory structure; the size of each recess bottom along the first direction is greater than the size of each top along the first direction"; and other subsequent processes can be understood in detail with reference to the above Figures 14a to 19d , which will not be repeated here.

[0222] Based on this, the size of the bottom surface of the active layer along the first direction in the obtained semiconductor structure is greater than the size of the top surface of the active layer along the first direction (not shown in the embodiment of the present disclosure, which can be understood with reference to Figures 13a to 13d , specifically, the "narrow top and wide bottom" active layer in Figure 13b is replaced by an "wide top and narrow bottom" active layer, Figure 13a , Figure 13c , Figure 13d may remain unchanged).

[0223] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided by the above embodiments of the present disclosure has the following characteristics: the size of the bottom surface of the active layer along the first direction is greater than the size of the top surface of the active layer along the first direction; and / or, the size of the bottom surface of the active layer along the second direction is greater than the size of the top surface of the active layer along the second direction. That is, the size of the bottom surface of the active layer is relatively large, so that the contact area between the bottom surface of the active layer and the memory structure can be larger, which is beneficial for better contact between the active layer and the memory structure to reduce the resistance; and the size of the top of the active layer is relatively small, so that the top of the active layer is more easily contacted by the bit line, and because the size of the top of the active layer is relatively small, the spacing between the tops of the active layers is relatively large, which reduces the parasitic capacitance between the subsequently formed bit lines and word lines, reduces the process difficulty of forming the bit line isolation trench and the word line isolation trench, and is more conducive to the formation of the bit line and the bit line isolation structure and the word line and the word line isolation structure, and thus the semiconductor structure can be further miniaturized.

[0224] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided by the embodiments of the present disclosure is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in the embodiments of the present disclosure, please refer to the above embodiments for understanding, which will not be repeated here.

[0225] Figure 20 This is a schematic diagram of a planar structure of a memory provided in an embodiment of this disclosure.

[0226] According to another aspect of this disclosure, a memory is provided, comprising: a substrate, and at least one semiconductor structure as described in any of the above embodiments, located above the substrate.

[0227] Figure 20 This can be understood as being in Figures 13a to 13d or Figures 19a to 19d The memory is further formed on the basis of the array cell area (CELL) and core / peripheral circuit area (CORE / PERI) in the memory.

[0228] In order to maintain consistency with the above behaviors Figure 20 The arrangement of the active column SP in the diagram can be referenced. Figures 13a to 13d or Figures 19a to 19d The arrangement of the active layer 304 described herein will be understood. Figure 20 The AA, BB, CC, and DD sections can also be referenced. Figures 13a to 13d or Figures 19a to 19d To understand the cross-sectional position in the text; among them, Figure 20 The AA section in the diagram represents a plane along the YZ plane that does not pass through a row of transistors (including active pillars SP) extending along the second direction; Figure 20 The BB section in the diagram represents a plane along the YZ plane that passes through a row of transistors (including active pillars SP) extending along the second direction; Figure 20 The CC section in the figure represents a plane along the XZ plane and passing through a row of transistors (including active pillars SP) arranged along the first direction; Figure 20 The DD section in the diagram represents a plane along the XZ plane that does not pass through a row of transistors (including active pillars SP) arranged along the first direction. It should be noted that, here and below, the active pillar SP can be understood as... Figures 13a to 13d or Figures 19a to 19d The active layer 304, dielectric layer 305, and at least a partial pillar gate 306 (at least a portion of the pillar gate 306 surrounded by dielectric layer 305) are shown.

[0229] It should be noted that, Figure 20The diagram illustrates the array cell region (CELL) and core / peripheral circuit region (CORE / PERI) of the memory. The array cell region includes active pillars SP, word lines WL, and bit lines BL, and the active pillars SP, word lines WL, and bit lines BL are projected onto the XY plane. The extension direction of the word lines WL is perpendicular to the extension direction of the bit lines BL. The word lines WL extend along a first direction and are arranged along a second direction, while the word lines BL extend along the second direction and are arranged along the first direction. The active layer (not shown) in the active pillars SP, the source and drain (not shown) formed at both ends along the extension direction of the active layer, the pillared gate (not shown) surrounded by the active layer on its sidewalls, and the dielectric layer between the active layer and the pillared gate constitute the transistors of the memory.

[0230] Understandably, the bit line BL surrounds and electrically connects the sidewalls of the active layer, electrically connecting the source / drain of each transistor in each column of transistors arranged along the second direction; the word line WL contacts and electrically connects the top surface of the pillar gate, electrically connecting the pillar gate of each transistor in each row of transistors arranged along the first direction.

[0231] In some embodiments, the memory includes a plurality of said semiconductor structures stacked in a direction perpendicular to the substrate.

[0232] It should be noted that the memory described in the embodiments of this disclosure is not limited to fabricating a specific number of three-dimensional stacks, but can also be formed from two or more such... Figures 13a to 13d or Figures 19a to 19d The semiconductor structure shown is a three-dimensional stacked memory along the third direction, which can increase the density of the memory.

[0233] like Figures 13a to 13d or Figures 19a to 19d As shown, in some embodiments, the substrate 101 includes peripheral circuitry, and the memory cells (including transistors and memory structures) in the semiconductor structure are electrically connected to the peripheral circuitry.

[0234] With the peripheral circuitry located at the bottom, the area available for the 201 memory array and transistor array can be greatly increased, which is beneficial for increasing memory density.

[0235] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0236] The specific embodiments of the present disclosure are disclosed herein, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art, within the technical scope disclosed by the present disclosure, can easily think of changes or replacements, which should be covered by the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be subject to the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a plurality of memory cells, a plurality of word lines, a plurality of bit lines; wherein, the plurality of memory cells form an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction, each of the memory cells comprises a storage structure and a transistor located above the storage structure; the transistor comprises a columnar gate, a dielectric layer and an active layer, the dielectric layer covers at least part of sidewalls and a bottom surface of the columnar gate, the active layer covers sidewalls of the dielectric layer, a bottom surface of the active layer is electrically connected to the storage structure; each of the bit lines extends along the second direction and is electrically connected to sidewalls of the active layer of the same column; each of the word lines extends along the first direction and is electrically connected to top surfaces of the columnar gates of the same row; the first direction and the second direction intersect and are both perpendicular to a direction in which the columnar gate extends; a dimension of the bottom surface of the active layer along the first direction is greater than a dimension of a top surface of the active layer along the first direction; and / or, a dimension of the bottom surface of the active layer along the second direction is greater than a dimension of the top surface of the active layer along the second direction.

2. The semiconductor structure of claim 1, wherein, an outer contour shape of a first cross section and / or a second cross section of the active layer comprises two legs and a bottom edge of a trapezoid; the first cross section comprises a cross section of a plane in which the active layer lies along the first direction and a third direction, the second cross section comprises a cross section of a plane in which the active layer lies along the second direction and the third direction, the third direction is parallel to a direction in which the columnar gate extends.

3. The semiconductor structure of claim 2, wherein, a dimension of the active layer along the third direction is less than a dimension of the columnar gate along the third direction.

4. The semiconductor structure of claim 3, wherein, one of a source or a drain of the transistor is located at a top sidewall of the active layer, the other of the source or the drain of the transistor is located at a bottom surface of the active layer.

5. The semiconductor structure of claim 1, wherein, a dimension of the columnar gate along the first direction and a dimension of the columnar gate along the second direction both decrease as a height of the columnar gate increases; or, the dimension of the columnar gate along the first direction increases as the height of the columnar gate increases, and the dimension of the columnar gate along the second direction decreases as the height of the columnar gate increases.

6. The semiconductor structure of claim 1, wherein, the storage structure comprises one of a capacitor, a thin film transistor, a magnetic memory cell.

7. The semiconductor structure of claim 1, wherein, the semiconductor structure further comprises a bit line isolation structure and a word line isolation structure; wherein, the bit line isolation structure is located between the active layers of two adjacent columns arranged along the first direction; the word line isolation structure is located between two adjacent word lines arranged along the second direction.

8. A memory, comprising: Comprising: a substrate, and at least one semiconductor structure as claimed in any one of claims 1 to 7 located above the substrate.

9. The memory of claim 8, wherein, the memory comprises a plurality of the semiconductor structures, the plurality of the semiconductor structures are stacked in a direction perpendicular to the substrate.

10. The memory of claim 8 or 9, wherein, the substrate comprises a peripheral circuit, and the semiconductor structure is electrically connected to the peripheral circuit.

11. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a substrate; forming a plurality of storage structures in the substrate; Forming a plurality of transistors on the memory structure, each of the memory structure corresponding to a transistor, the plurality of transistors forming an array having a plurality of columns arranged along a first direction and a plurality of rows arranged along a second direction; wherein the transistor comprises a columnar gate, a dielectric layer and an active layer, the dielectric layer covering at least part of sidewalls and a bottom surface of the columnar gate, the active layer covering sidewalls of the dielectric layer, a bottom surface of the active layer electrically connecting the memory structure; Forming a bit line, the bit line extending along the second direction and electrically connecting sidewalls of the active layer of the same column; Forming a word line, the word line extending along the first direction and electrically connecting top surfaces of the columnar gate of the same row; the first direction and the second direction intersect and are both perpendicular to a direction in which the columnar gate extends; a dimension of the bottom surface of the active layer along the first direction is greater than a dimension of a top surface of the active layer along the first direction; and / or, a dimension of the bottom surface of the active layer along the second direction is greater than a dimension of the top surface of the active layer along the second direction.

12. The method of fabricating a semiconductor structure of claim 11, wherein, Before forming the transistor, the method further comprises: forming a sacrificial layer on the memory structure; forming a plurality of first trenches spaced along the first direction and filling the first trenches with a first insulating material; the first trenches penetrating the sacrificial layer; forming a plurality of second trenches alternately spaced along the second direction and filling the second trenches with a second insulating material; the second trenches penetrating the sacrificial layer; removing the remaining sacrificial layer to obtain an array of recesses having a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction, a bottom of each of the recesses exposing a top surface of each of the memory structures; a dimension of the bottom of each of the recesses along the first direction is greater than a dimension of a top of each of the recesses along the first direction, and a dimension of the bottom of each of the recesses along the second direction is greater than a dimension of the top of each of the recesses along the second direction.

13. The method of fabricating a semiconductor structure of claim 11, wherein, Before forming the transistor, the method further comprises: forming an insulating layer on the memory structure; forming a plurality of third trenches spaced along the first direction and filling the third trenches with a sacrificial material; the third trenches penetrating the insulating layer; forming a plurality of fourth trenches alternately spaced along the second direction and filling the fourth trenches with a third insulating material; the fourth trenches penetrating the sacrificial material; removing the remaining sacrificial material to obtain an array of recesses having a plurality of columns arranged along the first direction and a plurality of rows arranged along the second direction, a bottom of each of the recesses exposing a top surface of each of the memory structures; a dimension of the bottom of each of the recesses along the second direction is greater than a dimension of the top of each of the bottom along the second direction.

14. The method of fabricating a semiconductor structure according to claim 12 or 13, wherein, Forming the transistor comprises: in the recess, forming a semiconductor material covering sidewalls and a bottom wall of the recess; forming a dielectric material covering sidewalls and a bottom wall of the semiconductor material; forming the columnar gate covering sidewalls and a bottom wall of the dielectric material; Etching back part of the dielectric material and part of the semiconductor material along the direction in which the columnar gate extends, forming the active layer and the dielectric layer; the dielectric layer is between the columnar gate and the active layer and covers at least the surface of the active layer.

15. The method of fabricating a semiconductor structure of claim 11, wherein, Forming the bit line includes: forming a first conductive material in the gap between the top of the active layer; the first conductive material surrounds the sidewall of the top of the active layer and electrically connects the top of the active layer; removing part of the first conductive material along the second direction to form a plurality of bit line isolation trenches spaced along the first direction; the bit line isolation trenches penetrate the first conductive material along the direction in which the columnar gate extends; the first conductive material that is not removed constitutes the bit line.

16. The method of fabricating a semiconductor structure of claim 11, wherein, Forming the word line includes: forming a second conductive material on the top of the columnar gate; the second conductive material contacts and electrically connects the top surface of the columnar gate; removing part of the second conductive material along the first direction to form a plurality of word line isolation trenches spaced along the second direction; the word line isolation trenches penetrate the second conductive material along the direction in which the columnar gate extends; the second conductive material that is not removed constitutes the word line.

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