2D1R process method based on driving current and window improvement

Abstract

The present invention provides a 2D1R process method and array based on drive current and window improvements. The method connects a second diode in a p+ active region to a reset line via a CT. The p-type end of the first diode and the n-type end of the second diode are connected to a metal layer via the CT, and the metal layer is connected to an RRAM device to form an RRAM array. The two diodes and an RRAM device are connected to form a storage cell in the RRAM array. The RRAM array is then subjected to read, write, and erase operations according to a preset operation table. In this way, due to the reverse bias effect between the n-well and the p-well, the reverse bias breakdown voltage of the two is generally above 10V, far exceeding the application scenario of RRAM < 5V. At the same time, the well end of each diode is led out, reducing the resistance of the well as a word line and a RESET line, thereby reducing IR drop and increasing the drive current. In addition, a 2D1R operation method different from the prior art is adopted to actively set the voltages of unselected bit lines, word lines, and RESET lines, thereby improving the suppression performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and more particularly to a 2D1R process method based on drive current and window improvement. Background Art

[0002] RRAM (resistance random access memory) generally requires a selection device to suppress the sneak path and change the state of the selected memory cell. The common practice is to use a single MOSFET or a single diode to achieve this. When using a MOSFET as a selection device, it is necessary to provide relatively high set and reset voltages, such voltages are generally around 3V. For logic processes of 28nm and below, the MOSFET device size that provides such voltages is relatively large, generally over 100F^2, where F is the process node size. At the same time, the leakage current is also relatively high. The device reliability decreases as the voltage increases. When using a single diode as a selection device, it can only conduct in one direction and cannot meet the requirements of bipolar RRAM.

[0003] Therefore, a new array structure is needed. The 2D1R array structure can meet such requirements. There are currently some implementation methods for the 2D1R structure in the prior art, such as the prior art with patent publication number CN110047867. In this patent document, since the driving current needs to flow through a well resistor with a relatively high resistance, an IR drop is generated, resulting in a large voltage drop when reaching the selected resistor far away from the well lead end, which is not conducive to SET or RESET operations. For example, the patent document with patent publication number CN109427839 uses the same type of well (both n-type wells or p-type wells) for all diodes. However, in this patent, the isolation performance between wells is difficult to achieve complete isolation through deep isolation trenches.

[0004] Therefore, there is an urgent need for a 2D1R process method based on drive current and window improvement that isolates the n-type well and p-type well from each other, while leading out the well end of each diode in parallel to balance the device size and IR drop of the well resistance, improve the process window, and realize the 2D1R array structure. Summary of the Invention

[0005] In view of the above problems, the purpose of the present invention is to provide a 2D1R process method based on drive current and window improvements to solve the problems of relatively high leakage in existing arrays, reduced device reliability due to higher voltage, and the inability to meet the requirements of bipolar RRAM due to the use of a single diode as a selection device, which can only conduct in one direction.

[0006] The present invention provides a 2D1R process method based on drive current and window improvement, which includes:

[0007] forming an n-well and a p-well by ion implantation, forming a deep trench region and a shallow trench region based on the n-well and the p-well by etching, and grinding and filling the shallow trench region to isolate the n-well from the p-well to form an n-well region and a p-well region;

[0008] Performing ion implantation in the n-well region and the p-well region to form an n+ active region and a p+ active region respectively;

[0009] Connecting the first diode where the n+ active region is located to the word line through a CT; connecting the second diode where the p+ active region is located to the reset line through a CT; connecting the p-type end of the first diode and the n-type end of the second diode to a metal layer through a CT, and connecting the metal layer to the RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a memory cell in the RRAM array;

[0010] The RRAM array is made to perform read, write and erase operations according to a preset operation table.

[0011] Preferably, the process of forming the n-well and the p-well by ion implantation includes:

[0012] The n-well is formed by implanting n-type element ions, and the p-well is formed by implanting p-type element ions.

[0013] Preferably, during the process of implanting elemental ions,

[0014] The implantation depth of the n-well or the p-well is adjusted by adjusting the implantation energy, and the concentration of the n-well or the p-well is adjusted by adjusting the implantation dose; wherein,

[0015] The difference in depth and concentration between the n-well and the p-well causes reverse bias leakage between the n-well and the p-well, and also generates forward bias current.

[0016] Preferably, after forming the n-well and the p-well,

[0017] An np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well.

[0018] Preferably, during the read operation of the RRAM array,

[0019] For a selected memory cell in the RRAM array, the bit line voltage is set to Vrd voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

[0020] Preferably, during the writing process of the RRAM array,

[0021] For a selected memory cell in the RRAM array, the bit line voltage is set to Vset voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

[0022] Preferably, during the erasing operation of the RRAM array,

[0023] A RESET voltage is applied to the reset line of the selected memory cell in the RRAM array, and 0V is applied to the bit line. A RESET voltage is applied to the unselected bit line in the RRAM array to suppress leakage.

[0024] The present invention further provides an array based on drive current and window improvement, which is produced based on the aforementioned 2D1R process method based on drive current and window improvement, comprising:

[0025] An n-well and a p-well, wherein the n-well and the p-well are formed by ion implantation;

[0026] A deep trench region and a shallow trench region are formed on the n-well and the p-well by an etching process; the shallow trench region isolates the n-well and the p-well and divides them into an n-well region and a p-well region;

[0027] Ions are implanted into the n-well region and the p-well region to form an n+ active region and a p+ active region respectively;

[0028] The first diode where the n+ active region is located is connected to the word line via a CT; the second diode where the p+ active region is located is connected to the reset line via a CT; the p-type end of the first diode and the n-type end of the second diode are connected via the CT via a metal layer, and the metal layer is connected to the RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a storage cell in the RRAM array; the RRAM array is used to perform read, write, and erase operations according to a preset operation table.

[0029] Preferably, the n-well contains n-type element ions, and the p-well contains p-type element ions.

[0030] Preferably, an np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well.

[0031] As can be seen from the above technical solutions, the 2D1R process method based on the drive current and window improvement provided by the present invention first forms an n-well and a p-well by ion implantation, and forms a deep trench region and a shallow trench region based on the n-well and the p-well by etching process, and the shallow trench region is ground and filled to isolate the n-well from the p-well to form an n-well region and a p-well region; ion implantation is performed in the n-well region and the p-well region respectively to form an n+ active region and a p+ active region; the first diode where the n+ active region is located is connected to the word line through CT; the second diode where the p+ active region is located is connected to the reset line through CT; and the p-type end of the first diode and the n-type end of the second diode are connected to the m-type region through CT. etal layer, connecting the metal layer to the RRAM device to form an RRAM array; wherein, two diodes and an RRAM device are connected to form a storage cell in the RRAM array; then the RRAM array is made to perform read, write, and erase operations according to a preset operation table. In this way, the same word line is implemented through a connected n-well, and the same RESET line is implemented through a p-well of the opposite type to the word line. Due to the reverse bias effect between the n-well and the p-well, the reverse bias breakdown voltage of the two is generally above 10V, which far exceeds the application scenario of RRAM<5V. At the same time, the well end of each diode is brought out to reduce the resistance of the well as the word line and RESET line, thereby reducing IR DROP and increasing the drive current. In addition, a 2D1R operation method different from the existing technology is adopted to actively set the voltage of the unselected bit line, word line and RESET line, thereby improving the suppression performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the accompanying drawings:

[0033] Figure 1-Figure 3 It is a schematic diagram of the prior art;

[0034] Figure 4 Flowchart of a 2D1R process method based on driving current and window improvement according to an embodiment of the present invention;

[0035] Figure 5 Schematic diagram of an array structure involved in a 2D1R process method based on drive current and window improvement according to an embodiment of the present invention;

[0036] Figure 6 Schematic diagram of n-well and p-well in a 2D1R process method based on drive current and window improvement according to an embodiment of the present invention;

[0037] Figure 7 A top view of an array based on driving current and window improvement involved in a 2D1R process method based on driving current and window improvement according to an embodiment of the present invention;

[0038] Figure 8 A cross-sectional view of an array based on driving current and window improvement involved in a 2D1R process method based on driving current and window improvement according to an embodiment of the present invention;

[0039] Figure 9 A cross-sectional view of an array along WL, which is involved in a 2D1R process method based on driving current and window improvement according to an embodiment of the present invention;

[0040] Figure 10 4 is a cross-sectional view of an array based on driving current and window improvement involved in a 2D1R process method based on driving current and window improvement according to an embodiment of the present invention, taken along the RESET line. DETAILED DESCRIPTION

[0041] Figure 1-Figure 3 The structure in the prior art is shown. For an RRAM array (such as Figure 1 ), due to the leakage path formed by the surrounding low-resistance resistors, a misreading will occur when reading a selected high-resistance resistor, and it will be misread as a low-resistance resistor; in order to solve this problem, the industry generally adopts a 1T1R structure (such as Figure 2 ) or a 1D1R structure (such as Figure 3 ), for the 1T1R structure, the need for RRAM SET and RESET voltages and the need for drive current result in a relatively large device size, generally greater than 100F^2, and also brings high leakage and reliability issues; for the 1D1R structure, it can realize the reading and SET of the RRAM array, and can also realize the RESET of the unipolar RRAM, but it cannot realize the RESET of the bipolar RRAM.

[0042] In view of the above problems existing in the prior art, the present invention provides a 2D1R process method based on driving current and window improvement. The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] In order to illustrate the 2D1R process method based on driving current and window improvement provided by the present invention, Figure 4-10 The 2D1R process method based on driving current and window improvement according to an embodiment of the present invention is exemplarily illustrated; Figure 4 A flow chart of a 2D1R process method based on drive current and window improvement according to an embodiment of the present invention is shown; Figure 5-10 The array involved in the 2D1R process method based on driving current and window improvement according to the embodiment of the present invention is exemplarily marked.

[0044] The following description of exemplary embodiments is merely illustrative in nature and is in no way intended to limit the present invention, its application, or uses. Techniques and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques and devices should be considered part of the specification.

[0045] like Figure 4 As shown, the 2D1R process method based on driving current and window improvement according to an embodiment of the present invention includes:

[0046] S1: forming an n-well and a p-well by ion implantation, and forming a deep trench region and a shallow trench region based on the n-well and the p-well by an etching process, and grinding and filling the shallow trench region to isolate the n-well and the p-well to form an n-well region and a p-well region;

[0047] S2: performing ion implantation in the n-well region and the p-well region to form an n+ active region and a p+ active region respectively;

[0048] S3: Connecting the first diode where the n+ active region is located to the word line through CT; connecting the second diode where the p+ active region is located to the reset line through CT; and connecting the p-type end of the first diode and the n-type end of the second diode to the metal layer through CT, and connecting the metal layer to the RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a memory cell in the RRAM array;

[0049] S4: performing read, write, and erase operations on the RRAM array according to a preset operation table.

[0050] like Figure 4 、 Figure 5 、 Figure 6 As shown together, step S1 is a process of forming an n-well and a p-well by ion implantation, and forming a deep trench region and a shallow trench region based on the n-well and the p-well by an etching process, and grinding and filling the shallow trench region to isolate the n-well and the p-well to form an n-well region and a p-well region; in step S1, the process of forming the n-well and the p-well by ion implantation includes:

[0051] The n-well is formed by implanting n-type element ions, and the p-well is formed by implanting p-type element ions; the implantation depth of the n-well or p-well is adjusted by adjusting the implantation energy, and the concentration of the n-well or p-well is adjusted by adjusting the implantation dose; wherein,

[0052] The difference in depth and concentration between the n-well and p-well causes reverse leakage between the n-well and p-well, and also generates forward current. For the n-well, n-type element ions are used, and the depth of the junction injection is adjusted by adjusting the injection energy, and the concentration of the well is adjusted by adjusting the injection dose. For the p-well, p-type element ions are used, and the depth of the junction injection is adjusted by adjusting the injection energy, and the concentration of the well is adjusted by adjusting the injection dose. In principle, the depth and concentration of the n-well and p-well should form good isolation and a large forward current.

[0053] In addition, an np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well. That is, after the n-well and the p-well are formed, an np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-type region relative to the p-type region.

[0054] exist Figure 4 、 Figure 5 、 Figure 6 In the embodiment shown in the figure, a deep trench isolation (DTI) is formed by exposure and etching. The top view of the process at this time is as shown in FIG. Figure 6 , where n-well (NW) and p-well (PW) are semi-transparent to represent the corresponding relationship with DTI. Figure 6 It can be seen that the opening size of the n-well and p-well is 4F, the spacing size is 8F, and the pattern shape is a regular strip size, which provides a large process window for process manufacturing; then a shallow trench area (STI) is formed through an etching process, and separated n-well and p-well areas are formed through subsequent filling and grinding processes. Among them, DTI is used to better isolate the NW and PW, and STI is used to isolate the PN junction inside the diode. The grinding process refers to filling the DTI and STI areas that have been etched away with oxide, and then grinding the filled oxide flat.

[0055] exist Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 In the embodiment shown in the figure, step S2 is a process of performing ion implantation in the n-well region and the p-well region to form an n+ active region and a p+ active region, that is, forming an N+ and a P+ region (N+ and P+ active regions) by ion implantation, respectively. The top view of the formed region is shown in FIG. Figure 7 , in this embodiment, Figure 7 The area marked by the dotted line is the size of a single 2D1R unit of 16F2.

[0056] exist Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 In the embodiment shown together, step S3 is a process of connecting the first diode where the n+ active area is located to the word line through CT; connecting the second diode where the p+ active area is located to the reset line through CT; and connecting the p-type end of the first diode and the n-type end of the second diode to the metal layer through CT, and connecting the metal layer to the RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a memory cell in the RRAM array.

[0057] More specifically, the RRAM array is formed by connecting the CT and Metal lines with the RRAM resistor array. Figure 8 ,in Figure 8 It is along Figure 7 The X-ray cut has a cross-sectional view, along Figure 7 The cross-section taken along the Y1 line is shown in the figure below: Figure 9 ,along Figure 7 The cross-section taken along the Y2 line is shown in the figure below: Figure 10 .from Figure 9 and Figure 10 It can be seen that all n-well diodes on the same WL have a CT lead to reduce the lead resistance, and all p-well diodes on the same RESET line have a CT lead to reduce the lead resistance, thereby reducing IR drop and providing sufficient drive current.

[0058] Each memory cell in the array consists of two diodes and an RRAM link. The p-type terminal of the first diode and the n-type terminal of the second diode are connected to a metal layer via a CT. This metal layer is then connected to the RRAM device. The WL is connected to the n-type active region of the first diode via a CT, and the RL (reset line) is connected to the p-type active region of the second diode via a CT.

[0059] The n-well resistance of each first diode in the array is reduced by directly connecting the n-well of each first diode in the array to the metal layer through the CT on the n-type active region, and the p-well resistance of each second diode in the array is reduced by directly connecting the p-well of each second diode in the array to the metal layer through the CT on the p-type active region.

[0060] Step S4 is a process of making the RRAM array perform read, write, and erase operations according to a preset operation table. The operation table is a preset table for 2D1R, as shown in the following table:

[0061] In step S4, during the RRAM array read operation,

[0062] For a selected memory cell in the RRAM array, the bit line voltage is set to Vrd voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

[0063] During the writing process of the RRAM array,

[0064] For a selected memory cell in the RRAM array, the bit line voltage is set to Vset voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

[0065] During the erase operation of the RRAM array,

[0066] A RESET voltage is applied to the reset line of the selected memory cell in the RRAM array, and 0V is applied to the bit line. A RESET voltage is applied to the unselected bit line in the RRAM array to suppress leakage.

[0067] That is, using Figure 5The 2D1R structure of the RRAM memory array implements the read, write (SET), and erase (RESET) operations of the RRAM array. In the figure, BL is the bit line, WL is the word line, and R / L is the RESET line (reset line). The read, write, and erase operations of the RRAM array are shown in the table above. During the read process, for the selected RRAM memory cell, BL is at the Vrd voltage, WL is 0V, and R / L is set to 0V regardless of whether it is selected or not. This can suppress leakage through R / L. For the unselected BL, 0V is added, and the unselected WL is added to the Vrd voltage to suppress leakage from the selected BL to the unselected WL. During the write process, for the selected RRAM memory cell, BL is at the Vset voltage, WL is 0V, and R / L is set to 0V regardless of whether it is selected or not. This can suppress leakage through R / L. For the unselected BL, 0V is added, and the unselected WL is added to the Vset voltage to suppress leakage from the selected BL to the unselected WL. In the above read and write processes, the RESET line is relatively redundant, but leakage needs to be suppressed, so the RESET lines are all set to 0V. During the RESET process, the RESET voltage is applied to the RESET line of the selected RRAM cell, and the BL is applied to 0V. The RESET voltage is applied to the unselected BL to suppress leakage, thereby preventing the RRAM cell with the selected RESET line but unselected BL from being RESET. At this time, the RESET voltage is applied to all WLs to suppress the leakage path. The Vrd voltage is generally 0.3V to 1V, the Vset voltage is generally 2.0V to 3.5V, and the Vreset voltage is generally 1.5V to 3.5V. During the read operation, the current flows from BL to WL. Since the diode on the RESET line is reverse biased, and the diode can achieve a leakage current of <1e-12A, it can be seen from the table that the Vwl voltage is greater than or equal to Vrl in any case. The reverse bias effect of the n-well and p-well can be used to maintain a good process window while achieving isolation.

[0068] As described above, the 2D1R process method based on drive current and window improvement provided by the present invention first forms an n-well and a p-well by ion implantation, and forms a deep trench region and a shallow trench region based on the n-well and the p-well by etching process, and grinds and fills the shallow trench region to isolate the n-well from the p-well to form an n-well region and a p-well region; ion implantation is performed in the n-well region and the p-well region respectively to form an n+ active region and a p+ active region; the first diode where the n+ active region is located is connected to the word line through CT; the second diode where the p+ active region is located is connected to the reset line through CT; and the p-type end of the first diode and the n-type end of the second diode are connected to the meta through CT. The first layer connects the metal layer to the RRAM device to form an RRAM array. Two diodes and an RRAM device are connected to form a memory cell in the RRAM array. The RRAM array is then operated to perform read, write, and erase operations according to a preset operation table. In this way, the same word line is implemented through a connected n-well, and the same RESET line is implemented through a p-well of the opposite type to the word line. Due to the reverse bias effect between the n-well and p-well, the reverse bias breakdown voltage of both is generally above 10V, which far exceeds the application scenario of RRAM <5V. At the same time, the well end of each diode is brought out to reduce the resistance of the well as the word line and RESET line, thereby reducing IR drop and increasing the drive current. In addition, a 2D1R operation method is used, which is different from the existing technology, to actively set the voltage of the unselected bit line, word line, and RESET line, improving the device's suppression performance.

[0069] The present invention also provides an array based on driving current and window improvement, which is generated based on the 2D1R process method based on driving current and window improvement as described above. The array based on driving current and window improvement is the array based on driving current and window improvement involved in the 2D1R process method based on driving current and window improvement, such as Figure 7-10 Shown, including:

[0070] An n-well and a p-well, wherein the n-well and the p-well are formed by ion implantation;

[0071] A deep trench region and a shallow trench region are formed on the n-well and the p-well by an etching process; the shallow trench region isolates the n-well and the p-well and divides them into an n-well region and a p-well region;

[0072] Ions are implanted into the n-well region and the p-well region to form an n+ active region and a p+ active region respectively;

[0073] The first diode, where the n+ active region is located, is connected to the word line via a CT; the second diode, where the p+ active region is located, is connected to the reset line via a CT; the p-type end of the first diode and the n-type end of the second diode are connected via a CT via a metal layer, which is connected to an RRAM device to form an RRAM array; wherein, two diodes and an RRAM device are connected to form a storage cell in the RRAM array; the RRAM array is used to perform read, write, and erase operations according to a preset operation table.

[0074] The n-well contains n-type element ions, and the p-well contains p-type element ions.

[0075] An np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well.

[0076] It can be seen from the above embodiments that the array based on the drive current and window improvement provided by the present invention first forms an n-well and a p-well by ion implantation, and forms a deep trench region and a shallow trench region based on the n-well and the p-well by etching process, and grinds and fills the shallow trench region to isolate the n-well from the p-well to form an n-well region and a p-well region; ion implantation is performed in the n-well region and the p-well region respectively to form an n+ active region and a p+ active region; the first diode where the n+ active region is located is connected to the word line through CT; the second diode where the p+ active region is located is connected to the reset line through CT; and the p-type end of the first diode and the n-type end of the second diode are connected to the met The al layer connects the metal layer to the RRAM device to form an RRAM array; wherein, two diodes and an RRAM device are connected to form a storage cell in the RRAM array; then, according to a preset operation table, the RRAM array is subjected to read, write, and erase operations. In this way, the same word line is implemented through a connected n-well, and the same RESET line is implemented through a p-well of the opposite type to the word line. Due to the reverse bias effect between the n-well and the p-well, the reverse bias breakdown voltage of both is generally above 10V, which far exceeds the application scenario of RRAM <5V. At the same time, the well end of each diode is brought out to reduce the resistance of the well as the word line and RESET line, thereby reducing IR drop and increasing the drive current. In addition, a 2D1R operation method different from the existing technology is adopted to actively set the voltage of the unselected bit line, word line and RESET line, thereby improving the suppression performance of the device.

[0077] The 2D1R process method and array based on drive current and window improvements proposed in accordance with the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the 2D1R process method and array based on drive current and window improvements proposed in accordance with the present invention without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A 2D1R process method based on driving current and window improvement, characterized in that: include: forming an n-well and a p-well by ion implantation, forming a deep trench region and a shallow trench region based on the n-well and the p-well by etching, and grinding and filling the shallow trench region to isolate the n-well from the p-well to form an n-well region and a p-well region; Performing ion implantation in the n-well region and the p-well region to form an n+ active region and a p+ active region respectively; Connecting the first diode where the n+ active region is located to the word line through a CT; connecting the second diode where the p+ active region is located to the reset line through a CT; connecting the p-type end of the first diode and the n-type end of the second diode to a metal layer through a CT, and connecting the metal layer to an RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a memory cell in the RRAM array; The RRAM array is made to perform read, write and erase operations according to a preset operation table.

2. The 2D1R process method based on drive current and window improvement according to claim 1, characterized in that: The process of forming the n-well and p-well by ion implantation includes: The n-well is formed by implanting n-type element ions, and the p-well is formed by implanting p-type element ions.

3. The 2D1R process method based on driving current and window improvement according to claim 2, characterized in that: During the process of injecting element ions, The implantation depth of the n-well or the p-well is adjusted by adjusting the implantation energy, and the concentration of the n-well or the p-well is adjusted by adjusting the implantation dose; wherein, The difference in depth and concentration between the n-well and the p-well causes reverse bias leakage between the n-well and the p-well, and also generates forward bias current.

4. The 2D1R process method based on driving current and window improvement according to claim 1, characterized in that: After forming the n-well and p-well, An np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well.

5. The 2D1R process method based on driving current and window improvement according to claim 1, characterized in that: During the read operation of the RRAM array, For a selected memory cell in the RRAM array, the bit line voltage is set to Vrd voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

6. The 2D1R process method based on driving current and window improvement according to claim 1, characterized in that: During the writing process of the RRAM array, For a selected memory cell in the RRAM array, the bit line voltage is set to Vset voltage, the word line voltage is set to 0V, and the reset line is set to 0V regardless of whether the cell is selected or not.

7. The 2D1R process method based on driving current and window improvement according to claim 6, characterized in that: During the erase operation of the RRAM array, A RESET voltage is applied to the reset line of the selected memory cell in the RRAM array, and 0V is applied to the bit line. A RESET voltage is applied to the unselected bit line in the RRAM array to suppress leakage.

8. An array based on drive current and window improvement, produced based on the 2D1R process method based on drive current and window improvement according to any one of claims 1 to 7, comprising: An n-well and a p-well, wherein the n-well and the p-well are formed by ion implantation; A deep trench region and a shallow trench region are formed on the n-well and the p-well by an etching process; The shallow trench region isolates the n-well and the p-well and divides them into an n-well region and a p-well region; Ions are implanted into the n-well region and the p-well region to form an n+ active region and a p+ active region respectively; The first diode where the n+ active region is located is connected to the word line via a CT; the second diode where the p+ active region is located is connected to the reset line via a CT; the p-type end of the first diode and the n-type end of the second diode are connected to a metal layer via the CT, and the metal layer is connected to the RRAM device to form an RRAM array; wherein two diodes and one RRAM device are connected to form a memory cell in the RRAM array; The RRAM array is used to perform read, write, and erase operations according to a preset operation table.

9. The array based on drive current and window improvement as claimed in claim 8, characterized in that: The n-well contains n-type element ions, and the p-well contains p-type element ions.

10. The array based on drive current and window improvement according to claim 8, characterized in that: An np junction is formed between the n-well and the p-well, and the np junction forms a reverse bias effect when a positive voltage is applied to the n-well relative to the p-well.

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