Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate including a device unit region and an isolation region located at the periphery of the device unit region; an isolation structure located in the substrate of the isolation region; a device gate structure located on the substrate of the device unit region; a source-drain doped layer embedded in the substrate of the device unit region on both sides of the device gate structure, the source-drain doped layer comprising a source-drain bulk layer, and the sidewall of the source-drain bulk layer at the edge of the device unit region being spaced apart from the isolation structure. In the semiconductor structure of the embodiment of the present application, the sidewall of the source-drain bulk layer at the edge of the device unit region is spaced apart from the isolation structure, so that the sidewall of the source-drain bulk layer at the edge of the device unit region is not in contact with the isolation structure, which is beneficial to prevent the diffusion of the doped ions in the source-drain bulk layer into the isolation structure, and further beneficial to prevent the problem of the increase of the extension resistance of the device, improve the length of diffusion region (LOD) effect, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit technology, more devices will be integrated onto chips, and chips will operate at higher speeds. Driven by these requirements, the geometric dimensions of devices will continue to shrink, and new materials, technologies, and manufacturing processes will be continuously adopted in chip manufacturing. Currently, the fabrication of semiconductor devices has reached the nanometer level, while the fabrication processes for conventional devices are gradually maturing.

[0003] In the semiconductor field, CMOS device manufacturing technology typically separates PMOS and NMOS processes. For example, compressive stress materials are used in PMOS device manufacturing, while tensile stress materials are used in NMOS devices to apply appropriate stress to the channel region, thereby improving carrier mobility. Embedded silicon germanium (SiGe) technology has become one of the main techniques for PMOS stress engineering because it can apply appropriate compressive stress to the channel region to improve hole mobility. Embedded silicon germanium process introduces compressive stress into the channel by forming an embedded SiGe layer in the source / drain regions. This stress distorts the semiconductor crystal lattice, generating uniaxial stress in the channel region, which in turn affects the bandgap alignment and charge transport performance of the semiconductor. By controlling the magnitude and distribution of stress in the final device, hole mobility is improved, thereby enhancing device performance.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, wherein the sidewalls of the source / drain body layer located at the edge of the device cell region are spaced apart from the isolation structure, so that the sidewalls of the source / drain body layer located at the edge of the device cell region are not in contact with the isolation structure. This is beneficial to prevent doped ions in the source / drain body layer from diffusing into the isolation structure, and is beneficial to prevent the problem of increased extension resistance of the device, thereby improving the length of diffusion (LOD) effect and enhancing the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a device cell region and an isolation region located on the periphery of the device cell region; an isolation structure located within the substrate of the isolation region; a device gate structure located on the substrate of the device cell region; and a source / drain doped layer embedded within the substrate of the device cell regions on both sides of the device gate structure, wherein the source / drain doped layer includes a source / drain body layer, and the sidewalls of the source / drain body layer located at the edge of the device cell region are spaced apart from the isolation structure.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including a device cell region and an isolation region located on the periphery of the device cell region; forming an isolation structure in the substrate of the isolation region; after forming the isolation structure, forming a gate structure on the substrate of the device cell region; forming source / drain doped layers in the substrate of the device cell regions on both sides of the gate structure, the source / drain doped layers including source / drain host layers, and the sidewalls of the source / drain host layers located at the edge of the device cell region being spaced apart from the isolation structure.

[0008] Compared with the prior art, the technical solution of the present invention has the following advantages: In the semiconductor structure provided by the present invention, the source / drain doped layer includes a source / drain host layer, and the sidewall of the source / drain host layer located at the edge of the device cell region is spaced apart from the isolation structure, so that the sidewall of the source / drain host layer located at the edge of the device cell region is not in contact with the isolation structure, which helps to prevent doped ions in the source / drain host layer from diffusing into the isolation structure, and correspondingly helps to prevent the problem of increased extension resistance of the device, thereby helping to improve the length of diffusion (LOD) effect and improve the performance of the semiconductor structure.

[0009] In the semiconductor structure formation method provided in this embodiment of the invention, in the step of forming the source / drain doped layer, the source / drain doped layer includes a source / drain host layer, and the sidewall of the source / drain host layer located at the edge of the device cell region is spaced apart from the isolation structure, so that the sidewall of the source / drain host layer located at the edge of the device cell region is not in contact with the isolation structure. This helps to prevent doped ions in the source / drain host layer from diffusing into the isolation structure, which in turn helps to prevent the problem of increased device elongation resistance, thereby improving the diffusion length (LOD) effect and enhancing the performance of the semiconductor structure.

[0010] In an optional embodiment, during the formation of the source / drain doped layer, the sidewall of the source / drain main body layer located at the edge of the device cell region has an angle with the isolation structure and forms a trench with the isolation structure; the method for forming the semiconductor structure further includes: after forming the source / drain doped layer, forming a capping layer that fills the trench and covers the surface of the source / drain main body layer, wherein the material of the capping layer is a silicon-containing semiconductor material, thereby isolating the contact between the source / drain main body layer and the isolation structure through the capping layer, thereby preventing the source / drain main body layer from contacting the isolation material, and thus ensuring that the device's extended resistance is effectively reduced and the diffusion length (LOD) effect is improved.

[0011] In an optional embodiment, the method for forming the semiconductor structure further includes: after forming the capping layer, conformally covering a stress layer on the surfaces of the isolation structure, the capping layer, and the gate structure. The stress layer helps to maintain the stress in the source / drain body layer, so that the stress of the source / drain body layer can be applied to the channel, preventing stress loss in the source / drain doped layer, thereby helping to ensure the improvement of carrier mobility in the channel region, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0012] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.

[0013] Figures 4 to 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0014] Figures 6 to 25 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using an example of a semiconductor structure. Figures 1 to 3 This is a schematic diagram of a semiconductor structure.

[0016] refer to Figure 1The semiconductor structure includes: a substrate 1, comprising a device cell region 1a and an isolation region 1b located on the periphery of the device cell region 1a; an isolation structure 2 located in the substrate 1 within the isolation region 1b; a gate structure 3 located on the substrate 1 of the device cell region 1a; and a source / drain doped layer 4 located in the substrate 1 of the device cell region 1a on both sides of the gate structure 3. The source / drain doped layer 4 includes a source / drain seed layer 5 and a source / drain host layer 6 located on the source / drain seed layer 5, and the sidewall of the source / drain host layer 6 located at the edge of the device cell region 1a is in contact with the isolation structure 2. The source / drain host layer 6 is a highly doped layer, and the doping concentration of the source / drain host layer 6 is higher than the doping concentration of the source / drain seed layer 5.

[0017] As an example, the semiconductor structure is used to form a PMOS device. To improve the performance of the PMOS device, the source / drain doped layer 4 employs an embedded germanium-silicon layer, which can apply compressive stress to the channel region, thereby improving hole mobility.

[0018] However, it is difficult to improve the length of diffusion (LOD) effect of PMOS devices by using embedded germanium-silicon layers.

[0019] Specifically, such as Figure 2 and Figure 3 As shown, a first device cell region 10a for forming a first device and a second device cell region 20a for forming a second device are shown respectively. The difference between the first device cell region 10a and the second device cell region 20a is that: in the first device cell region 10a, there are multiple gate structures 3, including a central gate structure 3 (2) and an edge gate structure 3 (1) located at the edge of the first device cell region 10a. The source and drain doped layers 4 located on both sides of the central gate structure 3 (2) are used as the central source and drain doped layers 4 (2), and the source and drain doped layers 4 located at the edge of the first device cell region 10a are used as the edge source and drain doped layers 4 (1). Correspondingly, the source and drain doped layers 4 of the first device corresponding to the central gate structure 3 (2) are not in contact with the isolation structure 2, while the edge source and drain doped layers 4 (1) are in contact with the isolation structure 2; in the second device cell region 20a, there is only one gate structure 3, and the sidewall of the source and drain doped layer 4 of the second device is in contact with the isolation structure 2.

[0020] Therefore, the distance SA1 or SB1 from the central gate structure 3 (2) of the first device unit region 10a to the isolation region 10b is different from the distance SA2 or SB2 from the gate structure 3 of the second device unit region 20a to the isolation region 20b; moreover, the sidewall of the source / drain doped layer 4 of the second device unit region 20a is in contact with the isolation structure 2, and the doped ions in the source / drain doped layer 4 can easily diffuse into the isolation structure 2, resulting in an increase in the extension resistance of the second device, which in turn affects the device performance; in addition, the structural integrity of the central source / drain doped layer 4 (2) of the first device unit region 10a is greater than the structural integrity of the source / drain doped layer 4 of the second device unit region 20a, and the volume of the central source / drain doped layer 4 of the first device unit region 10a is greater than the volume of the source / drain doped layer 4 of the second device unit region 20a.

[0021] Based on the above analysis, it can be seen that the performance of the first device and the second device is significantly different. The extension resistance of the second device is higher than that of the first device, which leads to a significant difference in the performance of the first device and the second device (e.g., saturation current, threshold voltage). The diffusion region length effect of the device is difficult to improve, especially the performance of the second device is poor.

[0022] To address the aforementioned technical problem, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a device cell region and an isolation region located on the periphery of the device cell region; an isolation structure located within the substrate of the isolation region; a device gate structure located on the substrate of the device cell region; and a source / drain doped layer embedded within the substrate of the device cell regions on both sides of the device gate structure, wherein the source / drain doped layer includes a source / drain host layer, and the sidewalls of the source / drain host layer located at the edge of the device cell region are spaced apart from the isolation structure.

[0023] In the semiconductor structure provided by the embodiments of the present invention, the sidewalls of the source / drain body layer located at the edge of the device cell region are spaced apart from the isolation structure, so that the sidewalls of the source / drain body layer located at the edge of the device cell region are not in contact with the isolation structure. This helps to prevent doped ions in the source / drain body layer from diffusing into the isolation structure, which in turn helps to prevent the problem of increased device elongation resistance, thereby improving the diffusion length (LOD) effect and enhancing the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 4 and Figure 5 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0025] In this embodiment, the semiconductor structure includes: a substrate 100, including a device cell region 100a and an isolation region 100b located on the periphery of the device cell region 100a; an isolation structure 110 located within the substrate 100 of the isolation region 100b; a device gate structure 300 located on the substrate 100 of the device cell region 100a; and a source / drain doped layer 200 embedded in the substrate 100 of the device cell region 100a on both sides of the device gate structure 300. The source / drain doped layer 200 includes a source / drain body layer 210, and the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110.

[0026] The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0027] The device unit region 100a is used to form a device; the isolation region 100b is used to achieve isolation between the device unit regions 100a.

[0028] In this embodiment, the substrate 100 includes a first device unit region 100a(1) for forming a first device and a second device unit region 100a(2) for forming a second device. The isolation region 100b is disposed on the outer periphery of the first device unit region 100a(1) and the second device unit region 100a(2). The device unit region 100a correspondingly includes the first device unit region 100a(1) and the second device unit region 100a(2).

[0029] In this embodiment, the first device and the second device are devices with different layout types in the integrated circuit design.

[0030] In this embodiment, the substrate 100 is a planar substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. In still other embodiments, depending on the type of transistor to be formed, the substrate may also be a three-dimensional substrate; for example, the substrate may include a substrate and fins located on the substrate.

[0031] The isolation structure 110 is used to achieve isolation between device unit regions 100.

[0032] In this embodiment, the isolation structure 110 is a shallow trench isolation structure (STI), and the material of the isolation structure 110 is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0033] In this embodiment, an isolation groove (not shown) is formed in the substrate 100 of the isolation area 100b, and the isolation structure 110 is filled in the isolation groove. The isolation groove is used to provide space for the formation of the isolation structure 110, and the isolation groove is also used to define the active area (AA) and the isolated area 100b of the substrate 100.

[0034] When the device is in operation, the device gate structure 300 is used to control the opening and closing of the conductive channel.

[0035] In this embodiment, the device gate structure 300 is a metal gate structure, which includes a high-k gate dielectric layer (not shown), a work function layer (not shown), and a metal gate electrode layer (not shown) stacked sequentially from bottom to top.

[0036] The high-k gate dielectric layer is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of HfO2. In other embodiments, the high-k gate dielectric layer may also be made of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0037] The work function layer is used to adjust the work function of the device gate structure 300, thereby adjusting the device threshold voltage. When forming a PMOS device, the work function layer is a P-type work function layer, and the material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN, and TiSiN; when forming an NMOS device, the work function layer is an N-type work function layer, and the material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN.

[0038] The gate electrode layer serves as an electrode, used to electrically lead out the device gate structure 300, thereby realizing the electrical connection between the device gate structure 300 and external circuits or other interconnect structures. The material of the gate electrode layer is a conductive material. The material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the material of the gate electrode layer is W.

[0039] In other embodiments, the device gate structure may also be a polysilicon gate structure. The device gate structure may accordingly include a polysilicon gate layer.

[0040] In this embodiment, there are multiple device gate structures 300 located in the first device unit region 100a(1); and there is one device gate structure 300 located in the second device unit region 100a(2).

[0041] In this embodiment, in the first device unit region 100a (1), the device gate structure 300 includes a central device gate 300 (1) and an edge device gate 300 (2) located at the edge of the first device unit region 100a (1).

[0042] In this embodiment, the semiconductor structure further includes a gate oxide layer 140, located between the device gate structure 300 and the substrate 100. The gate oxide layer 140 is used to achieve isolation between the device gate structure 300 and the channel. In this embodiment, the material of the gate oxide layer 140 is silicon oxide or silicon oxynitride.

[0043] In this embodiment, the semiconductor structure further includes a sidewall 130 located on the sidewall of the device gate structure 300. The sidewall 130 is used to protect the sidewall of the device gate structure 300 and also to define the formation location of the source / drain doped layer 200. In this embodiment, the sidewall 130 also covers the gate oxide layer 140.

[0044] The sidewall 130 can be a single-layer or multi-layer structure. As an example, the sidewall 130 is a multi-layer structure, which includes a first silicon oxide layer (not shown) located on the sidewall of the device gate structure 300, a silicon nitride layer (not shown) located on the first silicon oxide layer, and a second silicon oxide layer (not shown) located on the sidewall of the silicon nitride layer.

[0045] When the device is operating, the source / drain doped layer 200 is used to provide a carrier source. In this embodiment, the source / drain doped layer 200 is also used to provide stress to the channel region, thereby improving the carrier mobility.

[0046] The source / drain doped layer 200 includes a source / drain bulk layer 210. The source / drain bulk layer 210 has a high doping concentration and a large volume. If the source / drain bulk layer 210 is not adjusted, the doped ions in the source / drain bulk layer 210 located at the edge of the device cell region 100a are at high risk of diffusing into the isolation structure 110, which can easily lead to an increase in the device's extended resistance and significantly affect the device's performance.

[0047] Therefore, in this embodiment, by spacing the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a from the isolation structure 110, the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are not in contact with the isolation structure 110. This helps to prevent doped ions in the source / drain body layer 210 from diffusing into the isolation structure 110, which in turn helps to prevent the problem of increased extension resistance of the device, thereby improving the length of diffusion (LOD) effect and enhancing the performance of the semiconductor structure.

[0048] In this embodiment, the source / drain main body layer 210 located at the edge of the device unit region 100a has an angle with the isolation structure 110, and the source / drain main body layer 210 located at the edge of the device unit region 100a forms a trench 230 with the isolation structure 110.

[0049] Specifically, in this embodiment, the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a on the side opposite to the isolation structure 110 is... <111> The crystal plane is such that the angle between the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a and the surface of the substrate 100 is about 45°, so as to ensure that the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a will not come into contact with the isolation structure 110.

[0050] As an example, the substrate 100 of the device cell region 100a is used to form a PMOS device, and the material of the source / drain doped layer 200 includes SiGe.

[0051] By selecting SiGe material, since Ge's lattice constant is greater than Si's, and utilizing the lattice mismatch between silicon and germanium, SiGe's lattice constant is greater than silicon's. This allows the source / drain doped layer 200 to generate compressive stress pushing towards the channel, thereby improving hole mobility, current drive capability, and circuit speed. Furthermore, SiGe material is relatively sensitive to the environment, and in existing PMOS devices using SiGe as the source / drain doped layer 200 material, the LOD effect has been difficult to improve. In this embodiment, by adjusting the morphology of the source / drain main layer 210, the sidewalls of the source / drain main layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110, which significantly improves the performance of the PMOS device.

[0052] In other embodiments, when forming an NMOS device, the source / drain doped layer is made of SiC. Carbon has a lower lattice constant than silicon. Utilizing the lattice mismatch between silicon and carbon, SiC's lattice constant is lower than silicon's, and since carbon's lattice constant is much smaller than silicon's, SiC requires only a small number of carbon atoms to achieve high stress. This allows the source / drain doped layer to generate tensile stress in the lateral channel, thereby improving electron mobility.

[0053] The source / drain doped layer 200 is doped with ions. In this embodiment, taking the formation of a PMOS device as an example, the source / drain doped layer 200 is doped with P-type ions, which can be B ions, Ga ions, or In ions. In other embodiments, when forming an NMOS device, the source / drain doped layer is correspondingly doped with N-type ions, which can be P ions, As ions, or Sb ions.

[0054] In this embodiment, the semiconductor structure includes: a recess 260 (referring to a reference). Figure 10 and Figure 11 The source and drain doped layers 200 are located within the substrate 100 of the device cell regions 100a on both sides of the device gate structure 300; the source and drain doped layers 200 are located within the groove 260.

[0055] The groove 260 is used to provide space for the formation of the source / drain doped layer 200. The groove 260 is formed by etching the substrate 100 of the device cell region 100a on both sides of the device gate structure 200.

[0056] In this embodiment, the groove 260 is a sigma (Σ) type structure. The source / drain doped layer 200 is formed by epitaxial growth in the groove 260, which is a sigma type structure, thereby exposing the substrate 100 surface to the groove 260. <111> The crystal orientation allows the source / drain host layer 210 to selectively align with the crystal orientation during the epitaxial growth process of forming the source / drain doped layer 200. <111> The crystal-oriented epitaxial growth allows for adjustment of the growth morphology of the source / drain body layer 210, preventing the source / drain body layer 210 located at the edge of the device cell region 100a from growing in a direction close to the isolation structure 110, thereby ensuring that the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110.

[0057] In this embodiment, the source / drain doped layer 200 further includes a source / drain seed layer 220, located between the substrate 100 exposed by the groove 260 and the source / drain main body layer 210, wherein the doping concentration of the source / drain seed layer 220 is lower than the doping concentration of the source / drain main body layer 210.

[0058] The source / drain seed layer 220 is used as an epitaxial seed layer when forming the source / drain body layer 210, that is, the source / drain body layer 210 is formed by epitaxial growth based on the source / drain seed layer 220. In addition, the source / drain seed layer 220 is also helpful in improving the defects of the sidewalls and bottomwalls of the groove 260, thereby improving the epitaxial growth quality of the source / drain body layer 210. Furthermore, the source / drain seed layer 220 is also used to isolate the source / drain body layer 210 with a high doping concentration from the substrate 100, thereby significantly reducing the probability of doped ions in the source / drain body layer 210 diffusing into the substrate 100.

[0059] In this embodiment, the doping concentration and volume of the source / drain seed layer 220 are both smaller than those of the source / drain main layer 210. The probability of the source / drain seed layer 220 located at the edge of the device cell region 100a contacting the isolation structure 110, and the probability of doped ions in the source / drain seed layer 220 diffusing into the isolation structure 110, are both low. Therefore, by adjusting the morphology of the source / drain main layer 210, the source / drain main layer 210 located at the edge of the device cell region 100a does not contact the isolation structure 110. This significantly reduces the probability of doped ions in the source / drain doped layer 200 diffusing into the isolation structure 110 and improves the diffusion region length effect. At the same time, there is no need to adjust the morphology of the source / drain seed layer 220, which also helps to improve compatibility with existing processes.

[0060] It should be noted that in the first device cell region 100a(1), the device gate structure 300 includes a central device gate 300(1) and an edge device gate 300(2) located at the edge of the first device cell region 100a(1). Correspondingly, the source / drain doped layer 200 located between the edge device gate 300(2) and the isolation region 100b serves as the edge source / drain doped layer 200(2), thereby making the source / drain doped layer 200 of the first device corresponding to the central device gate 300(1) far away from the isolation structure 110, thus ensuring the integrity of the source / drain doped layer 200 of the first device corresponding to the central device gate 300(1).

[0061] In the second device cell region 100a(2), there is one device gate structure 300, and the source / drain doped layer 200 of the second device is located at the edge of the second device cell region 100a(2) and close to the isolation structure 110.

[0062] Accordingly, in this embodiment, by adjusting the morphology of the source / drain body layer 210, the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110, so as to prevent the source / drain body layer 210 of the second device from contacting the isolation structure 110, thereby significantly improving the performance of the second device, especially significantly improving the performance when the second device is a PMOS device.

[0063] In this embodiment, a trench 230 is formed between the sidewall of the source / drain body layer 210 located at the edge of the device unit region 100a and the isolation structure 110.

[0064] In this embodiment, the semiconductor structure further includes a metal silicide layer 310, located within the trench 230 and covering the surface of the source / drain host layer 210.

[0065] The metal silicide layer 310 is used to reduce the contact resistance between the source / drain doped layer 200 and the source / drain contact plug (not shown). The material of the metal silicide layer 310 can be a nickel silicon compound, a cobalt silicon compound, or a titanium silicon compound.

[0066] In this embodiment, during the formation of the semiconductor structure, before the formation of the metal silicide layer 210, a capping layer covering the surface of the source / drain host layer 210 is also formed in the trench 230. During the metal silicide process, the metal silicide layer 310 is formed by the reaction of the capping layer and the metal layer.

[0067] The capping layer is made of silicon-containing semiconductor material. By setting a capping layer made of silicon-containing semiconductor material in the trench 230 during the formation of the semiconductor structure, the contact between the source / drain body layer 210 and the isolation structure 110 can be isolated during the formation of the semiconductor structure, thereby preventing the source / drain body layer 210 from contacting the isolation material, and thus ensuring that the extension resistance of the device can be effectively reduced and the diffusion length (LOD) effect can be improved.

[0068] In this embodiment, during the formation of the metal silicide layer 310, the capping layer reacts completely with the metal layer and transforms into the metal silicide layer 310. Therefore, no residual capping layer remains in the semiconductor structure.

[0069] In other embodiments, when a sidewall layer is formed on the sidewall of the sidewall during the formation of the semiconductor structure, and the sidewall layer also covers part of the top surface of the capping layer, part of the capping layer does not react with the metal layer under the covering effect of the sidewall layer. Accordingly, the semiconductor structure also includes the sidewall layer located on the sidewall of the sidewall and the capping layer located between the bottom of the sidewall layer and the source / drain doped layer.

[0070] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 270 located on the substrate 100 on the side of the device gate structure 300. In this embodiment, the interlayer dielectric layer 270 covers the sidewall of the sidewall 130 and the surface of the metal silicide layer 310, and the interlayer dielectric layer 270 also fills the trench 230.

[0071] The interlayer dielectric layer 270 is used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer 270 is a dielectric material. In this embodiment, the material of the interlayer dielectric layer 270 is silicon oxide.

[0072] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 25 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. The semiconductor structure formation method of this embodiment will be described in detail below with reference to the accompanying drawings.

[0073] refer to Figure 6 and Figure 7 A substrate 100 is provided, including a device cell region 100a and an isolation region 100b located on the periphery of the device cell region 100a.

[0074] The substrate 100 is used to provide a process platform for the fabrication process. The device cell region 100a is used to form a device; the isolation region 100b is used to achieve isolation between the device cell regions 100a.

[0075] In this embodiment, the substrate 100 includes a first device unit region 100a(1) for forming a first device and a second device unit region 100a(2) for forming a second device. The isolation region 100b is disposed on the outer periphery of the first device unit region 100a(1) and the second device unit region 100a(2). The device unit region 100a correspondingly includes the first device unit region 100a(1) and the second device unit region 100a(2).

[0076] In this embodiment, the first device and the second device are devices with different layout types in the integrated circuit design.

[0077] In this embodiment, the substrate 100 is a planar substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. In still other embodiments, depending on the type of transistor to be formed, the substrate may also be a three-dimensional substrate; for example, the substrate may include a substrate and fins located on the substrate.

[0078] Continue to refer to Figure 6 and Figure 7 An isolation structure 110 is formed in the substrate 100 of the isolation zone 100b.

[0079] The isolation structure 110 is used to achieve isolation between the device unit regions 100a.

[0080] In this embodiment, the isolation structure 110 is a shallow trench isolation structure (STI), and the material of the isolation structure 110 is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0081] In this embodiment, the step of forming the isolation structure 110 includes: forming an isolation groove (not shown) in the substrate 100 of the isolation region 100b; and forming the isolation structure 110 in the isolation groove.

[0082] The isolation groove is used to provide a spatial location for forming the isolation structure 110, and the isolation groove is also used to define the active area (AA) and isolated area 100b of the substrate 100.

[0083] Specifically, the step of forming the isolation structure 110 in the isolation groove includes: filling the isolation groove with an isolation material layer (not shown), the isolation material layer also covering the top surface of the substrate 100; removing the isolation material layer located on the top surface of the substrate 100, and the remaining isolation material layer in the isolation groove is used as the isolation structure 110.

[0084] In this embodiment, the method for forming the semiconductor structure further includes forming a gate oxide layer 140 on the top surface of the substrate 100. The gate oxide layer 140 is used to achieve isolation between the device gate structure and the channel. In this embodiment, the material of the gate oxide layer 140 is silicon oxide or silicon oxynitride.

[0085] refer to Figure 8 and Figure 9 After the isolation structure 110 is formed, a gate structure 120 is formed on the substrate 100 of the device cell region 100a. In this embodiment, the gate structure 120 is formed on the gate oxide layer 140.

[0086] In this embodiment, the gate structure 120 is a pseudo-gate structure, used to occupy space for forming the device gate structure. In this embodiment, the gate structure 120 is a polysilicon gate structure. The gate structure 120 includes a polysilicon gate layer.

[0087] In this embodiment, in the step of forming the gate structure 120, there are multiple gate structures 120 formed in the first device unit region 100a (1); and only one gate structure 120 formed in the second device unit region 100a (2). In this embodiment, in the first device unit region 100a (1), the gate structure 120 includes a central gate 120 (1) and an edge gate 120 (2) located at the edge of the first device unit region 100a (1).

[0088] In this embodiment, the method for forming the semiconductor structure further includes forming a sidewall 130 on the sidewall of the gate structure 120.

[0089] The sidewall 130 is used to protect the sidewalls of the gate structure 120, and the sidewall 130 is also used to define the formation locations of the source and drain doped layers. In this embodiment, the sidewall 130 also covers a portion of the gate oxide layer 140.

[0090] The sidewall 130 is a single-layer or multilayer structure. As an example, the sidewall 130 is a multilayer structure, comprising a first silicon oxide layer (not shown) located on the sidewall of the gate structure 120, a silicon nitride layer (not shown) located on the first silicon oxide layer, and a second silicon oxide layer (not shown) located on the sidewall of the silicon nitride layer.

[0091] refer to Figures 10 to 15 A source / drain doped layer 200 is formed in the substrate 100 of the device cell region 100a on both sides of the gate structure 120. The source / drain doped layer 200 includes a source / drain bulk layer 210, and the sidewall of the source / drain bulk layer 210 located at the edge of the device cell region 100a is spaced apart from the isolation structure 110.

[0092] When the device is operating, the source / drain doped layer 200 is used to provide a carrier source. In this embodiment, the source / drain doped layer 200 is also used to provide stress to the channel region, thereby improving the carrier mobility.

[0093] The source / drain host layer 210 has a high doping concentration and a large volume. If the source / drain host layer 210 is not adjusted, the doped ions in the source / drain host layer 210 located at the edge of the device cell region 100a are at high risk of diffusing into the isolation structure 110, which can easily lead to an increase in the device's extended resistance and have a significant impact on the device's performance.

[0094] Therefore, in this embodiment, by spacing the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a from the isolation structure 110, the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are not in contact with the isolation structure 110. This helps to prevent doped ions in the source / drain body layer 210 from diffusing into the isolation structure 110, thereby preventing the problem of increased extension resistance of the device. This, in turn, helps to improve the length of diffusion (LOD) effect and improve the performance of the semiconductor structure.

[0095] Specifically, by adjusting the growth morphology of the source / drain body layer 210, the sidewalls of the source / drain body layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110.

[0096] As an example, in this embodiment, the substrate 100 of the device cell region 100a is used to form a PMOS device, and the material of the source / drain doped layer 200 includes SiGe.

[0097] By selecting SiGe material, since Ge's lattice constant is greater than Si's, and utilizing the lattice mismatch between silicon and germanium, SiGe's lattice constant is greater than silicon's. This allows the source / drain doped layer 200 to generate compressive stress pushing towards the channel, thereby improving hole mobility, current drive capability, and circuit speed. Furthermore, SiGe material is relatively sensitive to the environment; in existing processes, when SiGe is used as the source / drain doped layer 200 material in PMOS devices, the LOD effect of the PMOS device has been difficult to improve. In this embodiment, by adjusting the morphology of the source / drain main layer 210, such that the sidewalls of the source / drain main layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110, the performance of the PMOS device is significantly improved.

[0098] In other embodiments, when forming an NMOS device, the source / drain doped layer is made of SiC. Carbon has a lower lattice constant than silicon. Utilizing the lattice mismatch between silicon and carbon, SiC's lattice constant is lower than silicon's, and since carbon's lattice constant is much smaller than silicon's, SiC requires only a small number of carbon atoms to achieve high stress. This allows the source / drain doped layer to generate tensile stress in the lateral channel, thereby improving electron mobility.

[0099] The source / drain doped layer 200 is doped with ions. In this embodiment, taking the formation of a PMOS device as an example, the source / drain doped layer 200 is doped with P-type ions, which can be B ions, Ga ions, or In ions. In other embodiments, when forming an NMOS device, the source / drain doped layer is correspondingly doped with N-type ions, which can be P ions, As ions, or Sb ions.

[0100] The steps for forming the source / drain doped layer 200 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0101] like Figure 10 and Figure 11 As shown, grooves 260 are formed in the substrate 100 of the device cell regions 100a on both sides of the gate structure 120, and the grooves 260 located at the edge of the device cell regions 100a expose part of the sidewalls of the isolation structure 110. The grooves 260 are used to provide space for the formation of source and drain doped layers.

[0102] In this embodiment, during the process of forming the groove 260, the gate oxide layer 140 located on the top surface of the substrate 100 on both sides of the gate structure 120 is also etched away.

[0103] Specifically, the substrate 100 of the device unit region 100a on both sides of the gate structure 120 is etched by sequentially using dry etching and wet etching processes to form the groove 260.

[0104] In this embodiment, during the formation of the groove 260, the groove 260 is a sigma (Σ) type structure.

[0105] Subsequently, source and drain doped layers are epitaxially grown in the groove 260, wherein the groove 260 is a sigma-type structure, thereby exposing the substrate 100 surface to the groove 260, including <111> The crystal orientation allows the source / drain host layer to selectively align with the crystal orientation during the epitaxial growth process to form the source / drain doped layer. <111> Crystal-oriented epitaxial growth is used, and since the source / drain body layer will not grow epitaxially on the sidewall of the isolation structure 110 exposed by the groove 260, the source / drain body layer located at the edge of the device cell region 100a is prevented from growing in a direction close to the isolation structure 110, so as to ensure that the source / drain body layer located at the edge of the device cell region 100a is spaced apart from the isolation structure 110.

[0106] like Figures 12 to 15 As shown, the source / drain doped layer 200 is formed in the groove 260.

[0107] Specifically, the step of forming the source / drain doped layer 200 in the groove 260 includes: as follows Figure 12 and Figure 13As shown, a source / drain seed layer 220 is formed on the surface of the substrate 100 exposed in the groove 200; as Figure 14 and Figure 15 As shown, a source / drain body layer 210 is formed on the source / drain seed layer 220, and the doping concentration of the source / drain body layer 210 is higher than that of the source / drain seed layer 220.

[0108] Therefore, in this embodiment, the source / drain doped layer 200 includes a source / drain seed layer 220 that is in contact with the surface of the substrate 100 exposed by the groove 260, and a source / drain body layer 210 located on the source / drain seed layer 220.

[0109] The source / drain seed layer 220 is used as an epitaxial seed layer when forming the source / drain main body layer 210. That is, the source / drain main body layer 210 is formed by epitaxial growth based on the source / drain seed layer 220. Furthermore, the source / drain seed layer 220 is also beneficial to improve the defects of the sidewalls and bottomwalls of the groove 260, which is beneficial to improve the epitaxial growth quality of the source / drain main body layer 210. In addition, the source / drain seed layer 220 is also used to isolate the source / drain main body layer 210 with a high doping concentration from the substrate 100, thereby reducing the probability of dopant ions in the source / drain main body layer 210 diffusing into the substrate 100.

[0110] In this embodiment, the doping concentration and volume of the source / drain seed layer 220 are both smaller than those of the source / drain body layer 210. The probability of the source / drain seed layer 220 located at the edge of the device cell region 100a contacting the isolation structure 110, and the probability of doped ions in the source / drain seed layer 220 diffusing into the isolation structure 110, are both low. Therefore, by adjusting the morphology of the source / drain body layer 210, this embodiment ensures that the source / drain body layer 210 located at the edge of the device cell region 100a does not contact the isolation structure 110, which can significantly reduce the probability of source / drain doped ions diffusing into the isolation structure 110 and improve the diffusion region length effect. At the same time, there is no need to adjust the formation process and growth morphology of the source / drain seed layer 220, which also helps to improve compatibility with existing processes.

[0111] In this embodiment, the source-drain seed layer 220 is formed using the Selective Epitaxy Growth (SEG) process.

[0112] In this embodiment, after the source / drain seed layer 220 is formed, an epitaxial layer is formed using an epitaxial process, and in the process of forming the epitaxial layer, ions are self-doped in situ to form the source / drain host layer 210.

[0113] In this embodiment, the step of forming the source / drain body layer 210 includes: adjusting the process conditions (Recipe) of the epitaxial process to make the source / drain body layer 210 along... <111> Crystalline epitaxial growth.

[0114] By causing the source / drain body layer 210 along <111> The source / drain body layer 210 located at the edge of the device cell region 100a is grown epitaxially to adjust the growth morphology of the layer, thereby ensuring that the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a has an angle with the sidewall of the isolation structure 110, thus ensuring that the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a will not contact the isolation structure 110.

[0115] In this embodiment, a portion of the sidewall of the isolation structure 110 is exposed on one side of the groove 260 at the edge of the device cell region 100a. During the epitaxial process of forming the source / drain body layer 210, the source / drain body layer 210 located at the edge of the device cell region 100a will not epitaxially grow on the sidewall of the isolation structure 110 exposed by the groove 260. Accordingly, after forming the source / drain body layer 210, the sidewall of the source / drain body layer 210 located at the edge of the device cell region 100a on the side opposite to the isolation structure 110 is... <111> The crystal plane is such that the source / drain body layer 210 located at the edge of the device cell region 100a does not come into contact with the isolation structure 110.

[0116] Specifically, adjusting the process conditions of the epitaxial process may include: adjusting process parameters such as the flow rate, temperature, and pressure of the reaction gas in the epitaxial process, so that the source / drain host layer 210 can move along... <111> Epitaxial growth is performed in the crystal orientation.

[0117] It should be noted that in the first device cell region 100a(1), the gate structure 120 includes a central gate 120(1) and an edge gate 120(2). Correspondingly, the source / drain doped layer 200 located between the edge gate 120(2) and the isolation region 100b serves as the edge source / drain doped layer 200(2), thereby making the source / drain doped layer 200 of the first device corresponding to the central gate 120(1) far away from the isolation structure 110, thus ensuring the integrity of the source / drain doped layer 200 of the first device.

[0118] In the second device cell region 100a(2), there is one gate structure 120. The source / drain doped layer 200 of the second device is located at the edge of the second device cell region 100a(2) and close to the isolation structure 110. Accordingly, in this embodiment, by adjusting the morphology of the source / drain main layer 210, the sidewalls of the source / drain main layer 210 located at the edge of the device cell region 100a are spaced apart from the isolation structure 110. This helps to prevent the source / drain main layer 210 of the second device from contacting the isolation structure 110, thereby significantly improving the performance of the second device, especially when the second device is a PMOS device.

[0119] In this embodiment, during the formation of the source / drain doped layer 200, the sidewall of the source / drain main layer 210 located at the edge of the device cell region 100a has an angle with the isolation structure 110, and a trench 230 is formed between the sidewall of the source / drain main layer 210 located at the edge of the device cell region 100a and the isolation structure 110.

[0120] Reference Figure 16 and Figure 17 The method for forming the semiconductor structure further includes: after forming the source / drain doped layer 200, forming a capping layer 240 covering the surface of the source / drain host layer 210 in the trench 230, wherein the material of the capping layer 240 is a silicon-containing semiconductor material.

[0121] By forming the capping layer 240, which is made of silicon semiconductor material, the source / drain body layer 210 can be isolated from the isolation structure 110, thereby preventing the source / drain body layer 210 from contacting the isolation material, and thus ensuring that the extension resistance of the device can be effectively reduced and the length of diffusion region (LOD) effect can be improved.

[0122] Among these factors, the difference in thermal expansion coefficients between the isolation material and the source / drain host layer 210 material is smaller. Therefore, by forming the capping layer 240 of the silicon semiconductor material to isolate the source / drain host layer 210 from the isolation structure 110, it is beneficial to prevent the isolation structure 110 from generating stress on the source / drain host layer 210, thereby preventing changes in the device's electrical parameters. The capping layer 240 also helps maintain stress in the source / drain host layer 210, allowing the source / drain doped layer 200 to apply stress to the channel region.

[0123] Furthermore, the capping layer 240 is made of silicon-containing semiconductor material. In the subsequent self-aligned metal silicide process, the capping layer 240 is also used to react with the metal layer to form a metal silicide layer with low resistance. The metal silicide layer is located between the source / drain doped layer 200 and the source / drain contact plug, which helps to reduce the contact resistance between the source / drain doped layer 200 and the source / drain contact plug.

[0124] In this embodiment, the capping layer 240 is made of silicon or germanium-silicon. Silicon is a commonly used reactive material in self-aligned metal silicide processes in semiconductor manufacturing, which improves process compatibility. When the capping layer 240 is made of germanium-silicon, it is a low-germanium-concentration germanium-silicon, thereby ensuring that the capping layer 240 can react with the metal layer to form a metal silicide with low resistance.

[0125] In this embodiment, the process for forming the capping layer 240 includes selective epitaxy (SEG). SEG utilizes the basic principles of epitaxial growth and the characteristic that epitaxial materials are difficult to nucleate into films on insulators, thereby enabling epitaxial growth only in specific regions of the semiconductor structure. Specifically, in this embodiment, the exposed semiconductor material is only the surface of the source / drain host layer 210, thus allowing the material of the capping layer 240 to grow selectively on the surface of the source / drain host layer 210. This eliminates the need to remove the capping layer material located on other film structures, which helps reduce process complexity.

[0126] refer to Figure 18 and Figure 19 In this embodiment, the method for forming the semiconductor structure further includes: after forming the capping layer 240, conformally covering the surface of the isolation structure 110, the capping layer 240, and the gate structure 120 with a stress layer 250. Specifically, the stress layer 250 conformally covers the sidewalls and top of the sidewall 130.

[0127] By forming the stress layer 250, it is beneficial to maintain the stress in the source / drain host layer 210, so that the stress of the source / drain host layer 210 can be applied to the channel, preventing stress loss in the source / drain doped layer 200, thereby ensuring the effect of the source / drain doped layer 200 on improving the carrier mobility in the channel region, and thus improving the performance of the semiconductor structure.

[0128] In this embodiment, the stress layer 250 is an integral structure, which helps to prevent stress loss in the stress layer 250 and can further improve the stress maintenance effect in the source / drain body layer 210.

[0129] In this embodiment, the stress layer 250 is made of silicon nitride. Silicon nitride is a commonly used stress film material, which is beneficial for improving process compatibility.

[0130] In this embodiment, the process for forming the stress layer 250 includes atomic layer deposition (ALD). The stepped coverage capability of ALD improves the conformal coverage of the stress layer 250 on the surfaces of the isolation structure 110, the capping layer 240, and the gate structure 120. Furthermore, the thin film formed by ALD has advantages such as high density, good thickness uniformity, high film quality, and few defects, which helps improve the film quality of the stress layer 250 and correspondingly enhances the stress retention effect of the stress layer 250 on the source / drain doped layer 200.

[0131] In other embodiments, other suitable deposition processes (e.g., chemical vapor deposition) can be used to form the stress layer. The chemical deposition process can be plasma-enhanced chemical vapor deposition (PECVD).

[0132] It should be noted that, in this embodiment, after forming the stress layer 250, the forming method further includes: annealing the stress layer 250.

[0133] By annealing the stress layer 250, the stress in the stress layer 250 is transferred to the source / drain doped layer 200 and the gate structure 120. The stress is then applied to the channel through the source / drain doped layer 200 and the gate structure 120, and the stress is memorized by the source / drain doped layer 200 and the gate structure 120.

[0134] refer to Figure 20 and Figure 21 In this embodiment, the method for forming the semiconductor structure further includes: removing the stress layer 250 after annealing the stress layer 250.

[0135] Since the stress in the stress layer 250 has been transferred to the source / drain doped layer 200 and the gate structure 120 during the aforementioned annealing process, and stress has also been applied to the channel, removing the stress layer 250 has little impact on the stress in the source / drain doped layer 200, the gate structure 120, and the channel. Furthermore, removing the stress layer 250 exposes the top surface of the capping layer 240 and the gate structure 120, which facilitates subsequent process steps (e.g., metal silicide process).

[0136] In this embodiment, a wet etching process is used to remove the stress layer 250. The wet etching process has isotropic etching characteristics, thereby enabling the conformal removal of the stress layer 250 covering the surfaces of the isolation structure 110, the capping layer 240, and the gate structure 120. As an example, the stress layer 250 is made of silicon nitride, and the etching solution used in the wet etching process can be a hot phosphoric acid solution.

[0137] Reference Figure 22 and Figure 23 In this embodiment, after removing the stress layer 250, the method for forming the semiconductor structure further includes: forming a metal layer (not shown) on the top surface of the capping layer 240, the top surface of the gate structure 120, the sidewall and top surface of the sidewall 130, and the top surface and part of the sidewall of the isolation structure 110; performing heat treatment to react the metal layer with the capping layer 240 to form a metal silicide layer 310; and removing the remaining metal layer.

[0138] The metal silicide layer 310 is used to reduce the contact resistance between the source / drain doped layer 200 and the subsequent source / drain contact plugs. The material of the metal silicide layer 310 can be a nickel silicon compound, a cobalt silicon compound, or a titanium silicon compound.

[0139] During the formation of the metal silicide layer 310, the metal layer reacts only with the capping layer 240, thereby achieving self-alignment of the position of the metal silicide layer 310. Accordingly, after the metal silicide layer 310 is formed, the unreacted metal layer can be selectively removed.

[0140] As an example, during the formation of the metal silicide layer 310, the capping layer 240 reacts completely with the metal layer and transforms into the metal silicide layer 310. Therefore, after the metal silicide layer 310 is formed, no residual capping layer 240 remains in the semiconductor structure.

[0141] In other embodiments, after removing the stress layer and before forming the metal layer, the method for forming the semiconductor structure may further include: forming a sidewall layer on the sidewall of the sidewall, the sidewall layer further covering a portion of the top surface of the capping layer. Accordingly, during the formation of the metal silicide layer, a portion of the capping layer does not react with the metal layer under the covering effect of the sidewall layer, and after the metal silicide layer is formed, the portion of the capping layer covered by the sidewall layer is retained in the semiconductor structure.

[0142] In this embodiment, the gate structure 120 is a pseudo-gate structure. Therefore, referring to... Figure 24 and Figure 25The method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 270 on a substrate 100 on the side of the gate structure 120 to expose the top of the gate structure 120; removing the gate structure 120 to form a gate opening (not shown); and forming a device gate structure 300 in the gate opening.

[0143] The interlayer dielectric layer 270 is used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer 270 is a dielectric material. In this embodiment, the material of the interlayer dielectric layer 270 is silicon oxide.

[0144] In this embodiment, the interlayer dielectric layer 270 covers the metal silicide layer 310.

[0145] When the device is in operation, the device gate structure 300 is used to control the opening and closing of the conductive channel.

[0146] In this embodiment, the device gate structure 300 is a metal gate structure, which includes a high-k gate dielectric layer (not shown), a work function layer (not shown), and a metal gate electrode layer (not shown) stacked sequentially from bottom to top.

[0147] The high-k gate dielectric layer is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of HfO2. In other embodiments, the high-k gate dielectric layer may also be made of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0148] The work function layer is used to adjust the work function of the device gate structure 300, thereby adjusting the device threshold voltage. When forming a PMOS device, the work function layer is a P-type work function layer, and the material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN, and TiSiN; when forming an NMOS device, the work function layer is an N-type work function layer, and the material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN.

[0149] The gate electrode layer serves as an electrode, used to draw out the electrical properties of the device gate structure 300, thereby achieving electrical connection between the gate structure 300 and external circuits or other interconnect structures. The gate electrode layer is made of a conductive material. The material of the gate electrode layer can be Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the material of the gate electrode layer is W.

[0150] In this embodiment, there are multiple device gate structures 300 located in the first device unit region 100a(1); and there is one device gate structure 300 located in the second device unit region 100a(2).

[0151] It should be noted that in the first device unit region 100a (1), the device gate structure 300 includes a central device gate 300 (1) and an edge device gate 300 (2) located at the edge of the first device unit region 100a (1).

[0152] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a device cell region and an isolation region located on the periphery of the device cell region; An isolation structure is located within the base of the isolation zone; The device gate structure is located on the substrate of the device cell region; A source / drain doped layer is embedded in the substrate of the device cell region on both sides of the device gate structure. The source / drain doped layer includes a source / drain body layer and a source / drain seed layer. The sidewall of the source / drain body layer located at the edge of the device cell region is spaced apart from the isolation structure, such that the sidewall of the source / drain body layer located at the edge of the device cell region is not in contact with the isolation structure. Specifically, the sidewall of the source / drain body layer located at the edge of the device cell region on the side opposite to the isolation structure is... <111> The crystal plane has an angle between the sidewall of the source / drain body layer located at the edge of the device cell region and the isolation structure, and forms a trench with the isolation structure; the source / drain doped layer is doped with ions, and the source / drain seed layer is located between the substrate exposed by the trench and the source / drain body layer, and the doping concentration of the source / drain seed layer is lower than the doping concentration of the source / drain body layer; A metal silicide layer is located within the trench and covers the surface of the source / drain host layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes: a groove located within the substrate of the device cell regions on both sides of the device gate structure; and the source / drain doped layer located within the groove.

3. The semiconductor structure as described in claim 2, characterized in that, The groove has a sigma-type structure.

4. The semiconductor structure as described in claim 1, characterized in that, When forming a PMOS device, the material of the source and drain doped layers includes SiGe; When forming an NMOS device, the material of the source and drain doped layers includes SiC.

5. The semiconductor structure as described in claim 1, characterized in that, The substrate includes a first device cell region for forming a first device and a second device cell region for forming a second device, wherein the first device cell region and the second device cell region are isolated by the isolation region. There are multiple device gate structures located in the first device unit region; there is one device gate structure located in the second device unit region.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a device cell region and an isolation region located on the periphery of the device cell region; An isolation structure is formed in the substrate of the isolation zone; After the isolation structure is formed, a gate structure is formed on the substrate of the device cell region; Source / drain doped layers are formed within the substrate of the device cell regions on both sides of the gate structure. Each source / drain doped layer includes a source / drain body layer and a source / drain seed layer. The sidewalls of the source / drain body layer located at the edge of the device cell region are spaced apart from the isolation structure, such that the sidewalls of the source / drain body layer located at the edge of the device cell region are not in contact with the isolation structure. Specifically, the sidewall of the source / drain body layer located at the edge of the device cell region on the opposite side of the isolation structure is... <111> The crystal plane has an angle between the sidewall of the source / drain body layer located at the edge of the device cell region and the isolation structure, and forms a trench with the isolation structure; the source / drain doped layer is doped with ions, and the source / drain seed layer is located between the substrate exposed by the trench and the source / drain body layer, and the doping concentration of the source / drain seed layer is lower than the doping concentration of the source / drain body layer; A capping layer is formed in the trench to cover the surface of the source / drain body layer, and the material of the capping layer is a silicon-containing semiconductor material; A metal silicide layer is formed by the reaction of the cap layer and the metal layer.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The step of forming the source / drain doped layer includes: forming a groove in the substrate of the device cell region on both sides of the gate structure, wherein the groove located at the edge of the device cell region exposes part of the sidewall of the isolation structure; The source / drain doped layer is formed in the groove.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The substrate of the device unit region on both sides of the gate structure is etched by sequentially using dry etching and wet etching processes to form the groove.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, During the formation of the groove, the groove has a sigma-type structure.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming the source / drain doped layer in the groove includes: forming a source / drain seed layer on the substrate surface exposed in the groove; and forming the source / drain body layer on the source / drain seed layer, wherein the doping concentration of the source / drain body layer is higher than that of the source / drain seed layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, An epitaxial layer is formed using an epitaxial process, and in the process of forming the epitaxial layer, ions are self-doped in situ to form the source / drain host layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the source / drain host layer includes: adjusting the process conditions of the epitaxial process to make the source / drain host layer along... <111> Crystalline epitaxial growth.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the semiconductor structure further includes: after forming the capping layer, conformally covering the stress layer on the surfaces of the isolation structure, the capping layer, and the gate structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the semiconductor structure further includes annealing the stress layer after it has been formed.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of providing a substrate, the substrate includes a first device cell region for forming a first device and a second device cell region for forming a second device, wherein the first device cell region and the second device cell region are isolated by the isolation region. In the step of forming the gate structure, the number of gate structures formed in the first device unit region is multiple, and the number of gate structures formed in the second device unit region is one.

16. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of forming the gate structure, the gate structure is a pseudo-gate structure; After forming the source and drain doped layers, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on a substrate on the side of the gate structure to expose the top of the gate structure; removing the gate structure to form a gate opening in the interlayer dielectric layer; and forming a device gate structure in the gate opening.

Images