Motor drive circuit and motor module

Abstract

This invention provides a motor drive circuit and a motor module capable of reducing capacitor ripple current. The motor drive circuit (100) has three output terminals (102), a first input terminal (P), a second input terminal (N), a capacitor (C), and three series conductors (112). During at least a portion of the three-phase output current when the output current of two phases is positive and the output current of one phase is negative, each predetermined PWM cycle includes a period during which a first semiconductor switching element corresponding to one of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other corresponding first semiconductor switching element is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform.

Description

Technical Field

[0001] This invention relates to motor drive circuits and motor modules. This application claims priority based on Japanese Patent Application No. 2020-157374, filed on September 18, 2020, the contents of which are incorporated herein by reference. Background Technology

[0002] Previously, motor drive circuits for driving three-phase motors were known (e.g., Patent Document 1). In the motor drive circuit described in Patent Document 1, the erroneous detection of the power relay circuit's connection failure due to the influence of charge accumulated in the capacitor was suppressed.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-160972 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] However, in the motor drive circuit described in Patent Document 1, high-frequency current, also known as ripple current, is generated in the capacitors of the motor drive circuit as the inverter switches, causing the capacitors to heat up. Therefore, a large-capacity capacitor is required, which is the reason for the large size and high cost of the motor drive circuit.

[0008] The present invention was made in view of the above-mentioned problems, and its purpose is to provide a motor drive circuit and a motor module that can reduce the ripple current of the capacitor in the motor drive circuit, thereby achieving miniaturization and cost reduction of the capacitor.

[0009] Methods for solving problems

[0010] The present invention provides an exemplary motor drive circuit for controlling the drive of a three-phase motor. The motor drive circuit has three output terminals, a first input terminal, a second input terminal, a capacitor, and three series-connected elements. The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. A first voltage is applied to the first input terminal. A second voltage lower than the first voltage is applied to the second input terminal. The capacitor is connected between the first and second input terminals. The three series-connected elements are formed by two semiconductor switching elements connected in series. The three series-connected elements are connected in parallel. One end of each of the three series-connected elements is connected to the first input terminal, and the other end is connected to the second input terminal. Each of the three series-connected elements has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first input terminal. The second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected elements is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a predetermined PWM cycle. In at least a portion of the three-phase output current, where two phases have positive output current and one phase has negative output current, each defined PWM cycle includes a period during which one of the first semiconductor switching elements corresponding to one of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform.

[0011] The present invention provides an exemplary motor drive circuit for controlling the drive of a three-phase motor. The motor drive circuit has three output terminals, a first input terminal, a second input terminal, a capacitor, and three series-connected elements. The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. A first voltage is applied to the first input terminal. A second voltage lower than the first voltage is applied to the second input terminal. The capacitor is connected between the first and second input terminals. The three series-connected elements are formed by two semiconductor switching elements connected in series. The three series-connected elements are connected in parallel. One end of each of the three series-connected elements is connected to the first input terminal, and the other end is connected to the second input terminal. Each of the three series-connected elements has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first input terminal. The second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected elements is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a predetermined PWM cycle. In at least a portion of the three-phase output current, where the output current of two phases is negative and the output current of one phase is positive, each defined PWM cycle includes a period during which the second semiconductor switching element corresponding to one of the phases with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and a period during which the other phase with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform.

[0012] The present invention provides an exemplary motor drive circuit for controlling the drive of a three-phase motor. The motor drive circuit has three output terminals, a first input terminal, a second input terminal, a capacitor, and three series-connected elements. The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. A first voltage is applied to the first input terminal. A second voltage lower than the first voltage is applied to the second input terminal. The capacitor is connected between the first and second input terminals. The three series-connected elements are formed by two semiconductor switching elements connected in series. The three series-connected elements are connected in parallel. One end of each of the three series-connected elements is connected to the first input terminal, and the other end is connected to the second input terminal. Each of the three series-connected elements has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first input terminal. The second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected elements is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a predetermined PWM cycle. In at least a portion of the three-phase output current, where two phases have positive output current and one phase has negative output current, each defined PWM cycle includes a period during which one of the first semiconductor switching elements corresponding to one of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform. In at least a portion of the three-phase output current, where the output current of two phases is negative and the output current of one phase is positive, each defined PWM cycle includes a period during which the second semiconductor switching element corresponding to one of the phases with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and a period during which the other phase with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform.

[0013] The present invention provides an exemplary motor drive circuit for controlling the drive of a three-phase motor. The motor drive circuit has three output terminals, a first input terminal, a second input terminal, a capacitor, and three series-connected elements. The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. A first voltage is applied to the first input terminal. A second voltage lower than the first voltage is applied to the second input terminal. The capacitor is connected between the first and second input terminals. The three series-connected elements are formed by two semiconductor switching elements connected in series. The three series-connected elements are connected in parallel. One end of each of the three series-connected elements is connected to the first input terminal, and the other end is connected to the second input terminal. Each of the three series-connected elements has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first input terminal. The second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected elements is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a predetermined PWM cycle. In at least a portion of the three-phase output currents where two phases have positive output currents and one phase has negative output currents, each predetermined PWM cycle includes a negative-off-positive-on period where the second semiconductor switching element corresponding to the negative output current is off, and during this negative-off-positive-on period, the first semiconductor switching element corresponding to the positive output current is on, and the waveform of the three-phase output voltage is a waveform that uniformly decreases in voltage relative to the three-phase sinusoidal voltage waveform. In at least a portion of the three-phase output currents where two phases have negative output currents and one phase has positive output currents, each predetermined PWM cycle includes a positive-off-negative-on period where the first semiconductor switching element corresponding to the positive output current is off, and during this positive-off-negative-on period, the second semiconductor switching element corresponding to the negative output current is on, and the waveform of the three-phase output voltage is a waveform that uniformly increases in voltage relative to the three-phase sinusoidal voltage waveform.

[0014] The exemplary motor module of the present invention has the motor drive circuit described above and a three-phase motor. The three-phase motor is driven by the motor drive circuit.

[0015] Invention Effects

[0016] According to the illustrative invention, the ripple current of the capacitor in the motor drive circuit can be reduced. Attached Figure Description

[0017] Figure 1 This is a block diagram of a motor module according to an embodiment of the present invention.

[0018] Figure 2 This is a circuit diagram showing the inverter section.

[0019] Figure 3 This is a diagram used to illustrate the generation of the gate signal in the comparator section.

[0020] Figure 4A This is a diagram showing the typical output voltage.

[0021] Figure 4B This is a diagram showing the output current.

[0022] Figure 5 This is a timing diagram showing the gate signals in a typical center-aligned configuration.

[0023] Figure 6A This is a diagram used to illustrate the ripple current of a capacitor in a typical center-aligned configuration.

[0024] Figure 6B This is a diagram used to illustrate the ripple current of a capacitor in a typical center-aligned configuration.

[0025] Figure 7A This is a diagram used to illustrate the ripple current of a capacitor in a typical center-aligned configuration.

[0026] Figure 7B This is a diagram used to illustrate the ripple current of a capacitor in a typical center-aligned configuration.

[0027] Figure 8A This is a timing diagram showing the gate signal.

[0028] Figure 8B This is a timing diagram showing the gate signal.

[0029] Figure 9A This is a diagram used to illustrate the ripple current of a capacitor.

[0030] Figure 9B This is a diagram used to illustrate the ripple current of a capacitor.

[0031] Figure 10A This is a diagram used to illustrate the ripple current of a capacitor.

[0032] Figure 10B This is a diagram used to illustrate the ripple current of a capacitor.

[0033] Figure 11A This is a timing diagram showing the gate signal.

[0034] Figure 11B This is a timing diagram showing the gate signal.

[0035] Figure 12A This is a diagram used to illustrate the ripple current of a capacitor.

[0036] Figure 12B This is a diagram used to illustrate the ripple current of a capacitor.

[0037] Figure 13A This is a diagram used to illustrate the ripple current of a capacitor.

[0038] Figure 13B This is a diagram used to illustrate the ripple current of a capacitor.

[0039] Figure 14 This is a diagram showing the output voltage.

[0040] Figure 15A This is a timing diagram showing the gate signal.

[0041] Figure 15B This is a timing diagram showing the gate signal.

[0042] Figure 16A This is a timing diagram showing the gate signal.

[0043] Figure 16B This is a timing diagram showing the gate signal.

[0044] Figure 17A This is a diagram showing the waveform of a sinusoidal voltage wave.

[0045] Figure 17B It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform.

[0046] Figure 17C This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic.

[0047] Figure 18A This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic.

[0048] Figure 18B This is a diagram showing the output current.

[0049] Figure 19A It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform.

[0050] Figure 19B This is a diagram showing the output current.

[0051] Figure 19C This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic.

[0052] Figure 19D This is a diagram showing the output current.

[0053] Figure 20A It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform.

[0054] Figure 20B This is a diagram showing the output current.

[0055] Figure 20C This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic.

[0056] Figure 20D This is a diagram showing the output current. Detailed Implementation

[0057] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the drawings, the same or equivalent parts are labeled with the same reference numerals and will not be described repeatedly.

[0058] Reference Figure 1 and Figure 2 The motor according to an embodiment of the present invention will be described. Figure 1 This is a block diagram of the motor module 200 according to an embodiment of the present invention. Figure 2 This is a circuit diagram showing the inverter section 110.

[0059] like Figure 1 As shown, the motor module 200 includes a motor drive circuit 100 and a three-phase motor M. The three-phase motor M is driven by the motor drive circuit 100. The three-phase motor M is, for example, a brushless DC motor. The three-phase motor M has a U phase, a V phase, and a W phase.

[0060] The motor drive circuit 100 controls the drive of the three-phase motor M. The motor drive circuit 100 includes an inverter section 110 and an inverter control section 120.

[0061] The motor drive circuit 100 has three output terminals 102. The three output terminals 102 include output terminal 102u, output terminal 102v, and output terminal 102w. The three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. Specifically, output terminal 102u outputs the U-phase output voltage Vu and U-phase output current Iu to the three-phase motor M. Output terminal 102v outputs the V-phase output voltage Vv and V-phase output current Iv to the three-phase motor M. Output terminal 102w outputs the W-phase output voltage Vw and W-phase output current Iw to the three-phase motor M. Furthermore, the flow of output currents Iu, Iv, and Iw from the motor drive circuit 100 to the three-phase motor M is sometimes described as positive current, and the flow of output currents Iu, Iv, and Iw from the three-phase motor M to the motor drive circuit 100 is sometimes described as negative current.

[0062] like Figure 2 As shown, the motor drive circuit 100 has a first input terminal P, a second input terminal N, a capacitor C, and three series-connected terminals 112. More specifically, in this embodiment, the motor drive circuit 100 has an inverter section 110, which has a first input terminal P, a second input terminal N, a capacitor C, and three series-connected terminals 112. The inverter section 110 also has a DC voltage source B. Alternatively, the DC voltage source B may be located outside the inverter section 110.

[0063] A first voltage V1 is applied to the first input terminal P. The first input terminal P is connected to a DC voltage source B.

[0064] A second voltage V2 is applied to the second input terminal N. The second input terminal N is connected to a DC voltage source B. The second voltage V2 is lower than the first voltage V1.

[0065] Capacitor C is connected between the first input terminal P and the second input terminal N.

[0066] The three series-connected elements 112 are formed by connecting two semiconductor switching elements in series. The semiconductor switching elements are, for example, IGBTs (Insulated Gate Bipolar Transistors). Alternatively, the semiconductor switching elements can be other transistors such as field-effect transistors. The three series-connected elements 112 include series elements 112u, 112v, and 112w. The three series elements 112 are connected in parallel. One end of each of the three series elements 112 is connected to the first input terminal P. The other end of each of the three series elements 112 is connected to the second input terminal N. A rectifier element D is connected in parallel to these semiconductor switching elements, with the first input terminal P side (upper side of the paper) as the cathode and the second input terminal N side (lower side of the paper) as the anode. When using a field-effect transistor as the semiconductor switching element, a parasitic diode can also be used as the rectifier element.

[0067] The three series-connected elements 112 each have a first semiconductor switching element and a second semiconductor switching element. Specifically, series-connected element 112u has a first semiconductor switching element Up and a second semiconductor switching element Un. Series-connected element 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. Series-connected element 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.

[0068] The first semiconductor switching elements Up, Vp, and Wp are connected to the first input terminal P. In other words, the first semiconductor switching elements Up, Vp, and Wp are semiconductor switching elements on the high-voltage side.

[0069] The second semiconductor switching elements Un, Vn, and Wn are connected to the second input terminal N. In other words, the second semiconductor switching elements Un, Vn, and Wn are semiconductor switching elements on the low-voltage side.

[0070] The first semiconductor switching element and the second semiconductor switching element are connected at connection point 114. Specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at connection point 114w.

[0071] Each of the three series-connected bodies 112 has a connection point 114 connected to one of the three output terminals 102. Specifically, connection point 114u of series-connected body 112u is connected to output terminal 102u. Connection point 114v of series-connected body 112v is connected to output terminal 102v. Connection point 114w of series-connected body 112w is connected to output terminal 102w.

[0072] The first semiconductor switching elements Up, Vp, and Wp are input with gate signals. These gate signals are output from the inverter control unit 120. Hereinafter, in this specification, the gate signal input to the first semiconductor switching element Up will sometimes be referred to as the "Up gate signal." Additionally, the gate signal input to the first semiconductor switching element Vp will sometimes be referred to as the "Vp gate signal." The gate signal input to the first semiconductor switching element Wp will sometimes be referred to as the "Wp gate signal." The first semiconductor switching elements Up, Vp, and Wp are switched on and off at a predetermined PWM cycle. For example, the first semiconductor switching elements Up, Vp, and Wp are turned on when the Up gate signal, Vp gate signal, and Wp gate signal are all high. Conversely, the first semiconductor switching elements Up, Vp, and Wp are turned off when the Up gate signal, Vp gate signal, and Wp gate signal are all low.

[0073] The second semiconductor switching elements Un, Vn, and Wn are input with gate signals. These gate signals are output from the inverter control unit 120. Hereinafter, in this specification, the gate signal input to the second semiconductor switching element Un will sometimes be referred to as "Un gate signal." Additionally, the gate signal input to the second semiconductor switching element Vn will sometimes be referred to as "Vn gate signal." The gate signal input to the second semiconductor switching element Wn will sometimes be referred to as "Wn gate signal." The second semiconductor switching elements Un, Vn, and Wn are switched on and off according to a predetermined PWM cycle. For example, the second semiconductor switching elements Un, Vn, and Wn are turned on when the Un gate signal, Vn gate signal, and Wn gate signal are all high. Conversely, the second semiconductor switching elements Un, Vn, and Wn are turned off when the Un gate signal, Vn gate signal, and Wn gate signal are all low.

[0074] like Figure 1 As shown, the inverter control unit 120 includes a carrier generation unit 122, a voltage command value generation unit 124, a comparison unit 126, and a pulse changing unit 128. The inverter control unit 120 is a hardware circuit composed of a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit). Furthermore, the processor of the inverter control unit 120 functions as the carrier generation unit 122, the voltage command value generation unit 124, the comparison unit 126, and the pulse changing unit 128 by executing a computer program stored in a storage device.

[0075] The inverter control unit 120 controls the inverter unit 110. Specifically, the inverter control unit 120 controls the inverter unit 110 by generating a gate signal and outputting a gate signal.

[0076] The carrier generation unit 122 generates a carrier signal. The carrier signal is, for example, a triangular wave. Alternatively, the carrier signal can also be a sawtooth wave.

[0077] The voltage command value generation unit 124 generates a voltage command value. The voltage command value is equivalent to the voltage value output from the motor drive circuit 100. That is, the voltage command value generation unit 124 generates voltage values ​​corresponding to the output voltages Vu, Vv, and Vw as voltage command values.

[0078] The comparator 126 generates a gate signal by comparing a carrier signal and a voltage command value. For details on the generation of the gate signal by the comparator 126, please refer to... Figure 3 The explanation will follow.

[0079] The pulse changing unit 128 changes the timing of the gate signal output from the comparator unit 126. The gate signal, whose timing has been changed by the pulse changing unit 128, is input to the inverter unit 110. For details regarding the timing change of the gate signal by the pulse changing unit 128, please refer to... Figures 8A to 13B This will be explained later. Additionally, in Figure 1 In the example, after the comparator 126 generates the gate signal, the pulse changing unit 128 performs timing changes on the gate signal output from the comparator 126. However, it is not limited to this. For example, the voltage command value can be changed synchronously with the carrier of the carrier generation unit 122 by the voltage command value generation unit 124, and the timing-changed gate signal can be directly output from the comparator 126 to control the inverter unit 110. In addition, the carrier waveform generated by the carrier generation unit 122 can be shared by all three phases, or it can use other carriers with different phases for each phase.

[0080] Reference Figures 1-3 The generation of the gate signal of the comparator 126 will be explained. Figure 3 This is a diagram used to illustrate the generation of the gate signal in the comparator 126. Figure 3 The diagram illustrates the generation of the gate signal for the comparator 126 when the U-phase voltage command value is the largest, the V-phase voltage command value is the second largest, and the W-phase voltage command value is the third largest. Figure 3 The diagram only shows the gate signals of the first semiconductor switching elements Up, Vp, and Wp, while the gate signals of the second semiconductor switching elements Un, Vn, and Wn are omitted.

[0081] like Figure 3 As shown, the carrier signal is a triangular wave. For example, the period of the carrier signal is equal to the PWM period. The PWM period is, for example, 50 μs.

[0082] The comparator 126 generates a gate signal by comparing the voltage command value and the carrier signal. Specifically, the comparator 126 compares the U-phase voltage command value and the carrier signal; if the carrier signal is above the U-phase voltage command value, it disconnects the Up gate signal. Conversely, the comparator 126 compares the U-phase voltage command value and the carrier signal; if the carrier signal is below the U-phase voltage command value, it connects the Up gate signal.

[0083] Similarly, the comparator 126 compares the V-phase voltage command value with the carrier signal, and turns off the Vp gate signal if the carrier signal is above the V-phase voltage command value. On the other hand, the comparator 126 compares the V-phase voltage command value with the carrier signal, and turns on the Vp gate signal if the carrier signal is below the V-phase voltage command value.

[0084] Similarly, the comparator 126 compares the W-phase voltage command value with the carrier signal, and turns off the Wp gate signal if the carrier signal is above the W-phase voltage command value. On the other hand, the comparator 126 compares the W-phase voltage command value with the carrier signal, and turns on the Wp gate signal if the carrier signal is below the W-phase voltage command value.

[0085] In addition, although Figure 3 The details are omitted, but the Un gate signal, which serves as the gate signal of the second semiconductor switching element Un, is obtained by inverting the Up gate signal. Similarly, the Vn gate signal, which serves as the gate signal of the second semiconductor switching element Vn, is obtained by inverting the Vp gate signal. Likewise, the Wn gate signal, which serves as the gate signal of the second semiconductor switching element Wn, is obtained by inverting the Wp gate signal. Between the on-time of the Up gate signal and the on-time of the Un gate signal, the dead time period during which the two gate signals are in the off state is sometimes set to approximately several hundred n seconds to several μ seconds. By setting this dead time period, it is possible to prevent the simultaneous on-state of the first semiconductor switching element Up and the second semiconductor switching element Un, thus preventing the generation of through-current. For the same reason, the dead time between the turn-on period of the Vp gate signal and the turn-on period of the Vn gate signal is sometimes set to a few hundred n seconds to a few μ seconds, and the dead time between the turn-on period of the Wp gate signal and the turn-on period of the Wn gate signal is sometimes set to a few hundred n seconds to a few μ seconds.

[0086] Reference Figure 4A and Figure 4B The output voltage and output current are explained. Figure 4A This is a diagram showing the typical output voltages Vu, Vv, and Vw. Figure 4B This is a graph showing the output currents Iu, Iv, and Iw. Figure 4A In the diagram, solid lines represent output voltage Vu, dashed lines represent output voltage Vv, and dotted lines represent output voltage Vw. Figure 4B In the diagram, solid lines represent output current Iu, dashed lines represent output current Iv, and dotted lines represent output current Iw. Figure 4AThe vertical axis represents the voltage value normalized using the input voltages V1-V2, with the output voltage of each phase ranging from 0 to 1. Additionally, this value also represents the duty cycle, which is the ratio of the on-time of the first semiconductor switching element in each phase to the PWM period. Figure 4A and Figure 4B The horizontal axis represents the electric rotation angle of the motor, in degrees.

[0087] like Figure 4A As shown, the typical output voltages Vu, Vv, and Vw are sinusoidal. The phase of output voltage Vv is offset by 120 degrees relative to output voltage Vu. The phase of output voltage Vw is offset by 120 degrees relative to output voltage Vv. The phase of output voltage Vu is offset by 120 degrees relative to output voltage Vw.

[0088] like Figure 4B As shown, the output currents Iu, Iv, and Iw exhibit sinusoidal waveforms. The phase of the output current Iv is shifted by 120 degrees relative to the output current Iu. The phase of the output current Iw is shifted by 120 degrees relative to the output current Iv. The phase of the output current Iu is shifted by 120 degrees relative to the output current Iw. Furthermore, in... Figure 4B In the example shown, the phases of the output currents Iu, Iv, and Iw are offset by 30 degrees relative to the output voltages Vu, Vv, and Vw.

[0089] Reference Figures 5-7B The ripple current of capacitor C in the case of a gate signal in a typical center-aligned configuration is explained. Figure 5 This is a timing diagram showing the gate signals in a typical center-aligned configuration (dead time is omitted from the diagram). Figures 6A to 7B This diagram illustrates the ripple current of capacitor C in a typical center-aligned configuration. The rectifier element D, connected in parallel with the semiconductor switching elements, is omitted from the diagram. Figures 6A to 7B In the diagram, the input current Iin is the input current from the DC voltage source B. The capacitor current Ic is the current flowing in the capacitor C. Figures 5 to 7B Corresponding to Figure 4A and Figure 4B The period P1 is shown. Period P1 represents the period during which the output currents of two phases (output current Iv and output current Iw) of the three-phase output currents (output current Iu, output current Iv and output current Iw) are negative and the output current of one phase (output current Iu) is positive.

[0090] like Figure 5 As shown, in the typical center alignment method, the gate signal becomes a waveform that is symmetrical about the center of the PWM cycle.

[0091] like Figure 5 As shown, during periods t1 and t7, the Up, Vp, and Wp gate signals are at a low level. Conversely, the Un, Vn, and Wn gate signals are at a high level. Therefore, during periods t1 and t7, as... Figure 6A As shown, the first semiconductor switching elements Up, Vp, and Wp are off. On the other hand, the second semiconductor switching elements Un, Vn, and Wn are on. Therefore, none of the first semiconductor switching elements on the high-potential side receive current. As a result, the entire input current Iin flows into capacitor C. That is, Ic = Iin.

[0092] like Figure 5 As shown, during periods t2 and t6, the Up gate signal becomes high, and the Vp and Wp gate signals become low. Additionally, the Un gate signal becomes low, and the Vn and Wn gate signals become high. Therefore, during periods t2 and t6, as... Figure 6B As shown, the first semiconductor switching element Up is turned on, while the first semiconductor switching elements Vp and Wp are turned off. On the other hand, the second semiconductor switching element Un is turned off, while the second semiconductor switching elements Vn and Wn are turned on. Therefore, current flows only through the first semiconductor switching element Up, which is on the high-potential side. Furthermore, current flows through the second semiconductor switching elements Vn and Wn, which are on the low-potential side. Therefore, the current flowing downstream of capacitor C is only phase U. As a result, Ic = Iin - |Iu|.

[0093] like Figure 5 As shown, during periods t3 and t5, the Up and Vp gate signals are high, and the Wp gate signal is low. Additionally, the Un and Vn gate signals are low, and the Wn gate signal is high. Therefore, during periods t3 and t5, as... Figure 7A As shown, the first semiconductor switching elements Up and Vp are turned on, while the first semiconductor switching element Wp is turned off. On the other hand, the second semiconductor switching elements Un and Vn are turned off, while the second semiconductor switching element Wn is turned on. Therefore, current flows through the first semiconductor switching elements Up and Vp, which are on the high-potential side. Furthermore, current flows only through the second semiconductor switching element Wn, which is on the low-potential side. Therefore, Ic = Iin - |Iw|.

[0094] like Figure 5As shown, during period t4, the Up, Vp, and Wp gate signals are at a high level. Conversely, the Un, Vn, and Wn gate signals are at a low level. Therefore, during period t4, as... Figure 7B As shown, the first semiconductor switching elements Up, Vp, and Wp are turned on. On the other hand, the second semiconductor switching elements Un, Vn, and Wn are turned off. Therefore, the current in phases U, V, and W flows back. Consequently, the first semiconductor switching elements on the high-potential side do not accept current. As a result, the entire input current Iin flows into capacitor C. That is, Ic = Iin.

[0095] The above is for reference only. Figures 5-7B As explained, in the normal center alignment mode, all the input current Iin flows into capacitor C between periods t1 and t7 and t4, thus increasing the ripple current of the capacitor. Therefore, it is preferable to shorten the time between periods t1 and t7 and t4. In other words, it is preferable to shorten the period during which the first semiconductor switching elements Up, Vp, and Wp are all turned on. Furthermore, it is preferable to shorten the period during which the first semiconductor switching elements Up, Vp, and Wp are all turned off. Therefore, the motor drive circuit 100 of this embodiment changes the timing of the gate signal output from the comparator 126 in the pulse changing unit 128.

[0096] Reference Figure 4A and Figure 4B as well as Figures 8A to 10B The timing of the gate signal change in the pulse changing unit 128 will be explained. Figure 8A and Figure 8B This is a timing diagram showing the gate signal. Figure 8A The gate signal output by the comparator 126 is shown. That is, the gate signal before the timing is changed by the pulse changing unit 128 is shown. Figure 8B The gate signal after the timing has been changed by the pulse changing unit 128 is shown. Figures 9A to 10B This is a diagram used to illustrate the ripple current of capacitor C.

[0097] Figure 8A and Figure 8B It shows Figure 4A and Figure 4B The gate signal in period P1 is shown. Period P1 represents the period during which the output currents of two phases (output current Iv and output current Iw) are negative and the output current of one phase (output current Iu) is positive.

[0098] like Figure 8A As shown, the gate signal output by the comparator 126 is output in a center-aligned manner.

[0099] like Figure 8B As shown, the pulse changing unit 128 changes the timing of the gate signal.

[0100] like Figure 8B As shown, during periods t11 and t15, the Un and Vn gate signals are low, and the Wn gate signal is high. Therefore, during periods t11 and t15, as... Figure 9A As shown, the second semiconductor switching element Wn corresponding to one of the phases (W phase) with a negative output current (V phase, W phase) is turned on, while the second semiconductor switching elements (un and Vn) corresponding to the other two phases (U phase, V phase) are turned off. Periods t11 and t15 correspond to an example of "negative side 1 on 2 off period". In period t11, Ic = Iin - |Iw|.

[0101] like Figure 8B As shown, during period t12, the Un gate signal, Vn gate signal, and Wn gate signal are at a high level. Therefore, during period t12, as... Figure 9B As shown, the first semiconductor switching element Up, corresponding to the phase with positive output current (U phase), is disconnected, while the second semiconductor switching elements Vn and Wn, corresponding to the phases with negative output current (V phase, W phase), are turned on. Period t12 corresponds to an example of a "positive disconnection, negative turn-on period". Figure 8B During the period t12, Ic = Iin, and the entire input current Iin flows into capacitor C. Furthermore, during period t12, as described above, since the first semiconductor switching element Up corresponding to the phase with positive output current (U phase) is off, no current flows through the first semiconductor switching element Up. At this time, if at least one of the first semiconductor switching elements Vp and Wp corresponding to the phases with negative output current (V phase, W phase) is turned on, a current flows from below the plane of the paper upwards through the turned-on element. Since the first semiconductor switching element Up is off, this current flows into capacitor C, increasing the charging current of capacitor C. However, as described above, during period t12, the second semiconductor switching elements Vn and Wn are turned on, and no current flows through the first semiconductor switching elements Vp and Wp, thus suppressing the charging current of capacitor C.

[0102] like Figure 8B As shown, during period t13, the Un gate signal and the Wn gate signal are at a low level, and the Vn gate signal is at a high level. Therefore, during period t13, as... Figure 10AAs shown, the second semiconductor switching element Vn corresponding to another phase (V phase) of the phase with negative output current (V phase, W phase) is turned on, while the second semiconductor switching elements (second semiconductor switching element Un and second semiconductor switching element Wn) corresponding to the other two phases (U phase, W phase) are turned off. Period t13 is equivalent to an example of "the period when the negative side 1 is turned on and 2 is turned off". During period t13, Ic = Iin - |Iv|.

[0103] like Figure 8B As shown, during period t14, the Un gate signal is low, while the Vn and Wn gate signals are high. Therefore, during period t14, as... Figure 10B As shown, the first semiconductor switching element Up is turned on, and the second semiconductor switching element Vn and the second semiconductor switching element Wn are also turned on. During period t14, Ic = Iin - |Iu|.

[0104] The above is for reference only. Figure 4A and Figure 4B as well as Figures 8A to 10B As explained, during at least a portion of the three-phase output current, where the output currents (output current Iv and output current Iw) of two phases (V phase and W phase) are negative and the output current (output current Iu) of one phase (U phase) is positive, each defined PWM cycle includes a period of 1-on and 2-off for the negative side (periods t11 and t15) and a period of 1-on and 2-off for the other negative side (period t13). During the 1-on and 2-off period for the negative side (periods t11 and t15), the second semiconductor switching element Wn corresponding to one of the phases (V phase and W phase) with negative output current is turned on, and the second semiconductor switching elements (second semiconductor switching element Un and second semiconductor switching element Vn) corresponding to the other two phases (U phase and V phase) are turned off. During the period when the other side 1 is turned on and 2 is turned off (period t13), the second semiconductor switching element Vn corresponding to the other phase (V phase, W phase) of the phase with negative output current is turned on, and the second semiconductor switching elements (second semiconductor switching element Un and second semiconductor switching element Wn) corresponding to the other two phases (U phase, W phase) are turned off.

[0105] Reference Figure 4A and Figure 4B as well as Figures 11A to 13B The timing of the gate signal change in the pulse changing unit 128 will be explained. Figure 11A and Figure 11B This is a timing diagram showing the gate signal. Figure 11A The gate signal output by the comparator 126 is shown. That is, the gate signal before the timing is changed by the pulse changing unit 128 is shown. Figure 11BThe gate signal is shown after the timing has been changed by the pulse changing unit 128. Figures 12A to 13B This is a diagram used to illustrate the ripple current of capacitor C.

[0106] Figure 11A and Figure 11B It shows Figure 4A and Figure 4B The gate signal in period P2 is shown. Period P2 represents the period during which the output currents of two phases (output current Iu and output current Iv) are positive and the output current of one phase (output current Iw) is negative.

[0107] like Figure 11A As shown, the gate signal output by the comparator 126 is output in a center-aligned manner.

[0108] like Figure 11B As shown, the pulse changing unit 128 changes the timing of the gate signal.

[0109] like Figure 11B As shown, during periods t21 and t25, the Up gate signal and Wp gate signal are at a low level, and the Vp gate signal is at a high level. Therefore, during periods t21 and t25, as... Figure 12A As shown, the first semiconductor switching element Vp corresponding to one of the phases (U phase, V phase) with a positive output current (V phase) is turned on, while the first semiconductor switching elements (first semiconductor switching element Up and first semiconductor switching element Wp) corresponding to the other two phases (U phase, W phase) are turned off. Periods t21 and t25 correspond to an example of "one phase 1 is on and one phase is off". In period t21, Ic = Iin - |Iv|.

[0110] like Figure 11B As shown, during period t22, the Up gate signal, Vp gate signal, and Wp gate signal are at a high level. Therefore, during period t22, as... Figure 12B As shown, the second semiconductor switching element Wn corresponding to the phase with negative output current (W phase) is disconnected, while the first semiconductor switching elements Up and Vp corresponding to the phases with positive output current (U phase, V phase) are turned on. Period t22 corresponds to an example of a "negative disconnection and positive turn-on period". Figure 11BDuring period t22, Ic = Iin, and the entire input current Iin flows into capacitor C. Furthermore, during period t22, as described above, since the second semiconductor switching element Wn corresponding to the phase with negative output current (phase W) is off, no current flows through the second semiconductor switching element Wn. At this time, if at least one of the second semiconductor switching elements Vn and Wn corresponding to the phases with positive output current (phase U, phase V) is turned on, current flows from the top to the bottom of the paper in the turned-on element. Since the second semiconductor switching element Wn is off, this current flows into capacitor C, increasing the charging current of capacitor C. However, as described above, during period t22, the first semiconductor switching elements Up and Vp are turned on, and no current flows through the second semiconductor switching elements Vn and Wn, thus suppressing the charging current of capacitor C.

[0111] like Figure 11B As shown, during period t23, the Vp gate signal and Wp gate signal are at a low level, and the Up gate signal is at a high level. Therefore, during period t23, as... Figure 13A As shown, the first semiconductor switching element Up, corresponding to another phase (U phase) among the phases (U phase and V phase) with positive output current, is turned on, while the first semiconductor switching elements (V phase and W phase) corresponding to the other two phases (V phase and W phase) are turned off. Period t23 corresponds to an example of "the period when one phase is turned on and the other phase is turned off". During period t23, Ic = Iin - |Iu|.

[0112] like Figure 11B As shown, during period t24, the Wp gate signal is low, while the Up and Vp gate signals are high. Therefore, during period t24, as... Figure 13B As shown, the second semiconductor switching element Wn is turned on, and the first semiconductor switching elements Up and Vp are turned on. During period t24, Ic = Iin - |Iw|.

[0113] The above is for reference only. Figure 4A and Figure 4B as well as Figures 11A to 13BAs explained, during at least a portion of the three-phase output current, where the output currents (output current Iu and output current Iv) of two phases (U phase and V phase) are positive and the output current (output current Iw) of one phase (W phase) is negative, each defined PWM cycle includes a positive one-to-one on / off period (periods t21 and t25) and a positive other one-to-one on / off period (period t23). During the positive one-to-one on / off period (periods t21 and t25), the first semiconductor switching element Vp corresponding to one of the phases (U phase and V phase) with positive output current (V phase) is turned on, and the first semiconductor switching elements (first semiconductor switching element Up and first semiconductor switching element Wp) corresponding to the other two phases (U phase and W phase) are turned off. During the period when the other side is 1 on and 2 off (period t23), the first semiconductor switching element Vp corresponding to the other phase (U phase, V phase) of the phase with positive output current is turned on, and the first semiconductor switching elements (first semiconductor switching element Vp and first semiconductor switching element Wp) corresponding to the other two phases (V phase, W phase) are turned off.

[0114] Reference Figure 14 The output voltage will be further explained. Figure 14 This is a diagram showing the output voltage.

[0115] like Figure 14 As shown, in this embodiment, during at least a portion of the period when two phases of the three-phase output current are positive and one phase is negative, the waveform of the three-phase output voltage is a waveform that uniformly reduces the voltage relative to the three-phase sinusoidal voltage waveform. Even if the voltage of the three-phase sinusoidal voltage waveform is uniformly increased, the voltage between phases does not change. Therefore, it has no impact on motor control. Alternatively, it is also possible not to reduce the voltage of the three-phase sinusoidal voltage waveform by the exact same value.

[0116] On the other hand, when two phases of the three-phase output current are negative and one phase is positive, for at least a portion of the period, the waveform of the three-phase output voltage becomes a waveform that uniformly increases the voltage relative to the three-phase sinusoidal voltage waveform. Even with a uniform increase in the voltage of the three-phase sinusoidal voltage waveform, the voltage between phases does not change. Therefore, it has no impact on motor control. Alternatively, it is also possible not to increase the voltage of the three-phase sinusoidal voltage waveform by the exact same value.

[0117] For example, the waveforms of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) can be obtained by superimposing one or more higher harmonics onto the three-phase sinusoidal voltage waveforms. Alternatively, the waveforms can be obtained by superimposing third harmonics with different amplitude values ​​onto the three-phase sinusoidal voltage waveforms. Therefore, it is possible to make the three-phase output voltage waveforms identical in shape with only a 120° phase shift, allowing for smooth changes. This, in turn, suppresses torque unevenness.

[0118] Furthermore, the waveform of the output voltage of each phase preferably includes waveforms of the 3Nth order (N being an integer greater than or equal to 2). Therefore, the waveforms of the three-phase output voltages can be made to have the same shape with only their phases shifted by 120°, allowing for smooth changes. This helps suppress torque unevenness.

[0119] Furthermore, N is preferably an odd number. When N is an odd number, the symmetry of the three-phase output voltage waveform can be improved. Therefore, torque unevenness can be suppressed.

[0120] Reference Figure 15A and Figure 15B The effect is explained when, during at least a portion of the three-phase output current, two phases have negative output current and one phase has positive output current, the waveform of the three-phase output voltage is uniformly increased relative to the three-phase sinusoidal voltage waveform. Figure 15A and Figure 15B This is a timing diagram showing the gate signal.

[0121] like Figure 15A and Figure 15B As shown, by uniformly increasing the voltage of the three-phase sinusoidal voltage waveform, the high-level intervals of the Un, Vn, and Wn gate signals are shortened. Therefore, the period t12 is shortened. Consequently, the period during which all of the second semiconductor switching elements (second semiconductor switching elements Un, Vn, and Wn) on the low-potential side are turned on can be shortened. As a result, the period during which the entire input current Iin flows into the capacitor C can be shortened. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0122] Furthermore, the period t14 is shortened. Therefore, the period during which two of the second semiconductor switching elements (second semiconductor switching element Un, second semiconductor switching element Vn, and second semiconductor switching element Wn) on the low-potential side are turned on can be shortened. As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0123] Reference Figure 16A and Figure 16B The effect is explained when, during at least a portion of the three-phase output current, two phases have positive output current and one phase has negative output current, the waveform of the three-phase output voltage is uniformly reduced relative to the three-phase sinusoidal voltage waveform. Figure 16A and Figure 16B This is a timing diagram showing the gate signal.

[0124] like Figure 16A and Figure 16B As shown, by uniformly reducing the voltage of the three-phase sinusoidal voltage waveform, the high-level intervals of the Up gate signal, Vp gate signal, and Wp gate signal are shortened. Therefore, the period t22 is shortened. Consequently, the period during which all of the first semiconductor switching elements (first semiconductor switching element Up, first semiconductor switching element Vp, and first semiconductor switching element Wp) on the high-potential side can be shortened. As a result, the period during which the entire input current Iin flows into the capacitor C can be shortened. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0125] Furthermore, the period t24 is shortened. Therefore, the period during which two of the first semiconductor switching elements (first semiconductor switching element Up, first semiconductor switching element Vp, and first semiconductor switching element Wp) on the high-potential side are turned on can be shortened. As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0126] Reference Figures 17A-18B The superposition of the inverse third harmonic is explained. Figure 17A This is a diagram showing the waveform of a sinusoidal voltage wave. Figure 17B It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform. Figure 17C and Figure 18A This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic. Figure 18B This is a diagram showing the output current. Figure 17A , Figure 17B , Figure 17C as well as Figure 18A The vertical axis represents the voltage value after normalization using the input voltages V1-V2, with the output voltage of each phase ranging from 0 to 1. Additionally, this value also represents the duty cycle, which is the ratio of the on-time of the first semiconductor switching element in each phase to the PWM period. Figures 17A-18B The horizontal axis represents the electric rotation angle of the motor, in degrees.

[0127] like Figure 17BAs shown, here, the inverse third harmonic, which is in phase with the sine wave, is superimposed. Since the sine waves of each phase are sine waves that are offset by 120 degrees, the inverse third harmonic is shared.

[0128] like Figure 17C As shown, this can increase the amplitude of the output voltage. The result is that it can shorten... Figure 15B The period t12 and shown Figure 16B The period t22 is shown. Therefore, the ripple current of capacitor C can be reduced.

[0129] exist Figure 18A and Figure 18B In the example shown, the phase of the three-phase output currents (output current Iu, output current Iv, and output current Iw) lags behind the phase of the three-phase output voltages (output voltage Vu, output voltage Vv, and output voltage Vw) by 30 degrees.

[0130] In addition, in reference Figures 17A-18B In the illustrated example, the phase of the inverse third harmonic is the same as the phase of the sine wave, but the phase of the inverse third harmonic is preferably the same as the phase of the three-phase output current. Figure 19A It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform. Figure 19B This is a diagram showing the output current. Figure 19C This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic. Figure 19D This is a diagram showing the output current. Figure 19A and Figure 19C The vertical axis represents the voltage value after normalization using the input voltages V1-V2, with the output voltage of each phase ranging from 0 to 1. Additionally, this value also represents the duty cycle, which is the ratio of the on-time of the first semiconductor switching element in each phase to the PWM period. Figures 19A to 19D The horizontal axis represents the electric rotation angle of the motor, in degrees.

[0131] like Figure 19A and Figure 19B As shown, the phase of the inverse third harmonic is the same as the phase of the three-phase output current. Alternatively, the phases can be slightly offset. By making the phase of the inverse third harmonic the same as the phase of the three-phase output current, the waveform of the output voltage after superimposing the sinusoidal voltage waveform with the inverse third harmonic is as follows. Figure 19C As shown.

[0132] By aligning the phase of the inverse third harmonic with the phase of the three-phase output current, when one phase has a negative current and the other two phases have positive currents, the on-time of the first semiconductor switching element on the high-potential side of the negative current phase can be shortened near the point where the current curves of the two positive current phases intersect (the point where the current of the negative current phase reaches its peak). As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0133] Furthermore, by aligning the phase of the inverse third harmonic with the phase of the three-phase output current, when one phase is a positive current and the other two are negative currents, the on-time of the first semiconductor switching element on the high-potential side of the positive current phase can be shortened near the point where the current curves of the two positive current phases intersect (the point where the current of the positive current phase reaches its peak). As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0134] In addition, in reference Figures 19A to 19D In the example given, the phase of the inverse third harmonic is the same as the phase of the three-phase output current, but the phase of the inverse third harmonic can also be different from the phase of the three-phase output current. Figure 20A It is a diagram showing the sinusoidal voltage waveform and the inverse third harmonic waveform. Figure 20B This is a diagram showing the output current. Figure 20C This is a diagram showing the waveform of the output voltage after superimposing a sinusoidal voltage waveform with the inverse third harmonic. Figure 20D This is a diagram showing the output current. Figure 20A and Figure 20C The vertical axis represents the voltage value after normalization using the input voltages V1-V2, with the output voltage of each phase ranging from 0 to 1. Additionally, this value also represents the duty cycle, which is the ratio of the on-time of the first semiconductor switching element in each phase to the PWM period. Figures 20A to 20D The horizontal axis represents the electric rotation angle of the motor, in degrees.

[0135] like Figure 20A and Figure 20B As shown, the phase of the inverse third harmonic relative to the phase of the three-phase output current has a phase difference within a range of 30 degrees electrical angle. Here, the phase of the inverse third harmonic relative to the phase of the three-phase output current has a phase difference within a range of 20 degrees electrical angle. The result is that the waveform of the output voltage after superimposing the sinusoidal voltage waveform and the inverse third harmonic is as follows... Figure 20C As shown.

[0136] By making the phase of the inverse third harmonic relative to the phase of the three-phase output current have a phase difference within a range of 20 degrees electrical angle, it is possible to converge the peak value of the output voltage waveform within a specified range, for example, 5% to 95%, while simultaneously bringing the peak value of the output voltage waveform near the current peak value close to a specified range, for example, 5% to 95%. As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0137] The above is for reference only. Figures 19A to 20D As explained, the phase of the higher harmonics (inverse third harmonic) is preferably adjusted according to the phase of the three-phase output current. As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0138] Furthermore, the phase of the higher harmonics (inverse third harmonic) is preferably adjusted based on the amplitude of the three-phase sinusoidal voltage waveform. As a result, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0139] The above is for reference only. Figures 1 to 20B As explained, during at least a portion of the three-phase output current when two phases have positive output current and one phase has negative output current, each predetermined PWM cycle includes a period during which one of the positive phase's corresponding first semiconductor switching elements is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other phase's corresponding first semiconductor switching element is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage becomes a waveform that uniformly reduces the voltage relative to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0140] Furthermore, at least a portion of the period includes a negative disconnection-positive connection period during which the second semiconductor switching element corresponding to a negative output current is disconnected, and during this period, the first semiconductor switching element corresponding to a positive output current is turned on. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0141] Furthermore, for more than half of the period during which two phases of the three-phase output current are positive and one phase is negative, the waveform of the three-phase output voltage becomes a waveform that is uniformly reduced in voltage compared to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0142] Furthermore, during at least a portion of the three-phase output current when two phases have negative output current and one phase has positive output current, each predetermined PWM cycle includes a period during which the negative side 1 is turned on and 2 is turned off, corresponding to one of the phases with negative output current being negative and the other two corresponding second semiconductor switching elements being off, and a period during which the negative side 1 is turned on and 2 is turned off, corresponding to the other phase with negative output current being negative and the other two corresponding second semiconductor switching elements being off. The waveform of the three-phase output voltage becomes a waveform that uniformly increases the voltage relative to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0143] Furthermore, at least a portion of the period includes a positive-off negative-on period during which the first semiconductor switching element corresponding to a positive output current is turned off, and during this positive-off negative-on period, the second semiconductor switching element corresponding to a negative output current is turned on. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0144] Furthermore, for more than half of the period during which two phases of the three-phase output current are negative and one phase is positive, the waveform of the three-phase output voltage becomes a waveform that consistently increases the voltage relative to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0145] Furthermore, during at least a portion of the period when the output current of two phases in the three-phase output current is positive and the output current of one phase is negative, each predetermined PWM cycle includes a period during which one of the positive semiconductor switching elements corresponding to one of the phases with positive output current is turned on and the other of the positive semiconductor switching elements corresponding to the other phase with positive output current is turned on and the other of the positive semiconductor switching elements corresponding to the other phase with positive output current is turned off and the other of the positive semiconductor switching elements corresponding to the other phase with positive output current is turned on and the other of the positive semiconductor switching elements corresponding to the other phase with positive output current is turned off, and the waveform of the three-phase output voltage becomes a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform. In at least a portion of the three-phase output current, where two phases have negative output current and one phase has positive output current, each predetermined PWM cycle includes a period during which a negative phase 1 is turned on and a negative phase 2 is turned off, corresponding to one of the phases with negative output current being negative and the other two corresponding phases having negative output current being positive and the other two phases having negative output current being negative and the other two phases having negative output current being positive and the other two phases having negative output current being negative and the other two phases having negative output current being negative. Furthermore, the waveform of the three-phase output voltage becomes a waveform that uniformly increases the voltage relative to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0146] Furthermore, during at least a portion of the three-phase output current when two phases have positive output current and one phase has negative output current, a negative disconnect positive connection period is included, during which the second semiconductor switching element corresponding to the negative output current is disconnected. During the negative disconnect positive connection period, the first semiconductor switching element corresponding to the positive output current is turned on. During at least a portion of the three-phase output current when two phases have negative output current and one phase has positive output current, a positive disconnect negative connection period is included, during which the first semiconductor switching element corresponding to the positive output current is disconnected. During the positive disconnect negative connection period, the second semiconductor switching element corresponding to the negative output current is turned on. Therefore, the ripple current of the capacitor C included in the motor drive circuit 100 can be reduced.

[0147] Furthermore, during at least a portion of the three-phase output currents where two phases have positive output currents and one phase has negative output currents, each predetermined PWM cycle includes a negative-off-positive-on period where the second semiconductor switching element corresponding to the negative output current is turned off. During the negative-off-positive-on period, the first semiconductor switching element corresponding to the positive output current is turned on, and the waveform of the three-phase output voltage becomes a waveform that is uniformly reduced relative to the three-phase sinusoidal voltage waveform. During at least a portion of the three-phase output currents where two phases have negative output currents and one phase has positive output currents, each predetermined PWM cycle includes a positive-off-negative-on period where the first semiconductor switching element corresponding to the positive output current is turned off. During the positive-off-negative-on period, the second semiconductor switching element corresponding to the negative output current is turned on, and the waveform of the three-phase output voltage becomes a waveform that is uniformly increased relative to the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C included in the motor drive circuit 100 can be reduced.

[0148] Furthermore, for more than half of the period when two phases of the three-phase output current are positive and one phase is negative, the waveform of the three-phase output voltage becomes a waveform that is consistently lower than the three-phase sinusoidal voltage waveform. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0149] The motor module 200 includes a motor drive circuit 100 and a three-phase motor M driven by the motor drive circuit 100. Therefore, the ripple current of the capacitor C in the motor drive circuit 100 can be reduced.

[0150] The above refers to the attached diagram ( Figures 1 to 20D The embodiments of the present invention have been described. However, the present invention is not limited to the embodiments described above, and can be implemented in various ways without departing from its spirit. For ease of understanding, the accompanying drawings are schematically shown with each constituent element as the main body, and the thickness, length, number, etc. of each constituent element shown in the drawings differ from the actual figures for the convenience of drawing preparation. In addition, the material, shape, size, etc. of each constituent element shown in the above embodiments are examples and are not particularly limited, and various changes can be made without substantially departing from the effect of the present invention.

[0151] Industrial availability

[0152] This invention is applicable to motor drive circuits and motor modules.

[0153] Label Explanation

[0154] 100: Motor drive circuit; 102, 102u, 102v, 102w: Output terminals; 112, 112u, 112v, 112w: Series connection; 114, 114u, 114v, 114w: Connection point; 200: Motor module; C: Capacitor; Iu, Iv, Iw: Output current; P: First input terminal; N: Second input terminal; Up, Vp, Wp: First semiconductor switching element; Un, Vn Wn: Second semiconductor switching element; Vu, Vv, Vw: Output voltage; t11, t15: Period (during the negative side 1 is on and 2 is off); t12: Period (during the positive side is off and the negative side is on); t13: Period (during the negative side 1 is on and 2 is off); t21, t25: Period (during the positive side 1 is on and 2 is off); t22: Period (during the negative side is off and the positive side is on); t23: Period (during the positive side 1 is on and 2 is off).

Claims

1. A motor drive circuit that controls the driving of a three-phase motor, wherein, The motor drive circuit has the following features: The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. The output current flowing from the motor drive circuit to the three-phase motor is recorded as positive current, and the output current flowing from the three-phase motor to the motor drive circuit is recorded as negative current. A first input terminal is to which a first voltage is applied; The second input terminal is subjected to a second voltage that is lower than the first voltage; A capacitor is connected between the first input terminal and the second input terminal; as well as Three interconnected elements, each consisting of two semiconductor switching elements connected in series. The three series bodies are connected in parallel to each other. One end of each of the three series-connected terminals is connected to the first input terminal, and the other end is connected to the second input terminal. The three connected series bodies each have: A first semiconductor switching element is connected to the first input terminal; as well as A second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected bodies is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a specified PWM cycle. In at least a portion of the three-phase output current, where two phases have positive output current and one phase has negative output current, each defined PWM cycle includes a period during which one of the first semiconductor switching elements corresponding to one of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform.

2. The motor drive circuit according to claim 1, wherein, The at least part of the period also includes a negative disconnection and positive turn-on period corresponding to the second semiconductor switching element being disconnected when the output current is negative. During the negative disconnection and positive connection period, the first semiconductor switching element corresponding to the positive output current is turned on.

3. The motor drive circuit according to claim 1 or 2, wherein, For more than half of the period during which two phases of the three-phase output current are positive and one phase is negative, the waveform of the three-phase output voltage becomes a waveform that is lower than the three-phase sinusoidal voltage waveform.

4. A motor drive circuit that controls the driving of a three-phase motor, wherein, The motor drive circuit has the following features: The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. The output current flowing from the motor drive circuit to the three-phase motor is recorded as positive current, and the output current flowing from the three-phase motor to the motor drive circuit is recorded as negative current. A first input terminal is to which a first voltage is applied; The second input terminal is subjected to a second voltage that is lower than the first voltage; A capacitor is connected between the first input terminal and the second input terminal; as well as Three interconnected elements, each consisting of two semiconductor switching elements connected in series. The three series bodies are connected in parallel to each other. One end of each of the three series-connected terminals is connected to the first input terminal, and the other end is connected to the second input terminal. The three connected series bodies each have: A first semiconductor switching element is connected to the first input terminal; as well as A second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected bodies is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a specified PWM cycle. In at least a portion of the three-phase output current, where the output current of two phases is negative and the output current of one phase is positive, each defined PWM cycle includes a period during which the second semiconductor switching element corresponding to one of the phases with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and a period during which the other phase with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform.

5. The motor drive circuit according to claim 4, wherein, The at least part of the period also includes a positive off-off and negative on-off period corresponding to when the first semiconductor switching element is off when the output current is positive. During the positive disconnection and negative connection period, the second semiconductor switching element corresponding to the negative output current is turned on.

6. The motor drive circuit according to claim 4 or 5, wherein, The waveform of the three-phase output voltage becomes a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform for more than half of the period during which the output current of two phases is negative and the output current of one phase is positive.

7. A motor drive circuit for controlling the drive of a three-phase motor, wherein, The motor drive circuit has the following features: The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. The output current flowing from the motor drive circuit to the three-phase motor is recorded as positive current, and the output current flowing from the three-phase motor to the motor drive circuit is recorded as negative current. A first input terminal is to which a first voltage is applied; The second input terminal is subjected to a second voltage that is lower than the first voltage; A capacitor is connected between the first input terminal and the second input terminal; as well as Three interconnected elements, each consisting of two semiconductor switching elements connected in series. The three series bodies are connected in parallel to each other. One end of each of the three series-connected terminals is connected to the first input terminal, and the other end is connected to the second input terminal. The three connected series bodies each have: A first semiconductor switching element is connected to the first input terminal; as well as A second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected bodies is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a specified PWM cycle. In at least a portion of the three-phase output current, where two phases have positive output current and one phase has negative output current, each defined PWM cycle includes a period during which one of the first semiconductor switching elements corresponding to one of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and a period during which the other of the phases with positive output current is turned on and the other two corresponding first semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly reduced in voltage compared to the three-phase sinusoidal voltage waveform. In at least a portion of the three-phase output current, where the output current of two phases is negative and the output current of one phase is positive, each predetermined PWM cycle includes a period during which the second semiconductor switching element corresponding to one of the phases with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and a period during which the second semiconductor switching element corresponding to another phase with negative output current is turned on and the other two corresponding second semiconductor switching elements are turned off, and the waveform of the three-phase output voltage is a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform.

8. The motor drive circuit according to claim 7, wherein, At least a portion of the period when two phases of the three-phase output current are positive and one phase is negative includes a negative disconnection / positive on period corresponding to the negative output current, during which the second semiconductor switching element is disconnected. During the negative disconnection and positive connection period, the first semiconductor switching element corresponding to the positive output current is turned on. In the case where two phases of the three-phase output current are negative and one phase has a positive output current, the at least part of the period further includes a positive disconnection and negative connection period corresponding to the first semiconductor switching element being disconnected when the output current is positive. During the positive disconnection and negative connection period, the second semiconductor switching element corresponding to the negative output current is turned on.

9. A motor drive circuit that controls the driving of a three-phase motor, wherein, The motor drive circuit has the following features: The three output terminals output three-phase output voltage and three-phase output current to the three-phase motor. The output current flowing from the motor drive circuit to the three-phase motor is recorded as positive current, and the output current flowing from the three-phase motor to the motor drive circuit is recorded as negative current. A first input terminal is to which a first voltage is applied; The second input terminal is subjected to a second voltage that is lower than the first voltage; A capacitor is connected between the first input terminal and the second input terminal; as well as Three interconnected elements, each consisting of two semiconductor switching elements connected in series. The three series bodies are connected in parallel to each other. One end of each of the three series-connected terminals is connected to the first input terminal, and the other end is connected to the second input terminal. The three connected series bodies each have: A first semiconductor switching element is connected to the first input terminal; as well as A second semiconductor switching element is connected to the second input terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection point of each of the three series-connected bodies is connected to the three output terminals. The first semiconductor switching element switches on and off at a predetermined PWM cycle. The second semiconductor switching element switches on and off at a specified PWM cycle. During at least a portion of the three-phase output current, where two phases have positive output current and one phase has negative output current, each predetermined PWM cycle includes a negative-off-positive-on period corresponding to the off state of the second semiconductor switching element when the output current is negative, during which the first semiconductor switching element corresponding to the positive output current is on, and the waveform of the three-phase output voltage becomes a waveform that is uniformly reduced in voltage compared to the three-phase sinusoidal voltage waveform. During at least a portion of the three-phase output current, where two phases have negative output current and one phase has positive output current, each defined PWM cycle includes a positive-off-negative-on period when the first semiconductor switching element corresponding to the positive output current is off, during which the second semiconductor switching element corresponding to the negative output current is on, and the waveform of the three-phase output voltage becomes a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform.

10. The motor drive circuit according to any one of claims 7 to 9, wherein, For more than half of the period during which two phases of the three-phase output current are positive and one phase is negative, the waveform of the three-phase output voltage becomes a waveform that is uniformly reduced in voltage relative to the three-phase sinusoidal voltage waveform. The waveform of the three-phase output voltage becomes a waveform that is uniformly increased in voltage relative to the three-phase sinusoidal voltage waveform for more than half of the period during which the output current of two phases is negative and the output current of one phase is positive.

11. The motor drive circuit according to any one of claims 7 to 9, wherein, The waveform of the three-phase output voltage is a waveform obtained by superimposing one or more higher harmonics onto the three-phase sinusoidal voltage waveform. The waveform of the output voltage of the three phases is a waveform obtained by superimposing the sinusoidal voltage waveform of the three phases with third harmonics of different signs.

12. The motor drive circuit according to claim 11, wherein, The phase of the higher harmonics is adjusted according to the phase of the output current of the three phases.

13. The motor drive circuit according to claim 12, wherein, The phase of the higher harmonics is the same as the phase of the output current of the three phases.

14. The motor drive circuit according to claim 12, wherein, The phase of the higher harmonics has a phase difference with the phase of the three-phase output current within an electrical angle of 30 degrees.

15. The motor drive circuit according to claim 14, wherein, The phase of the higher harmonics is also adjusted according to the amplitude of the sinusoidal voltage waveform of the three phases.

16. The motor drive circuit according to claim 11, wherein, The waveforms of the multiple higher harmonics relative to the output voltage of each phase also include waveforms of the 3Nth order, where N is an integer greater than or equal to 2.

17. The motor drive circuit according to claim 16, wherein, N is an odd number.

18. A motor module comprising: The motor drive circuit according to any one of claims 1 to 17; and A three-phase motor, which is driven by the motor drive circuit.

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