A method for improving the growth of planar dislocations in silicon carbide epitaxial layers

Abstract

This invention discloses a growth method for improving planar dislocations in silicon carbide epitaxial layers, relating to the field of silicon carbide epitaxial layer growth. The method includes the following steps: S1, performing plasma cleaning on the silicon carbide substrate; S2, growing a first buffer layer on the silicon carbide substrate; S3, performing a first high-temperature heat treatment to repair the lattice, heating to 1650–1800°C, introducing only nitrogen gas, holding for 10–20 minutes, and then rapidly cooling to the buffer layer reaction temperature; S4, growing a second buffer layer; S5, performing a second high-temperature heat treatment. The lattice is repaired by heat treatment. The temperature is raised to 1650-1800℃, the carbon source, silicon source gas, and hydrogen are turned off, and only nitrogen is introduced. After holding for 10-20 minutes, the temperature is rapidly reduced to the buffer layer reaction temperature. S6, the third buffer layer is grown. S7, the epitaxial layer is grown in a conventional manner. S8, after the epitaxial growth is completed, the reaction gas is turned off, the temperature is reduced to 700-1000℃, and the silicon carbide epitaxial wafer is removed. This invention can improve the BPD conversion efficiency, inhibit the formation of BPD in the epitaxial layer, and has a simple production process that saves production time.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide epitaxial layer growth technology, and more particularly to a growth method for improving the basal plane dislocations of silicon carbide epitaxial layers. Background Technology

[0002] Defects in silicon carbide epitaxial wafers have a critical impact on the final device. During epitaxial growth, approximately 98% of threading screw dislocations (TSDs) in the substrate are converted into TSDs, while the remainder are converted into stacking faults (SFs). Threading edge dislocations (TEDs) are 100% converted into TEDs, and about 90% of base plane dislocations (BPDs) are converted into TEDs, with a small portion remaining as BPDs. Studies have shown that TSDs and TEDs have minimal impact on the performance of the final silicon carbide device, while BPDs can lead to device performance degradation or even failure, especially in bipolar devices. Therefore, effective suppression of BPDs is crucial during the fabrication of semiconductor epitaxial materials.

[0003] Existing methods for suppressing BPD defects include two approaches: one involves shutting down the growth and doping sources, performing high-temperature hydrogen annealing at the interface to shift the BPD-TED conversion point downwards, and then using highly doped and gradient buffer layers to facilitate the transition and eliminate some BPD conversion. The other approach involves creating multiple cycles of high- and low-doped composite buffer layers on a silicon carbide substrate, and then performing high-temperature hydrogen etching on each buffer layer at the interface to promote the conversion of BPD defects to TED defects using interfacial forces. However, existing suppression methods struggle to completely eliminate the substrate's influence, and all involve hydrogen etching, only partially converting BPD defects, leading to incomplete conversion. This is primarily because hydrogen etching thins the buffer layer, which already has a low flow rate, especially at low flow rates. Furthermore, prolonged annealing times reduce the machine's mass production capacity and lower production efficiency. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned defects in the prior art and provide an improved method for growing base plane dislocations in silicon carbide epitaxial layers. This method can improve BPD conversion efficiency, suppress the formation of BPD in the epitaxial layer, improve product quality, and has a simple production process that can save production time and increase production volume.

[0005] To achieve the above objectives, the present invention provides a method for improving the growth of planar dislocations in silicon carbide epitaxial layers, comprising the following steps:

[0006] S1. Place the silicon carbide substrate to be epitaxially grown into a plasma cleaner for plasma cleaning.

[0007] S2. Place the silicon carbide substrate in the growth position within the silicon carbide epitaxial furnace reaction chamber, gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source gas, carbon source gas, and dopant source nitrogen gas until the main gas flow rate reaches 60-100 slm, and raise the temperature to 1600-1700℃ to grow the first buffer layer.

[0008] S3. The first high-temperature heat treatment is performed to repair the crystal lattice. The temperature is rapidly increased to 1650-1800℃, while the carbon source, silicon source gas and hydrogen are turned off. Only nitrogen is introduced, and the gas flow rate is between 50-200 sccm. After holding for 10-20 minutes, the temperature is rapidly reduced to the buffer layer reaction temperature.

[0009] S4. Hydrogen gas is gradually introduced into the reaction chamber, along with small flow rates of silicon source gas, carbon source gas, and doped source nitrogen gas, until the main gas flow rate reaches 60-100 slm. The temperature is then raised to 1600-1700℃ to grow the second buffer layer.

[0010] S5. The second high-temperature heat treatment is performed to repair the crystal lattice. The temperature is rapidly increased to 1650-1800℃, while the carbon source, silicon source gas and hydrogen are turned off. Only nitrogen is introduced, and the gas flow rate is between 50-200 sccm. After holding for 10-20 minutes, the temperature is rapidly reduced to the buffer layer reaction temperature.

[0011] S6. Gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source gas, carbon source gas and doped source nitrogen gas until the main gas flow rate reaches 60-100 slm. Raise the temperature to 1600-1700℃. After the gas flow rate parameters reach and stabilize at the epitaxial growth conditions, grow the third buffer layer.

[0012] S7. After the third buffer layer is grown, perform conventional epitaxial layer growth.

[0013] S8. After completing the epitaxial growth of the complete structure, shut off the reaction gas and cool down to 700-1000℃, then remove the silicon carbide epitaxial wafer.

[0014] In the above technical solution, the gas flow ratio for Plasma cleaning is O2:N2:CF4 = 5:2:1.

[0015] In the above technical solution, the Plasma cleaning process takes 5-20 minutes.

[0016] In the above technical solution, the working pressure of the Plasma cleaning is 200-350 mtorr, and the power is 3-12 kW.

[0017] In the above technical solution, the carbon source gas is methane, ethylene, acetylene, or propane; the silicon source gas is silane, dichlorosilane, trichlorosilane, or tetrachlorosilane.

[0018] In the above technical solution, in steps S2, S3 and S6, the flow ratio of silicon source gas and hydrogen is controlled to be less than 0.03%.

[0019] This technical solution also provides a medium- and high-voltage semiconductor device, which uses a silicon carbide epitaxial wafer grown using a growth method for improving the base plane dislocations of the silicon carbide epitaxial layer as a raw material.

[0020] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0021] 1. In this technical solution, plasma is used to treat the surface of the silicon carbide substrate before growth. Plasma can better clean the substrate surface, eliminate some small impurities, and increase the surface state energy of the substrate, promoting the bonding of silicon carbide bonds. This allows the epitaxial growth to be better carried out in a step-by-step manner with the substrate.

[0022] 2. In this technical solution, after the first buffer layer is grown, a nitrogen high-temperature rapid heat treatment is performed, mainly to suppress BPD that is not completely converted from the substrate and is not converted. A second nitrogen high-temperature heat treatment is added between the second and third buffer layers, mainly because if only one nitrogen high-temperature rapid heat treatment is performed, the BPD suppression effect will be unstable and it will easily lead to incomplete BPD suppression.

[0023] 3. This technical solution can improve BPD conversion efficiency, suppress the formation of BPD in the epitaxial layer, improve product quality, and the production process is simple, which can save production time, increase production volume, thereby reducing the cost of silicon carbide semiconductor materials and expanding the commercialization of silicon carbide materials. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a method for improving the growth of base-plane dislocations in silicon carbide epitaxial layers provided by the present invention;

[0026] Figure 2 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer 1 using conventional processes;

[0027] Figure 3 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer 2 using conventional processes;

[0028] Figure 4 This is a BPD distribution diagram after growing a silicon carbide epitaxial wafer 3 using a conventional process;

[0029] Figure 5 This is a BPD distribution diagram after growing a silicon carbide epitaxial wafer 4 using the conventional process;

[0030] Figure 6 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer #1 using this technical solution;

[0031] Figure 7 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer #2 using this technical solution;

[0032] Figure 8 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer #3 using this technical solution;

[0033] Figure 9 This is a BPD distribution diagram after growing silicon carbide epitaxial wafer #4 using this technical solution. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0036] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0038] like Figures 1-9 As shown, this embodiment provides a method for improving the growth of base-plane dislocations in silicon carbide epitaxial layers, which includes the following steps:

[0039] S1. Place the silicon carbide substrate to be epitaxially grown into a plasma cleaner for plasma cleaning. Plasma cleaning can better clean the substrate surface, eliminate some microscopic impurities, and increase the surface state energy of the substrate, promoting silicon carbide bond bonding. This allows for better step-by-step crystal growth between the epitaxial layer and the substrate, and promotes better TED conversion of the inherent BPD on the substrate between the epitaxial buffer layer interface. Plasma cleaning before silicon carbide substrate growth can improve the conversion of silicon carbide BPD between the substrate and the buffer layer, and reduce the amount of BPD conversion during the subsequent silicon carbide epitaxial process. The preferred process parameters for plasma cleaning are: working pressure of 200-350 mtorr, power of 3-12 kW, time of 5-20 min, and gas flow ratio of O2:N2:CF4 = 5:2:1.

[0040] S2. Place the cleaned silicon carbide substrate into the growth position within the silicon carbide epitaxial furnace reaction chamber. Gradually introduce hydrogen gas into the reaction chamber, along with small flow rates of silicon source gas, carbon source gas, and dopant nitrogen gas. Control the flow rate ratio of silicon source gas to hydrogen gas to be less than 0.03% until the main gas flow rate reaches 60-100 slm. Raise the temperature to 1600-1700℃ to grow the first buffer layer. In this technical solution, the carbon source gas can be methane, ethylene, acetylene, or propane; the silicon source gas can be silane, dichlorosilane, trichlorosilane, or tetrachlorosilane.

[0041] S3. For the first time, perform high-temperature heat treatment to repair the crystal lattice. Rapidly raise the temperature to 1650-1800℃, while shutting off the carbon source, silicon source gas and hydrogen gas, and only introducing nitrogen gas with a flow rate between 50-200 sccm. After maintaining this temperature for 10-20 minutes, rapidly cool it down to the buffer layer reaction temperature.

[0042] S4. Gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source, carbon source gas and dopant source nitrogen gas, controlling the flow rate ratio of silicon source and hydrogen to be less than 0.03%, until the main gas flow rate reaches 60-100 slm, and raise the temperature to 1600-1700℃ to grow the second buffer layer.

[0043] S5. Perform a second high-temperature heat treatment to repair the crystal lattice. Rapidly raise the temperature to 1650-1800℃, while shutting off the carbon source, silicon source gas, and hydrogen gas. Only nitrogen gas is introduced, and the gas flow rate is between 50-200 sccm. After maintaining this temperature for 10-20 minutes, rapidly cool it down to the buffer layer reaction temperature.

[0044] S6. Gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source, carbon source gas and dopant nitrogen source gas, controlling the flow rate ratio of silicon source and hydrogen to be less than 0.03%, until the main gas flow rate reaches 60-100 slm, raise the temperature to 1600-1700℃, and after the gas flow rate parameters reach and stabilize at the epitaxial growth conditions, grow the third buffer layer.

[0045] S7. After the third buffer layer is grown, proceed with the conventional epitaxial layer growth, following the product specifications.

[0046] S8. After completing the epitaxial growth of the complete structure, shut off the reaction gas and cool down to 700-1000℃, then remove the silicon carbide epitaxial wafer.

[0047] In summary, this technical solution employs a nitrogen-based high-temperature rapid thermal treatment after the first buffer layer is grown. This is primarily to suppress incompletely converted and unconverted BPD from the silicon carbide substrate. A second nitrogen-based high-temperature rapid thermal treatment is then added between the second and third buffer layers to repair the lattice. This is because a single nitrogen-based high-temperature rapid thermal treatment results in unstable BPD suppression and may lead to incomplete suppression. This technical solution uses two nitrogen-based high-temperature rapid thermal treatments, which improves the BPD suppression effect. Furthermore, the use of nitrogen for high-temperature rapid thermal treatment in this technical solution can improve the production efficiency of the silicon carbide substrate.

[0048] Please see Figures 2-5Silicon carbide epitaxial wafers are obtained by growing silicon carbide substrates using conventional processes. This means that no plasma cleaning is performed before growth, and hydrogen etching is used during high-temperature annealing. The surface BPD (Body Diagram Processing) particle count is typically around 300. The BPD particle count on the surface of silicon carbide epitaxial wafer 1 is 315, on silicon carbide epitaxial wafer 2 it is 315, on silicon carbide epitaxial wafer 3 it is 318, and on silicon carbide epitaxial wafer 4 it is 378. These particles are mainly concentrated in the center of the epitaxial wafer. Please refer to [link / reference needed]. Figures 6-9 Using this technical solution, silicon carbide substrates were grown to obtain silicon carbide epitaxial wafers. The number of BPD particles on the surface of silicon carbide epitaxial wafer 1# was 0, the number of BPD particles on the surface of silicon carbide epitaxial wafer 2# was 7, the number of BPD particles on the surface of silicon carbide epitaxial wafer 3# was 4, and the number of BPD particles on the surface of silicon carbide epitaxial wafer 4# was 0. It can be seen that using this technical solution to grow silicon carbide substrates results in a high BPD conversion rate, reaching 99%. This technical solution can suppress the formation of BPD in the epitaxial layer, improve BPD conversion efficiency, and thus improve product quality. Furthermore, the production process of this technical solution is simple, saving production time and improving production efficiency, thereby reducing the cost of silicon carbide semiconductor materials and expanding the commercialization of silicon carbide materials.

[0049] This technical solution also provides a medium- and high-voltage semiconductor device, which uses the aforementioned silicon carbide epitaxial wafer as raw material.

[0050] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for improving the growth of planar dislocations in silicon carbide epitaxial layers, characterized in that, Includes the following steps: S1. Place the silicon carbide substrate to be epitaxially grown into a plasma cleaner for plasma cleaning. S2. Place the silicon carbide substrate in the growth position of the silicon carbide epitaxial furnace reaction chamber, gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source gas, carbon source gas and doping source nitrogen gas until the hydrogen flow rate reaches 60-100 slm, raise the temperature to 1600~1700℃, and grow the first buffer layer. S3. The first high-temperature heat treatment is performed to repair the crystal lattice. The temperature is rapidly increased to 1650~1800℃, while the carbon source, silicon source gas and hydrogen are turned off. Only nitrogen is introduced, and the gas flow rate is between 50-200 sccm. After holding for 10~20 minutes, the temperature is rapidly reduced to the buffer layer reaction temperature of 1600~1700℃. S4. Gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source gas, carbon source gas and doped source nitrogen gas until the hydrogen flow rate reaches 60-100 slm, and carry out the growth of the second buffer layer. S5. Perform a second high-temperature heat treatment to repair the crystal lattice. Rapidly raise the temperature to 1650~1800℃, while shutting off the carbon source, silicon source gas and hydrogen gas, and only introducing nitrogen gas with a flow rate between 50-200 sccm. After maintaining this temperature for 10~20 minutes, rapidly cool it down to the buffer layer reaction temperature of 1600~1700℃. S6. Gradually introduce hydrogen into the reaction chamber, and introduce small flow rates of silicon source gas, carbon source gas and doped source nitrogen gas until the hydrogen flow rate reaches 60-100 slm. After the gas flow rate parameters reach and stabilize at the epitaxial growth conditions, grow the third buffer layer. S7. After the third buffer layer is grown, perform conventional epitaxial layer growth. S8. After completing the epitaxial growth of the complete structure, shut off the reaction gas and cool down to 700~1000℃, then remove the silicon carbide epitaxial wafer.

2. The method for improving the growth of planar dislocations in silicon carbide epitaxial layers according to claim 1, characterized in that, The gas flow ratio for the Plasma cleaning is O2:N2:CF4 = 5:2:

1.

3. The method for improving the growth of planar dislocations in silicon carbide epitaxial layers according to claim 2, characterized in that, The Plasma cleaning process takes 5-20 minutes.

4. A method for improving the growth of planar dislocations in a silicon carbide epitaxial layer according to claim 2 or 3, characterized in that, The working pressure of the Plasma cleaning is 200~350 mtorr, and the power is 3~12KW.

5. The method for improving the growth of planar dislocations in silicon carbide epitaxial layers according to claim 1, characterized in that, The carbon source gas is methane, ethylene, acetylene, or propane; the silicon source gas is silane, dichlorosilane, trichlorosilane, or tetrachlorosilane.

6. The method for improving the growth of planar dislocations in silicon carbide epitaxial layers according to claim 1, characterized in that, In steps S2, S4, and S6, the flow rate ratio of silicon source gas to hydrogen is controlled to be less than 0.03%.

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