Queue-type DMA controller circuit and data transmission method for PCIE bus

Abstract

The present application discloses a queue-type DMA controller circuit and data transmission method for a PCIE bus. The circuit includes: an interface module, a descriptor engine module, a channel module, a completion engine module, an AXI_FULL_MASTER interface module, and an AXI_STREAM_MASTER interface module. During transmission, the descriptor list is sent to the DMA control circuit for processing in the PCIE TLP packet format. After the DMA control circuit processes and arranges the descriptors, it parses the information therein, forms a queue of descriptors according to the transaction information, and executes each descriptor in the queue in sequence to complete the data transmission of each transaction. The application of the present application solution can realize the transmission of multiple transactions at one time, solve the problem of data transmission with discontinuous addresses, and help to relieve the CPU load and improve data processing efficiency.

Description

Technical Field

[0001] The present application belongs to the field of digital circuit technology, and relates to the field of DMA transmission technology of PCIE bus, and in particular to a queue-type DMA controller circuit and data transmission method for PCIE bus. Background Art

[0002] The development of computer and bus technologies has driven the widespread application of data transmission in various fields. With the rapid development of data transmission technology, high-speed interface buses are rapidly updated, and data transmission bandwidth is increasing. PCIE, as a new-generation bus interface standard, is influenced by the rapid development of industrial technology. Compared with its predecessor, PCI, it has demonstrated advantages such as high bandwidth, high performance, low power consumption, low latency, and high transmission reliability.

[0003] DMA (Direct Memory Access) technology is a key and advanced technology in modern computer systems. Before the advent of DMA, data transmission between the CPU and peripherals involved polling and interrupts. The CPU directly connected to other components via the system bus for data transfer. To adapt to the operating frequency of external devices, the processor spent a significant number of clock cycles waiting for data and interrupts, resulting in inefficiency in data acquisition. DMA technology effectively prevents CPU cycles from being dominated by data access transactions. The CPU offloads data transfer tasks to DMA, indirectly improving CPU processing capabilities. In today's high-speed bus interface systems, the transmission and processing of large amounts of data is a crucial factor in system design. DMA transfer circuits used in PCIE bus technology provide excellent technical support for high-speed data transmission and efficient processing.

[0004] In the prior art, the DMA controller of the SOC chip generally adopts register-based DMA, that is, the CPU core configures the destination address, source address, data length and other information to the DMA controller for data transmission. After each transaction is completed, an interrupt signal is sent to the CPU. Data with discontinuous addresses cannot be sent, and the CPU is not well liberated. Summary of the Invention

[0005] In order to address the deficiencies of the above-mentioned prior art, the present application provides a queue-type DMA controller circuit and data transmission method for a PCIE bus. Combined with the characteristics of the PCIE bus TLP packet data format, multiple transaction transmissions can be realized at one time, solving the problem of data transmission with discontinuous addresses, which is conducive to freeing up the CPU load and improving data processing efficiency.

[0006] In order to achieve the above object, the present invention adopts the following technologies:

[0007] A queue-type DMA controller circuit for a PCIE bus is connected between the PCIE and a functional module, comprising: an interface module, a descriptor engine module, a channel module, a completion engine module, an AXI_FULL_MASTER interface module, and an AXI_STREAM_MASTER interface module;

[0008] The interface module includes an AXI_STREAM read interface and an AXI_STREAM write interface. The AXI_STREAM read interface is connected to the PCIE bus, the descriptor engine module, and the channel module. The AXI_STREAM write interface is connected to the PCIE bus, the completion engine module, and the channel module. The descriptor engine module is connected to the channel module and the completion engine module. The channel module is connected to the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module, and the AXI_STREAM_MASTER interface module. The AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module are connected between the channel module and the functional module.

[0009] The AXI_STREAM read interface is used to receive TLP packets from the PCIE bus and parse the TLP packets according to the TLP packet format: if it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module;

[0010] The descriptor engine module is used to queue the received descriptors and transmit them one at a time to the channel module in the queue order;

[0011] The channel module is used to receive the descriptor transmitted by the descriptor engine module, and select the AXI_FULL_MASTER interface module to transmit data with the function module through the address mapping addressing mode according to the information in the descriptor, or select the AXI_STREAM_MASTER interface module to transmit data with the function module through the data stream form, and after completing each read and write operation, send the data transmission information to the completion engine module;

[0012] The completion engine module is used to receive information sent by the channel module, and create a completion descriptor after each reception, and notify the descriptor engine module to transmit the next descriptor; when all transactions are completed, all completion descriptors are made into a descriptor queue and transmitted to the AXI_STREAM write interface, so that TLP packets are generated through the AXI_STREAM write interface and sent to the PCIE bus.

[0013] A data transmission method for a queue-type DMA controller circuit of a PCIE bus, comprising the steps of:

[0014] The interface module uses the AXI_STREAM read interface to obtain TLP packets from the PCIE bus through data stream mode, and parses the TLP packets according to the TLP packet format: if it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module;

[0015] The descriptor format is designed with two transaction IDs to determine the priority of the transaction described by the descriptor. When the descriptor engine module queues the descriptors, it queues the received descriptors according to the priority and transmits them one at a time to the channel module in the queue order.

[0016] The channel module receives the descriptor transmitted by the descriptor engine module, and selects the AXI_FULL_MASTER interface module to transmit data with the function module through the address mapping addressing mode according to the information in the descriptor, or selects the AXI_STREAM_MASTER interface module to transmit data with the function module through the data stream form; after completing each read and write operation, the channel module sends the data transmission information to the completion engine module;

[0017] The completion engine module receives the information sent by the channel module, and creates a completion descriptor after each reception, and notifies the descriptor engine module to transmit the next descriptor;

[0018] When all transactions are completed, the completion engine module makes all completion descriptors into a descriptor queue, transmits them to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface, and sends them to the PCIE bus.

[0019] The beneficial effects of the present invention are:

[0020] 1. The queue-type DMA controller circuit designed in this application for the PCIE bus mainly performs data transfer through the packet format of the PCIE protocol. Before data transmission, the CPU allocates a memory space in the host space and writes the information of the transaction to be transmitted into the descriptor. Multiple descriptors form a descriptor list and are stored in this memory space. The descriptor engine module of the designed circuit queues these descriptors in the descriptor list to complete the data transmission of multiple transactions. Therefore, multiple transactions can be transmitted at one time, solving the problem of data transmission with discontinuous addresses, which is conducive to relieving the CPU load and improving data processing efficiency.

[0021] 2. The present application presets a data type judgment bit in the first frame format of the TLP packet header, so that the interface module can transmit data to the description engine module or the channel module respectively. At the same time, the present application presets an interface type judgment bit and a read / write status judgment bit in the descriptor format, so as to facilitate the selection of different interfaces, realize data transmission through address mapping or data stream mode, and can also well manage read and write transactions separately;

[0022] 3. This application complies with the data packet format for processing the PCIE protocol. Subsequent development can change the configuration to make the circuit applicable to other interface types, with high efficiency and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is an application scenario of a queue-type DMA controller circuit for a PCIE bus and an overall structural framework diagram of the DMA controller circuit and peripheral circuits according to an embodiment of the present application.

[0024] Figure 2 This is a block diagram of the circuit structure of a queue-type DMA controller for a PCIE bus according to an embodiment of the present application.

[0025] Figure 3 The PCIE transaction layer TLP packet format of the embodiment of the present application and

[0026] Figure 4 This is the TLP packet header format of an embodiment of the present application.

[0027] Figure 5 This is the design of the descriptor format of the embodiment of the present application.

[0028] Figure 6 This is a structural block diagram of the descriptor engine module of an embodiment of the present application. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are described in detail below with reference to the accompanying drawings. However, the embodiments described in the present invention are only part of the embodiments of the present invention, rather than all the embodiments.

[0030] The embodiment of the present application provides a queue-type DMA controller circuit for a PCIE bus, such as Figure 1The following figure shows the circuit environment of its application scenario. Specifically, it is applied to a scenario where two PCIE devices are performing data transmission. One PCIE device is the host side, and the other is the endpoint side device. The two communicate via the PCIE bus. The address of the endpoint side device is mapped to the memory address of the host side. The host side can operate on the data in the endpoint side device address according to the mapped address. The endpoint side device reads and writes data through the PCIE port under the control of the host side. The DMA controller circuit of this example is configured at the endpoint side, connected between the PCIE bus and the functional module at the endpoint side, and serves as a bridge between the PCIE port and the user logic. Under the configuration of the host side CPU, it can temporarily obtain the bus from the CPU and perform data transmission between different devices on behalf of the CPU.

[0031] Before performing a data transfer, the host CPU writes the source address, destination address, data length, and configuration information of the transaction data to be transferred into a descriptor. Multiple descriptors are then grouped into a descriptor list and stored in a memory space on the host. Each TLP packet at the PCIE transaction layer consists of 32 bits, so the size of each descriptor is set to 32 x 3 bits. A descriptor list can contain a maximum of 1024 descriptors. When the host needs to perform a transaction data transfer, it sends the descriptor list to the PCIE interface as a TLP packet, which is then transmitted to the endpoint device via the PCIE bus. The data is then transferred via the DMA controller circuit.

[0032] Specifically, such as Figure 2 As shown, the DMA controller circuit of this example is connected between the PCIE bus and the functional module / user logic USER LOGIC, including: an interface module, a descriptor engine module, a channel module, a completion engine module, an AXI_FULL_MASTER interface module and an AXI_STREAM_MASTER interface module.

[0033] The interface module includes an AXI_STREAM read interface and an AXI_STREAM write interface. The AXI_STREAM read interface is connected to the PCIE bus, the descriptor engine module, and the channel module. The AXI_STREAM write interface is connected to the PCIE bus, the completion engine module, and the channel module. The descriptor engine module is connected to the channel module and the completion engine module. The channel module is connected to the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module, and the AXI_STREAM_MASTER interface module. The AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module are connected between the channel module and the functional module.

[0034] Among them, the AXI_STREAM read interface is used to receive TLP packets from the PCIE bus and parse the TLP packets according to the TLP packet format: if it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module; the AXI_STREAM write interface is used to generate data or descriptor queues into TLP packets and send them to the PCIE bus.

[0035] The descriptor engine module is used to queue the received descriptors and transmit them one at a time to the channel module in the queue order.

[0036] The channel module is used to receive the descriptor transmitted by the descriptor engine module, and select the AXI_FULL_MASTER interface module according to the information in the descriptor to transmit data with the functional module through the address mapping addressing mode, or select the AXI_STREAM_MASTER interface module to transmit data with the functional module through the data stream form, and after completing each read and write operation, send the data transmission information to the completion engine module.

[0037] The completion engine module is used to receive information sent by the channel module, and create a completion descriptor after each reception, and notify the descriptor engine module to transmit the next descriptor; when all transactions are completed, all completion descriptors are made into a descriptor queue and transmitted to the AXI_STREAM write interface, so that TLP packets are generated through the AXI_STREAM write interface and sent to the PCIE bus.

[0038] When using the DMA controller circuit of this example to perform data transmission method:

[0039] After the interface module uses the AXI_STREAM read interface to obtain a TLP packet from the PCIE bus through the data stream mode, the information in the packet is disassembled according to the format of the TLP packet. The first frame of the TLP packet header format obtained by the AXI_STREAM read interface is pre-designed with two data type judgment bits. When the AXI_STREAM read interface parses the TLP packet, it judges it as a descriptor or transaction data based on the data type judgment bits. For example, Figure 3 For PCIE transaction layer TLP packet format, Figure 4 The following shows the TLP header format. Bits 17 and 18 of the first frame of the TLP header are set as check bits. If they are 01, the data segment is a descriptor; if they are 10, the data segment is transaction data to be transmitted. If it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module.

[0040] The descriptor engine module processes the descriptors, manages them through queue sorting, and transmits them one at a time to the channel module in the queue order. The DMA transfer in this example can transfer multiple transactions at a time, and the completion of non-continuous address data transfer in a transaction requires the participation of multiple descriptors. There is a choice of transaction priority among multiple transactions, so a two-digit transaction ID is designed in the descriptor format to determine the priority of the described transaction. If the priority is high, it will be processed first. Figure 5 The descriptor format shown is 32*3 bits, with each layer containing 32 bits, for a total of three layers. The first layer of the descriptor contains transfer information. The lower sixteen bits (bits 0 to 15) represent the data length of the data transfer. Bits 16 and 17 represent the transaction ID for the descriptor, used to determine priority. Two bits can represent four states, so a DMA transfer can be set to a maximum of four times. Bits 18 and 19 determine the read / write status. If 01 indicates a read transaction, 10 indicates a write transaction. Bit 11 is reserved, and 00 is the default value. Bits 20 and 21 determine the interface type. If 01 indicates that the data transfer is performed using the AXI_FULL_MASTER interface module and the function module, and if 10 indicates that the data transfer is performed using the AXI_STREAM_MASTER interface module and the function module, bit 11 is reserved, and 00 is the default value. The remaining ten upper bits are reserved. The second 32 bits of the descriptor store the source address, from which data is read during data transfer. The third 32 bits of the descriptor are used to store the target address, and the data read from the source address is written to this address during data transmission.

[0041] like Figure 6 As shown, the descriptor engine module includes an arbiter and a descriptor FIFO. The arbiter is used to determine the transaction ID in the descriptor to determine the priority of the transaction described by the descriptor. The descriptors are then placed into the descriptor FIFO according to the priority to form a queue, so that they can be taken one at a time and transmitted in order to the channel module. Specifically, after obtaining descriptors from the interface module, the descriptor engine module first stores these descriptors in an internally set space. Because the host can generate a maximum of 1024 descriptors, this space is set to 96*1024 bits. The arbiter then determines the descriptor IDs of these descriptors and places them into the subsequent FIFO according to the priority order, forming a descriptor queue. The descriptors are then taken one at a time and sent to the channel module in order. After the channel module transmits the information contained in each descriptor, it sends a signal to the descriptor engine through the completion engine to send the next descriptor until all descriptors are consumed.

[0042] The channel module receives the descriptor transmitted by the descriptor engine module, and selects the AXI_FULL_MASTER interface module to transmit data with the functional module through address mapping addressing according to the information in the descriptor, or selects the AXI_STREAM_MASTER interface module to transmit data with the functional module through data stream form; after completing each read and write operation, the channel module sends the data transmission information to the completion engine module.

[0043] like Figure 2 As shown, the channel module includes a control module, two read FIFOs, and two write FIFOs, wherein one read FIFO is connected to the AXI_STREAM read interface and the AXI_FULL_MASTER interface module, the other read FIFO is connected to the AXI_STREAM read interface and the AXI_STREAM_MASTER interface module, one write FIFO is connected to the AXI_STREAM write interface and the AXI_FULL_MASTER interface module, and the other write FIFO is connected to the AXI_STREAM write interface and the AXI_STREAM_MASTER interface module.

[0044] Specifically, the AXI_FULL_MASTER interface module includes an AXI_FULL read interface and an AXI_FULL write interface. When the AXI_FULL_MASTER interface module is selected to transmit data through the address mapping addressing mode, the AXI_FULL read interface processes data read operations that comply with the AXI4 bus protocol, and the AXI_FULL write interface processes data write operations that comply with the AXI4 bus protocol.

[0045] The AXI_STREAM_MASTER interface module includes an AXI_STREAM read interface and an AXI_STREAM write interface. When the AXI_STREAM_MASTER interface module is selected to perform data transmission in the form of a data stream, it is performed in a manner that complies with the AXI_STREAM protocol.

[0046] The descriptor format is designed with two read-write status judgment bits. When the channel module performs each read-write operation, it determines whether the current read-write operation belongs to a write transaction or a read transaction based on the read-write status judgment bits: if it is a write transaction, the data is read through the AXI_STREAM read interface and the write operation is performed through the write FIFO inside the channel module; if it is a read transaction, the data is read through the AXI_FULL_MASTER interface module or the AXI_STREAM_MASTER interface module, and the read operation is performed through a read FIFO inside the channel module and the AXI_STREAM write interface.

[0047] The descriptor format is designed with two interface type judgment bits. When the channel module performs each read and write operation, it selects the AXI_FULL_MASTER interface module or the AXI_STREAM_MASTER interface module based on the interface type judgment bits.

[0048] (1) When selecting the AXI_FULL_MASTER interface module:

[0049] If it is a read transaction, the control module reads data from the functional module through the AXI_FULL_MASTER interface module according to the source address and data length information, and puts it into the read FIFO. Then, the interface module makes the read data, destination address and device information into a TLP packet and sends it to the PCIE bus through the AXI_STREAM write interface for transmission;

[0050] If it is a write transaction, the control module transmits the source address and data length information to the interface module, the interface module writes the source address and data length information into the TLP packet, and issues a read request through the PCIE bus. The host sends the required transaction data to the interface module in the format of the TLP packet according to the request. The interface module determines that the data in the currently received TLP packet is transaction data, and sends the data to the channel module. After passing through the write FIFO, the AXI_FULL_MASTER interface module writes the data to the target address according to the destination address information;

[0051] (2) When selecting the AXI_STREAM_MASTER interface module:

[0052] If it is a read transaction, the data is transmitted without a passive address. The data of the functional module is sent to the read FIFO of the channel module by the AXI_STREAM_MASTER interface module in the form of a data stream, and then sent to the interface module. The interface module makes the read data, destination address and device information into a TLP packet and sends it to the PCIE bus through the AXI_STREAM write interface for transmission;

[0053] If it is a write transaction, the data transmission has no target address. The control module transmits the source address and data length information to the interface module. The interface module writes the source address and data length information into the TLP packet and issues a read request through the PCIE bus. The host sends the required transaction data to the interface module in the format of the TLP packet according to the request. The interface module determines that the data in the currently received TLP packet is transaction data and sends the data to the channel module. After passing through the write FIFO, the AXI_STREAM_MASTER interface module writes the data into the functional module in the form of a data stream.

[0054] The completion engine module receives the information sent by the channel module, creates a completion descriptor after each reception, and notifies the descriptor engine module to transmit the next descriptor; when all transactions are completed, the completion engine module creates all completion descriptors into a descriptor queue, transmits them to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface, and sends them to the PCIE bus to notify the completion of the DMA transfer.

[0055] In this example, the queue-based DMA controller design proposes a CPU that writes the destination address, source address, and data length of the data being transferred into a descriptor. Multiple descriptors form a descriptor list, encompassing the transfer of multiple transactions. Incorporating the characteristics of the PCIE bus, the descriptor list is sent to the DMA for processing in the PCIE TLP format. After processing and arranging the descriptors, the DMA parses the information contained within them, organizes the descriptors into queues based on the transaction information, and executes each descriptor in the queue sequentially to complete the data transfer for each transaction.

[0056] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application.

Claims

1. A queue-type DMA controller circuit for a PCIE bus, connected between the PCIE bus and a functional module, characterized in that: Includes: interface module, descriptor engine module, channel module, completion engine module, AXI_FULL_MASTER interface module and AXI_STREAM_MASTER interface module; The interface module includes an AXI_STREAM read interface and an AXI_STREAM write interface. The AXI_STREAM read interface is connected to the PCIE bus, the descriptor engine module, and the channel module. The AXI_STREAM write interface is connected to the PCIE bus, the completion engine module, and the channel module. The descriptor engine module is connected to the channel module and the completion engine module. The channel module is connected to the descriptor engine module, the completion engine module, the AXI_FULL_MASTER interface module, and the AXI_STREAM_MASTER interface module. The AXI_FULL_MASTER interface module and the AXI_STREAM_MASTER interface module are connected between the channel module and the function module. The AXI_STREAM read interface is used to receive TLP packets from the PCIE bus and parse the TLP packets according to the TLP packet format: if it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module; The descriptor engine module is used to queue the received descriptors and transmit them one at a time to the channel module in the queue order; The channel module is used to receive the descriptor transmitted by the descriptor engine module, and select the AXI_FULL_MASTER interface module to transmit data with the function module through the address mapping addressing mode according to the information in the descriptor, or select the AXI_STREAM_MASTER interface module to transmit data with the function module through the data stream form, and after completing each read and write operation, send the data transmission information to the completion engine module; The completion engine module is used to receive information sent by the channel module, and create a completion descriptor after each reception, and notify the descriptor engine module to transmit the next descriptor; when all transactions are completed, all completion descriptors are made into a descriptor queue and transmitted to the AXI_STREAM write interface, so that TLP packets are generated through the AXI_STREAM write interface and sent to the PCIE bus.

2. The queue-type DMA controller circuit for PCIE bus according to claim 1, characterized in that: The descriptor engine module includes an arbiter and a descriptor FIFO. The arbiter is used to judge the transaction ID in the descriptor to obtain the priority of the transaction described by the descriptor, and put the descriptors into the descriptor FIFO to form a queue according to the priority, so that one descriptor can be taken at a time and transmitted to the channel module in sequence.

3. The queue-type DMA controller circuit for PCIE bus according to claim 2, characterized in that: The channel module includes a control module, two read FIFOs, and two write FIFOs. Among them, one read FIFO is connected to the AXI_STREAM read interface and the AXI_FULL_MASTER interface module, the other read FIFO is connected to the AXI_STREAM read interface and the AXI_STREAM_MASTER interface module, one write FIFO is connected to the AXI_STREAM write interface and the AXI_FULL_MASTER interface module, and the other write FIFO is connected to the AXI_STREAM write interface and the AXI_STREAM_MASTER interface module.

4. A data transmission method for a queue-type DMA controller circuit for a PCIE bus according to claim 3, characterized in that: Including steps: The interface module uses the AXI_STREAM read interface to obtain TLP packets from the PCIE bus through data stream mode, and parses the TLP packets according to the TLP packet format: if it is a descriptor, the descriptor is sent to the descriptor engine module; if it is transaction data, the data is sent to the channel module; The descriptor engine module queues the descriptors and sends them one at a time to the channel module in the queue order. The channel module receives the descriptor transmitted by the descriptor engine module, and selects the AXI_FULL_MASTER interface module to transmit data with the function module through the address mapping addressing mode according to the information in the descriptor, or selects the AXI_STREAM_MASTER interface module to transmit data with the function module through the data stream form; after completing each read and write operation, the channel module sends the data transmission information to the completion engine module; The completion engine module receives the information sent by the channel module, and creates a completion descriptor after each reception, and notifies the descriptor engine module to transmit the next descriptor; When all transactions are completed, the completion engine module makes all completion descriptors into a descriptor queue, transmits them to the AXI_STREAM write interface, generates TLP packets through the AXI_STREAM write interface, and sends them to the PCIE bus.

5. The data transmission method according to claim 4, characterized in that: Applicable to scenarios where two PCIE devices are transmitting data. One PCIE device is the host and the other is the endpoint device. The two communicate through the PCIE bus. The address of the endpoint device is mapped to the memory address of the host. The host can operate the data in the endpoint device address according to the mapped address. The endpoint device reads and writes data through the PCIE port under the control of the host. The DMA controller circuit is configured at the endpoint end, connected between the PCIE bus at the endpoint end and the functional module, and is used as a bridge between the PCIE port and the user logic; Before performing a data transmission, the host CPU writes the source address, destination address, data length, and configuration information of the transaction data to be transmitted into a descriptor, and stores multiple descriptors into a descriptor list in a memory space on the host. When the host needs to perform a transaction data transmission, the descriptor list is sent to the PCIE interface to form a TLP packet, which is then transmitted to the endpoint device through the PCIE bus, and then the data is transmitted through the DMA controller circuit.

6. The data transmission method according to claim 4, characterized in that The descriptor format is designed with two transaction IDs to determine the priority of the transaction described by the descriptor. When the descriptor engine module queues the descriptors, it queues the received descriptors according to the priority.

7. The data transmission method according to claim 5, characterized in that: The first frame of the TLP packet header format obtained by the AXI_STREAM read interface is pre-designed with two data type judgment bits. When the AXI_STREAM read interface parses the TLP packet, it determines whether it is a descriptor or transaction data based on the data type judgment bits.

8. The data transmission method according to claim 7, characterized in that: The descriptor format is designed with two read-write status judgment bits. When the channel module performs each read-write operation, it determines whether the current read-write operation belongs to a write transaction or a read transaction based on the read-write status judgment bits: if it is a write transaction, the data is read through the AXI_STREAM read interface and the write operation is performed through the write FIFO inside the channel module; if it is a read transaction, the data is read through the AXI_FULL_MASTER interface module or the AXI_STREAM_MASTER interface module, and the read operation is performed through a read FIFO inside the channel module and the AXI_STREAM write interface.

9. The data transmission method according to claim 8, characterized in that: The descriptor format is designed with two interface type judgment bits. When the channel module performs each read and write operation, it selects the AXI_FULL_MASTER interface module or the AXI_STREAM_MASTER interface module according to the interface type judgment bits. When selecting the AXI_FULL_MASTER interface module: If it is a read transaction, the control module reads data from the functional module through the AXI_FULL_MASTER interface module according to the source address and data length information, and puts it into the read FIFO. Then, the interface module makes the read data, destination address and device information into a TLP packet and sends it to the PCIE bus through the AXI_STREAM write interface for transmission; If it is a write transaction, the control module transmits the source address and data length information to the interface module, the interface module writes the source address and data length information into the TLP packet, and issues a read request through the PCIE bus. The host sends the required transaction data to the interface module in the format of the TLP packet according to the request. The interface module determines that the data in the currently received TLP packet is transaction data, and sends the data to the channel module. After passing through the write FIFO, the AXI_FULL_MASTER interface module writes the data to the target address according to the destination address information; When selecting the AXI_STREAM_MASTER interface module: If it is a read transaction, the data is transmitted without a passive address. The data of the functional module is sent to the read FIFO of the channel module by the AXI_STREAM_MASTER interface module in the form of a data stream, and then sent to the interface module. The interface module makes the read data, destination address and device information into a TLP packet and sends it to the PCIE bus through the AXI_STREAM write interface for transmission; If it is a write transaction, the data transmission has no target address. The control module transmits the source address and data length information to the interface module. The interface module writes the source address and data length information into the TLP packet and issues a read request through the PCIE bus. The host sends the required transaction data to the interface module in the format of the TLP packet according to the request. The interface module determines that the data in the currently received TLP packet is transaction data and sends the data to the channel module. After passing through the write FIFO, the AXI_STREAM_MASTER interface module writes the data into the functional module in the form of a data stream.

10. The data transmission method according to any one of claims 4 to 9, characterized in that: The AXI_FULL_MASTER interface module includes an AXI_FULL read interface and an AXI_FULL write interface. When the AXI_FULL_MASTER interface module is selected for data transmission through the address mapping addressing mode, the AXI_FULL read interface processes data read operations that comply with the AXI4 bus protocol, and the AXI_FULL write interface processes data write operations that comply with the AXI4 bus protocol. The AXI_STREAM_MASTER interface module includes an AXI_STREAM read interface and an AXI_STREAM write interface. When the AXI_STREAM_MASTER interface module is selected to perform data transmission in the form of a data stream, it is performed in a manner that complies with the AXI_STREAM protocol.

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