Chip and chip control method, electronic device, and storage medium

Abstract

The application discloses a chip, comprising: N core modules, N first path selectors, a first path control module, and N medium access controller (MAC) modules; N is a positive integer greater than 2; the output end of one first path selector is connected with one core module; the two input ends of the first first path selector are connected with the first MAC module and the second MAC module respectively; the two input ends of the Nth first path selector are connected with the Nth MAC module and the N-1th MAC module respectively; the three input ends of the mth first path selector are connected with the m-1th MAC module, the mth MAC module and the m+1th MAC module respectively; the first path control module is used for controlling the switch state of the first path selector when one core module is detected to be invalid, so that the first to N-1th MAC modules are respectively connected with one valid core module, and the core modules connected with different MAC modules are different.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and in particular to a chip, a chip control method, an electronic device and a storage medium. BACKGROUND

[0002] With the increase of the size of the chip on the silicon wafer, the yield of the chip will decrease. Currently, improving the yield of the wafer often includes two means:

[0003] 1. Increase the redundancy of the modules on the chip, for example, increase the redundancy of rows or columns for the memory, or increase the redundant processor for the processor.

[0004] 2. Cut a large chip into small chips, and interconnect multiple small chips through a high-speed bus based on an interposer, an integrated fan-out package (Info) technology or a multi-chip module (MCM) technology.

[0005] However, whether it is a memory redundancy technology or a multi-processor redundancy technology, a full interconnection structure needs to be adopted inside the memory or inside the multi-processor, which will occupy a lot of wiring resources.

[0006] In particular, for the redundancy design of the multi-processor, when two processors far apart from each other are redundant backups for each other, the wiring will pass through the entire chip, causing timing convergence problems in the back-end design.

[0007] In addition, by cutting a large chip into multiple small chips, the interconnection bandwidth between multiple small chips cannot exceed a certain threshold, and the interconnection between multiple small chips will also cause additional overhead and yield loss in packaging. Therefore, the existing technology for improving the yield will cause defects that cannot be ignored in other aspects. SUMMARY

[0008] Therefore, the present application provides a chip, a chip control method, an electronic device and a storage medium.

[0009] The technical solution of the present application is as follows:

[0010] In a first aspect, the present application provides a chip, comprising: N core modules, N first path selectors, a first path control module, and N medium access controller (MAC) modules; N is a positive integer greater than 2; wherein the output end of one first path selector is connected to one core module, and the core modules connected by different first path selectors are different.

[0011] The first and the Nth first path selectors each have two input terminals; the second to the (N-1)th first path selectors each have three input terminals;

[0012] The two input terminals of the first first path selector are connected with the first and the second MAC modules respectively; the two input terminals of the Nth first path selector are connected with the Nth and the (N-1)th MAC modules respectively;

[0013] The three input terminals of the mth first path selector are connected with the (m-1)th, the mth and the (m+1)th MAC modules respectively; the m is a positive integer greater than or equal to 2 and less than or equal to N-1;

[0014] The first path control module is connected with the N first path selectors respectively, and is used for controlling the switch state of the first path selector when one core module is detected to be invalid, so that the first to the (N-1)th MAC modules are connected with one valid core module respectively, and the core modules connected by different MAC modules are different.

[0015] Further, one MAC module comprises: j second path selectors, a second path control module and j+1 MACs; the j is a positive integer greater than 2; wherein the output terminal of the second path selector is connected with the input terminal of the first path selector;

[0016] One second path selector has two input terminals, and the two input terminals of the kth second path selector are connected with the kth and the (k+1)th MACs respectively; wherein the k is a positive integer greater than or equal to 1 and less than or equal to j;

[0017] The second path control module is connected with the j second path selectors respectively, and is used for controlling the switch state of the second path selector when one MAC is detected to be invalid, so that each second path selector is connected with one valid MAC, and the MACs connected by different second path selectors are different.

[0018] Further, the chip further comprises:

[0019] N serial interface modules, the output terminal of one serial interface module is connected with the input terminal of one first path selector, and the input terminals of the first to the Nth serial interface modules are connected with the first to the Nth MAC modules respectively;

[0020] The two input ends of the first first-path selector are connected with the first MAC module and the second MAC module respectively, and the two input ends of the first first-path selector are connected with the first serial interface module and the second serial interface module respectively.

[0021] The two input ends of the Nth first-path selector are connected with the Nth MAC module and the (N-1)th MAC module respectively, and the two input ends of the Nth first-path selector are connected with the Nth serial interface module and the (N-1)th serial interface module respectively.

[0022] The three input ends of the mth first-path selector are connected with the (m-1)th MAC module, the mth MAC module and the (m+1)th MAC module respectively, and the three input ends of the mth first-path selector are connected with the (m-1)th serial interface module, the mth serial interface module and the (m+1)th serial interface module respectively.

[0023] Further, the core module comprises a data processing module.

[0024] The chip further comprises:

[0025] A cache module is connected with the N core modules respectively and used for caching data, wherein the cache module comprises a preset memory bank corresponding to the capacity of the cache module and a redundant memory bank; the redundant memory bank is used for replacing the failed preset memory bank to perform the caching function when one preset memory bank fails.

[0026] Further, the chip further comprises:

[0027] A mapping module is connected with the N core modules respectively and used for mapping the physical addresses of the N-1 non-failed core modules into N-1 preset logical addresses in sequence when one core module is detected to fail; the preset logical addresses are used for providing the configuration of the upper-layer software.

[0028] In a second aspect, the application provides a chip control method applied to the chip in the one or more technical solutions, and the method comprises the following steps:

[0029] Detecting whether the N core modules in the chip fail; the N is a positive integer greater than 2;

[0030] If one core module is detected to fail, the first to the (N-1)th MAC modules in the chip are controlled to be connected with one valid core module respectively, and the core modules connected by different MAC modules are different.

[0031] Further, the first to the N-1th MAC modules in the chip are controlled to respectively communicate with one valid core module, and the core modules communicated by different MAC modules are different, comprising:

[0032] If the failed core module is the nth core module, the first to the n-1th MAC modules are controlled to respectively communicate with the first to the n-1th core modules, and the n to the N-1th MAC modules are controlled to respectively communicate with the n+1 to the Nth core modules; the n is a positive integer greater than or equal to 1 and less than or equal to N.

[0033] Further, the method further comprises:

[0034] Detecting whether the MAC in the MAC module is failed; each of the MAC modules comprises j second path selectors and j+1 MACs; the j is a positive integer greater than 2;

[0035] If all the MACs are detected to be normal, the first to the jth second path selectors are controlled to respectively communicate with the first to the jth MACs.

[0036] If the kth MAC is detected to be failed, the first to the k-1th second path selectors are controlled to respectively communicate with the first to the k-1th MACs, and the k to the jth second path selectors are controlled to respectively communicate with the k+1 to the j+1 MACs; the k is a positive integer greater than or equal to 1 and less than or equal to j.

[0037] Further, the method further comprises:

[0038] Detecting whether the memory bank in the cache module of the chip is failed; the memory bank in the cache module comprises a preset memory bank corresponding to the capacity of the cache module and a redundant memory bank; the redundant memory bank is used to replace the failed preset memory bank to perform the cache function when one preset memory bank is failed;

[0039] If at least one memory bank is detected to be failed, the failed memory bank is skipped, and the address pointers of the unfailed memory banks are rearranged for data caching.

[0040] Further, the method further comprises:

[0041] If one of the core modules is detected to be failed, the physical addresses of the N-1 unfailed core modules are sequentially mapped to N-1 preset logical addresses; the preset logical addresses are used to be provided to the upper-layer software for configuration.

[0042] In a third aspect, the present application provides an electronic device, comprising: a processor and a memory for storing a computer program capable of running on the processor;

[0043] The processor executes the computer program, and executes the steps of the chip control method in the one or more technical solutions.

[0044] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer executable instructions; the computer executable instructions are executed by a processor, and can implement the chip control method in the one or more technical solutions.

[0045] The chip provided by the present application comprises N core modules, N first path selectors, a first path control module and N media access controller (MAC) modules; N is a positive integer greater than 2; the first first path selector and the Nth first path selector each have two input ends; the second to the (N-1)th first path selectors each have three input ends; the two input ends of the first first path selector are connected with the first MAC module and the second MAC module respectively; the two input ends of the Nth first path selector are connected with the Nth MAC module and the (N-1)th MAC module respectively; the three input ends of the mth first path selector are connected with the (m-1)th MAC module, the mth MAC module and the (m+1)th MAC module respectively; m is a positive integer greater than or equal to 2 and less than or equal to N-1; the first path control module is connected with the N first path selectors respectively, and is used for controlling the switching state of the first path selector when one core module is detected to be invalid, so that the first to the (N-1)th MAC modules are connected with one valid core module respectively, and the core modules connected by different MAC modules are different. In this way, the first path selector of each chip core module can be connected with the corresponding MAC module and the MAC module corresponding to the adjacent chip core module. Based on this, in the case that one core module is invalid, the first path control module can control other MAC modules except the last MAC module to be connected with the valid core module, so that the chip can be used as a chip with a lower level specification and performance compared with the all good (AG) state, thereby inhibiting the chip with one invalid core module from being marked as a defective product and being unable to be used, and further improving the yield of the chip. In addition, it can be ensured that the MAC module stopped working in the chip is the last MAC module no matter which core module is invalid. In this way, the difficulty of internal control and coding of the chip can be greatly reduced, and the management of the modules in the chip is facilitated. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 A structural schematic diagram of the chip provided by the embodiment of the present application is shown in the figure;

[0047] Figure 2 A structural schematic diagram of the chip provided by the embodiment of the present application is shown in the figure;

[0048] Figure 3 A structure schematic diagram of a chip provided for an embodiment of the present application is shown in FIG. 1.

[0049] Figure 4 A structure schematic diagram of a MAC module provided for an embodiment of the present application is shown in FIG. 2.

[0050] Figure 5 A structure schematic diagram of a MAC module provided for an embodiment of the present application is shown in FIG. 3.

[0051] Figure 6 A structure schematic diagram of a chip provided for an embodiment of the present application is shown in FIG. 4.

[0052] Figure 7 A structure schematic diagram of a chip provided for an embodiment of the present application is shown in FIG. 5.

[0053] Figure 8 A mapping schematic diagram of a cache module memory bank provided for an embodiment of the present application is shown in FIG. 6.

[0054] Figure 9 A mapping schematic diagram of a cache module memory bank provided for an embodiment of the present application is shown in FIG. 7.

[0055] Figure 10 A flow schematic diagram of a chip control method provided for an embodiment of the present application is shown in FIG. 8.

[0056] Figure 11 A flow schematic diagram of a chip test method provided for an embodiment of the present application is shown in FIG. 9. DETAILED DESCRIPTION

[0057] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the present application in conjunction with the accompanying drawings, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0058] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict.

[0059] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to be limiting of this application.

[0061] As shown in Figure 1 Embodiments of the present application provide a chip, comprising: N core modules, N first path selectors, a first path control module, and N media access controllers (MAC) modules; N is a positive integer greater than 2; wherein an output terminal of one of the first path selectors is connected to one of the core modules, and the core modules connected by different first path selectors are different;

[0062] The first and the Nth first path selectors each have two input terminals; the second to the (N-1)th first path selectors each have three input terminals;

[0063] The two input terminals of the first first path selector are respectively connected to the first and the second MAC modules; the two input terminals of the Nth first path selector are respectively connected to the Nth and the (N-1)th MAC modules;

[0064] The three input terminals of the mth first path selector are respectively connected to the (m-1)th, the mth and the (m+1)th MAC modules; m is a positive integer greater than or equal to 2 and less than or equal to N-1;

[0065] The first path control module is connected to the N first path selectors respectively, and is configured to, when detecting that one of the core modules is invalid, control the switching state of the first path selectors, so that the first to the (N-1)th MAC modules are respectively connected to a valid core module, and the core modules connected by different MAC modules are different.

[0066] Here, the chip can include N core modules (slices): core module #0, core module #1, …, and core module # (N-1), N being a positive integer greater than 2, for example, N can be 8.

[0067] The core module can be a module in the chip for performing core functions such as processing and forwarding of data. The structure and the functions that can be implemented of each core module can be consistent, for example, each core module can include a packet processing engine (PP) for packet forwarding and editing, and two datapath engines (DP) for processing transmission of data. The N core modules are used to collectively implement the bandwidth processing capability of the chip.

[0068] Exemplarily, each core module can support a bandwidth processing capability of 3.2 Tbps, and when N is 8, the whole chip supports a bandwidth processing capability of 8*3.2 Tbps = 25.6 Tbps. Correspondingly, the failure of the core module can include the failure of a PP in the core module, the failure of at least one DP, or the failure of a storage module, etc.

[0069] In the embodiment of the application, the first path selector can be a multiplexer (MUX) for selecting a path in the connected at least one path for transmission. The input end of the first path selector can be directly connected to the MAC module, or can be connected to the MAC module through the serial interface module to improve the data transmission efficiency.

[0070] As shown in Figure 2 each core module is connected to a corresponding first path selector, core module #0 is connected to first path selector #0, core module #1 is connected to first path selector #1, and so on. The media access controller (MAC) module can be a module for data transmission with the core module. For example, each core module is connected to a corresponding MAC module through the first path selector. Exemplarily, 8*400G represents that the capacity of the corresponding MAC module is 8*400G, and the MAC module can be an 8*400G MAC.

[0071] In one embodiment, the first path control module can be used to save the path selection logic of the first path selector. The path selection logic can be used to control the first path selector to select a path for data transmission. When none of the N core modules in the chip fails, the first path control module controls each first path selector to be connected to the corresponding MAC module.

[0072] Exemplarily, when N is 8, the first path selector #0 is connected to the first 8*400G MAC module, the first path selector #1 is connected to the second 8*400G MAC module, and so on, and the first path selector #7 is connected to the eighth 8*400G MAC module.

[0073] In another embodiment, when one core module is failed, the first path control module is configured to re-adjust the connection state of each MAC module and each first path selector, so that the first to the N-1th MAC modules are connected to a non-failed core module, and the core modules connected by different MAC modules are different. In this way, the performance and specifications of the chip can be degraded. For example, when N is 8, the bandwidth processing capacity of the chip can be 8*3.2Tbps=25.6Tbps when all the 8 core modules are normal. When one core module is failed, the chip will not be abandoned for use as a defective product, but the bandwidth processing capacity can be reduced to 7*3.2Tbps=22.4Tbps, and the chip can be used as a lower performance chip, thereby effectively improving the availability of the chip and increasing the yield of the chip.

[0074] In addition, based on the re-setting of the connection state of the MAC module and the first path selector, the first to the N-1th MAC modules are always connected to the effective core module, and the Nth MAC module is in an idle state. For example, when the nth core module is failed, the n is a positive integer greater than or equal to 1 and less than or equal to N, the first to the n-1th MAC modules remain the original connection state, i.e., still connected to the first to the n-1th first path selector, and the n to the N-1th MAC modules are connected to the n+1 to the Nth first path selector in turn. For example, as shown in Figure 3 When the third core module, i.e., the core module #2, is failed, the core module #0 and the core module #1 are still connected to the corresponding MAC module, the core module #2 is failed and stopped to be used, the core module #3 is connected to the MAC module originally corresponding to the core module #2, the core module #4 is connected to the MAC module originally corresponding to the core module #3, and so on, and the core module #7 is connected to the MAC module originally corresponding to the core module #6.

[0075] In this way, on the basis of improving the yield of the chip, a flexible connection mode between the MAC module and the core module is also realized, and when one core module is failed, all the MAC modules can be connected to the effective core module based on the flexible adjustment of the path selection. Based on this, no matter which core module in the chip is failed, the MAC module in the idle state can be ensured to be a damaged MAC module or a useless MAC module, thereby reducing the difficulty of coding and control in the internal configuration of the chip and the configuration interaction with the upper software, and improving the efficiency of data interaction.

[0076] For example, when reporting available MAC flags to upper-layer software, if a core module failure is detected, there is no need to separately determine the core module location and corresponding MAC flag; it is sufficient to directly determine that the address corresponding to the last MAC module is unavailable. Furthermore, the above technical effects can be achieved based on the interconnection between adjacent core modules and their corresponding MAC modules, eliminating the need for full interconnection of all core modules and suppressing the high technological difficulty in top-level layout and wiring caused by signal lines running across core modules.

[0077] In some embodiments, a MAC module includes: j second path selectors, a second path control module, and j+1 MACs; where j is a positive integer greater than 2; wherein the output of the second path selector is connected to the input of the first path selector;

[0078] A second path selector has two input terminals, and the two input terminals of the kth second path selector are connected to the kth and (k+1)th MACs, respectively; wherein, k is a positive integer greater than or equal to 1 and less than or equal to j.

[0079] The second path control module is connected to j second path selectors respectively, and is used to control the switching state of the second path selectors when a MAC failure is detected, so that each second path selector is connected to a valid MAC, and the MAC connected to different second path selectors is different.

[0080] In this embodiment of the invention, the second path selector can be the same as the first path selector, such as a multiplexer (MUX). The second path control module is used to control the switching state of the second path selector to control its path selection. The second path control module can be integrated with the first path control module into one module, or it can be integrated into a control module. Each MAC module contains j preset MACs corresponding to the MAC module capacity and 1 redundant MAC. These j+1 MACs are arranged in order, with adjacent MACs serving as backups for each other, and are connected to the input terminal of the first path selector for path selection.

[0081] For example, when the capacity of each MAC module is 8×400G, the MAC module can contain 8 preset MACs and 1 redundant MAC, that is, a total of 9 MACs. The MAC module contains j=8 second path selectors, and each second path selector is connected to two adjacent MACs respectively.

[0082] In one embodiment, taking the first five 400G MACs in the MAC module as an example, such as... Figure 4As shown, the second path selector #0 connects 400G#0 and 400G#1, the second path selector #1 connects 400G#1 and 400G#2, and so on. When all the MACs are working normally, the second path control module can control each second path selector to be connected with the earlier MAC among the two MACs connected by the second path selector, i.e., the kth second path selector is connected with the kth MAC, for example, the second path selector #0 is connected with 400G#0.

[0083] When one MAC is detected to be invalid, the second path control module controls each second path selector to be connected with a valid MAC, and the MACs connected by different second path selectors are different. For example, when the kth MAC is invalid, the second path control module is configured to control the 1st to (k-1)th second path selectors to be connected with the 1st to (k-1)th MACs respectively, and control the kth to jth second path selectors to be connected with the (k+1)th to (j+1)th MACs respectively. k is a positive integer greater than or equal to 1 and less than or equal to j.

[0084] For example, as shown in FIG. 2, when the 2nd MAC, i.e., 400G#1, is invalid, the second path selector #0 still remains connected with 400G#0, the second path selector #1 is changed to be connected with 400G#2, the second path selector #2 is changed to be connected with 400G#3, and so on. Figure 5

[0085] In this way, based on the design of one redundant MAC and in combination with a certain number of second path selectors, the fault tolerance of the MAC module can be greatly improved, and the normal operation of the MAC module can be ensured in the case of one MAC being invalid, so as to ensure the stability of the chip. On this basis, based on the design that the adjacent MACs are backup for each other, the full interconnection structure between multiple MACs is not needed, the AG state of the chip can be maintained in the case of one MAC being invalid, the internal wiring complexity and manufacturing process difficulty of the chip are reduced, and the yield of the chip is improved.

[0086] In some embodiments, the chip further comprises:

[0087] N serial interface modules, an output end of a serial interface module is connected with an input end of a first path selector, and input ends of the 1st to Nth serial interface modules are connected with 1st to Nth MAC modules respectively;

[0088] two input ends of the 1st first path selector are connected with the 1st MAC module and the 2nd MAC module respectively, which comprises that two input ends of the 1st first path selector are connected with the 1st serial interface module and the 2nd serial interface module respectively;

[0089] ​The two input ends of the Nth first path selector are connected with the Nth MAC module and the N-1th MAC module respectively, and the two input ends of the Nth first path selector are connected with the Nth serial interface module and the N-1th serial interface module respectively.

[0090] The three input ends of the mth first path selector are connected with the m-1th MAC module, the mth MAC module and the m+1th MAC module respectively, and the three input ends of the mth first path selector are connected with the m-1th serial interface module, the mth serial interface module and the m+1th serial interface module respectively.

[0091] In the embodiment of the application, the first path selector can be connected with the MAC module through the serial interface module, the input end of the serial interface module is connected with the MAC module, and the output end of the serial interface module is connected with the first path selector. Here, the serial interface module can contain at least one serial interface, for example, the serial interface can be a serial interface (Serial and de-serail, serdes) composed of a serializer and a deserializer. The capacity of the serial interface module matches the capacity of the corresponding MAC module, for example, when the MAC module is 8x400G, the capacity of the serial interface module is also 8x400G. Exemplarily, the 8x400G serial interface module can contain 4 2x400G serial interfaces, each of which is connected with two 400G MACs.

[0092] In one embodiment, the 8x400G serial interface module can contain 4 2x400G serial interface serdes, each of which is connected with two second path selectors, so as to realize that each serial interface is connected with two 400G MACs.

[0093] In another embodiment, as shown in Figure 6 , the chip contains 32 2x400G serial interfaces, i.e., the total capacity is 64x400G. Every 4 serial interfaces form an 8x400G serial interface module. In this way, every 4 serial interfaces are connected with an 8x400G MAC module and are connected with the first path selector corresponding to the core module. Exemplarily, when N is 8, the serial interface module composed of the 4 2x400G serial interfaces in the middle of the upper edge of the chip is the serial interface module corresponding to the core module #7. Therefore, in the case that any core module fails or any interface in the above 4 serial interfaces fails, as shown in Figure 7 , the finally idle are the above 4 serial interfaces and the MAC modules connected therewith.

[0094] Thus, the connection between the core module and the MAC module is established based on the serial interface module, so that the data transmission rate and stability can be greatly improved.

[0095] In some embodiments, the core module comprises a data processing module.

[0096] The chip further comprises:

[0097] The cache module is connected with the N data processing modules respectively and is used for caching data; wherein, the cache module comprises a preset storage bank corresponding to the capacity of the cache module and a redundant storage bank; the redundant storage bank is used for replacing the failed preset storage bank to perform the caching function when one preset storage bank is failed.

[0098] In the embodiments of the application, the data processing module can be a packet processing engine in the core module, or can be other modules used for processing data. The cache module in the chip can be a packet buffer, which is used for caching data during the data receiving and processing of the data processing module, so as to improve the data read-write efficiency.

[0099] In one embodiment, a redundant storage bank (Bank) is additionally arranged in the cache module, for example, for a cache module with a capacity of 128 Mbytes, 128 storage banks with a storage space of 1 Mbyte are required under normal circumstances, and at this time, a storage bank with a storage space of 1 Mbyte is additionally arranged as a redundant storage bank. As long as any one preset storage bank is failed, the cache module can still be considered to be intact under the supplement of the redundant storage bank, and the chip is still in a full-good state.

[0100] Exemplarily, the cache module can further comprise a write address remapping circuit and a read address remapping circuit, which are used for re-establishing the write address mapping and the read address mapping when detecting that one storage bank is failed. Figure 8 As shown, re-establishing the write address mapping and the read address mapping can comprise replacing the failed storage bank with the redundant storage bank to re-establish the write address remapping and the read address remapping, or excluding the address of the failed storage bank and sequentially moving the address of the storage bank after the failed storage bank to re-establish the write address mapping and the read address mapping. For example, the cache module comprises 128 preset storage banks Bank#0 to Bank#127 and one redundant storage bank Bank#128, if Bank#2 is failed, Bank#128 is used to replace Bank#2 to re-establish the write address mapping and the read address mapping, and the mapping relationship of other storage banks is unchanged. Thus, the chip is still in a full-good state when only one storage bank is failed.

[0101] In another embodiment, as shown in Figure 9As shown, in the case of detecting that one or more memory banks are invalid, the cache module can also be used to write the remaining non-failed memory bank address pointers into the free pointer pool. Among them, the address pointer of the memory bank is represented by 0×FF, for example, the address pointer of the memory bank Bank#0 is 0×00, the address pointer of the memory bank Bank#1 is 0×01, and so on.

[0102] In establishing the write address mapping and the read address mapping, and in the packet cache read and write, the memory bank address pointer in the free pointer pool is used as the available address space.

[0103] Optionally, the cache module can also detect the invalidity of the cache module memory bank based on a certain detection period, and update the free pointer pool after detection according to the detection period, so as to ensure that the free pointer pool stores valid memory bank address pointers. In this way, when one memory bank is invalid, the chip can still be in the AG state based on the supplement of the redundant memory bank. When multiple memory banks are invalid, based on the elimination of the invalid memory bank address pointer, the cache module can continue to perform the cache function based on the remaining address space, so that the chip is in the Partial Good (PG) state, and will not be identified as a defective product, thereby realizing the AG design and PG design of the chip and improving the yield of the finished product.

[0104] In some embodiments, the chip further comprises:

[0105] A mapping module is connected with the N core modules respectively, and is used to map the physical addresses of N-1 non-failed core modules into N-1 preset logical addresses in sequence when one of the core modules is detected to be invalid. The preset logical addresses are used to provide configuration information to the upper-layer software.

[0106] In the embodiment of the application, when one core module is invalid, the chip is in the Partial Good (PG) state. In order to reduce the difficulty of the interaction between the chip internal configuration code and the upper-layer software configuration information, the mapping module is used to map the physical addresses of the N-1 non-failed core modules into N-1 preset logical addresses.

[0107] In one embodiment, when N=8, for example, in the case of invalid core module #2, the mapping module is used to map the physical addresses of the 7 non-failed core modules into 7 preset logical addresses, that is, the physical address of the core module #0 is mapped into the logical address #0, the physical address of the core module #1 is mapped into the logical address #1, the physical address of the core module #3 is mapped into the logical address #2, and so on, and the physical address of the core module #7 is mapped into the logical address #6.

[0108] In another embodiment, when N=8, for example, in the case of core module #0 failure, the mapping module is used to map the physical address of core module #1 to logical address #0, the logical address of core module #2 to logical address #1, and so on, to the physical address of core module #7 to logical address #6.

[0109] Thus, regardless of which core module within the chip fails, after logical address mapping by the mapping module, the available logical addresses provided to the upper-layer software are all from logical address #0 to logical address #6. This shields the upper-layer software from underlying physical information, eliminating the need for the upper-layer software to know the specific physical address of the failed core module and to encode and configure it accordingly. Based on this, for a PG chip with a failed core module, the upper-layer software only needs to encode based on the preset logical address during the configuration instruction process, without needing to adjust the encoding according to the specific physical address of the failed core module, greatly improving the efficiency of software configuration and information exchange.

[0110] like Figure 10 As shown, this embodiment of the invention provides a chip control method applied to the chip described in one or more of the foregoing technical solutions. The method includes:

[0111] S110: Detect whether N core modules in the chip have failed; where N is a positive integer greater than 2;

[0112] S120: If a failure of one of the core modules is detected, the first to the (N-1)th MAC modules in the chip are controlled to connect to a valid core module respectively, and the core modules connected to different MAC modules are different.

[0113] In this embodiment of the invention, controlling the 1st to N-1th MAC modules in the chip to connect to a valid core module can include: controlling the 1st to N-1th MAC modules in the chip to connect to a first path selector corresponding to a valid core module. When a core module fails, it is ensured that the 1st to N-1th MAC modules are all connected to a valid core module, and different MAC modules are connected to different core modules. In this way, the performance and specifications of the chip can be downgraded. For example, when N is 8, the bandwidth processing capability of the chip can be 8 × 3.2 Tbps = 25.6 Tbps when all 8 core modules are normal. When a core module fails, the chip will not be considered a defective product and abandoned for use. Instead, based on classification (binning) operations, the bandwidth processing capability can be reduced to 7 × 3.2 Tbps = 22.4 Tbps, and it can be used as a lower-performance chip in low-bandwidth applications, thereby effectively improving the chip's availability and indirectly improving the chip's yield.

[0114] Thus, when one core module fails, the first N-1 MAC modules can keep communicating with the effective core modules. Regardless of which core module fails in the chip, the last MAC module, i.e., the Nth MAC module, is ensured to be in an idle state, thereby reducing the difficulty of coding and control and improving the efficiency of data interaction in the internal configuration of the chip and the configuration interaction with the upper-layer software. For example, when reporting the available MAC addresses to the upper-layer software, it is not necessary to determine the position of the core module and the corresponding MAC address when detecting that one core module fails, and it is only necessary to directly determine that the address corresponding to the last MAC module is unavailable.

[0115] In some embodiments, the S120 can include:

[0116] If it is detected that one of the core modules fails, and the failed core module is the nth core module, the first to the (n-1)th MAC modules are controlled to communicate with the first to the (n-1)th core modules, respectively, and the (n)th to the (N-1)th MAC modules are controlled to communicate with the (n+1)th to the Nth core modules, respectively; the n is a positive integer greater than or equal to 1 and less than or equal to N.

[0117] In the embodiments of the present application, since the first to the (N-1)th MAC modules always keep communicating with the effective core modules, and one core module fails, the Nth MAC module is in an idle state. For example, when the nth core module fails, the n is a positive integer greater than or equal to 1 and less than or equal to N, the first to the (n-1)th MAC modules keep the original communication state, i.e., still communicate with the first to the (n-1)th core modules, respectively, and the (n)th to the (N-1)th MAC modules are changed to communicate with the (n+1)th to the Nth core modules, respectively. Exemplarily, when the third core module, i.e., core module #2, fails, the core module #0 and the core module #1 still communicate with the corresponding MAC modules, the core module #2 stops being used due to failure, the core module #3 is changed to communicate with the MAC module originally corresponding to the core module #2, the core module #4 is changed to communicate with the MAC module originally corresponding to the core module #3, and so on, and the core module #7 is changed to communicate with the MAC module originally corresponding to the core module #6.

[0118] Thus, based on the flexible adjustment of the communication relationship between the adjacent core modules and the MAC modules, the effect of reducing the specification and performance use of the chip can be achieved without full connection between the core modules, thereby reducing the complexity of internal wiring of the chip.

[0119] In some embodiments, the method further includes:

[0120] detecting whether a MAC in the MAC module fails; each of the MAC modules includes j second path selectors and j+1 MACs; the j is a positive integer greater than 2.

[0121] If it is detected that all the MACs are normal, the first to jth second-path selectors are controlled to connect the first to jth MACs, respectively.

[0122] If it is detected that the kth MAC is invalid, the first to (k-1)th second-path selectors are controlled to connect the first to (k-1)th MACs, respectively, and the kth to jth second-path selectors are controlled to connect the (k+1)th to (j+1)th MACs, respectively; the k is a positive integer greater than or equal to 1 and less than or equal to j.

[0123] In the embodiment of the application, taking the first five 400G MACs in the MAC module as an example, the second-path selector #0 connects 400G #0 and 400G #1, the second-path selector #1 connects 400G #1 and 400G #2, and so on. When all the MACs are normal, each second-path selector is connected to the earlier MAC of the two MACs, i.e., the kth second-path selector is connected to the kth MAC, for example, the second-path selector #0 is connected to 400G #0.

[0124] When one MAC is detected to be invalid, each second-path selector is connected to a valid MAC, and the MACs connected by different second-path selectors are different. For example, when the kth MAC is invalid, the first to (k-1)th second-path selectors are controlled to connect the first to (k-1)th MACs, respectively, and the kth to jth second-path selectors are controlled to connect the (k+1)th to (j+1)th MACs, respectively. The k is a positive integer greater than or equal to 1 and less than or equal to j. For example, when the second MAC, i.e., 400G #1, is invalid, the second-path selector #0 still remains connected to 400G #0, the second-path selector #1 is changed to be connected to 400G #2, the second-path selector #2 is changed to be connected to 400G #3, and so on.

[0125] In this way, based on the design of one redundant MAC, combined with a certain number of second-path selectors, the fault tolerance of the MAC module can be greatly improved, and the normal operation of the MAC module can be ensured in the case of one MAC being invalid, so as to ensure the stability of the chip and improve the yield of the chip.

[0126] In some embodiments, the method further comprises:

[0127] detecting whether a memory bank in a cache module of the chip is invalid; the memory banks in the cache module include a preset number of memory banks corresponding to the capacity of the cache module and one redundant memory bank; the redundant memory bank is used to replace an invalid preset memory bank to perform a cache function when the preset memory bank is invalid;

[0128] If at least one memory bank is detected to be failed, the failed memory bank is skipped, and the memory bank address pointers of the non-failed memory banks are rearranged for data caching.

[0129] In the embodiments of the present application, in the case that one memory bank is detected to be failed, the redundant memory bank can be used to replace the failed memory bank for data caching. In the case that one or more memory banks are detected to be failed, the memory bank address pointers of the remaining non-failed memory banks can be written into the free pointer pool. In the establishment of the write address mapping and the read address mapping, and in the packet caching read and write, the memory bank address pointers in the free pointer pool are used as the available address space. Optionally, the failure of the memory banks in the caching module can also be detected based on a certain detection period, and the free pointer pool is updated after the detection according to the detection period, so as to ensure that the memory bank address pointers in the free pointer pool are valid. In this way, in the case that one memory bank is failed, the chip can still be in the AG state based on the supplement of the redundant memory bank. In the case that multiple memory banks are failed, based on the elimination of the failed memory bank address pointers, the caching module can continue to perform the caching function based on the remaining address space, so that the chip is in the PG state, and the chip will not be identified as a defective product, thereby realizing the AG design and the PG design of the chip, and improving the yield of the finished product of the chip.

[0130] In some embodiments, the method further comprises:

[0131] If one of the core modules is detected to be failed, the physical addresses of N-1 non-failed chip core modules are sequentially mapped to N-1 preset logical addresses; the preset logical addresses are used to provide configuration to the upper layer software.

[0132] In the embodiments of the present application, in the case that one core module is failed, the chip is in the PG state. In order to reduce the difficulty of the interaction between the chip internal configuration code and the upper layer software configuration information, the physical addresses of the N-1 non-failed core modules are mapped to the preset N-1 logical addresses.

[0133] In one embodiment, when N=8, for example, in the case that core module #2 is failed, the mapping module is used to map the physical addresses of the 7 non-failed core modules to 7 preset logical addresses, i.e., the physical address of core module #0 is mapped to logical address #0, the physical address of core module #1 is mapped to logical address #1, the physical address of core module #3 is mapped to logical address #2, and the physical address of core module #7 is mapped to logical address #6.

[0134] In another embodiment, when N=8, for example, in the case of core module #0 failure, the mapping module is configured to map the physical address of core module #1 to logical address #0, the logical address of core module #2 to logical address #1, and so on, and the physical address of core module #7 to logical address #6.

[0135] In one embodiment, all module test results and Bin information need to be written into the eFuse of the chip for reading during the chip startup process. The chip can decode these information through a state machine or an embedded CPU, and make corresponding configurations to the internal path selectors (including the first path selector and the second path selector, etc.).

[0136] In yet another embodiment, for the internal global forwarding table of the chip, as long as there is a table entry storing core module information, a conversion logic of the above-mentioned physical address and preset logical address is added behind the table entry. The configuration of these conversion logics is based on the information recorded in the eFuse by the internal state machine or embedded CPU during the chip startup, including recording the failure encoding information of different core modules and modules according to the test results of the Design For Test (DFT), and then configuring the mapping table of the non-failed core module.

[0137] In this way, regardless of which core module fails in the chip, after the preset logical address is mapped to the core module physical address, the available logical address provided to the upper layer software is logical address #0 to logical address #6, thereby shielding the underlying physical information from the upper layer software, and the upper layer software does not need to know the specific physical address of the failed core module and make targeted coding configurations. Based on this, for a PG chip with a failed core module, the upper layer software only needs to code based on the preset logical address during the configuration instruction process, without the need to specifically adjust the coding according to the physical address of the failed core module, thereby greatly improving the efficiency of software configuration and information interaction.

[0138] In another embodiment, as shown in FIG. 6, before testing the core module effectiveness, module effectiveness, etc. of the chip, the feedthrough of the functional logic periphery in the chip and the logic of each path selector can be tested first. If there is a failure, the test can be stopped immediately to confirm that the chip is a bad die. After confirming that the feedthrough and the path selector are both not failed, the logic function of the PP and DP in each core module and the storage module are tested to detect the effectiveness of the core module; the MAC module logic and effectiveness are tested; the effectiveness of the serial interface serdes is tested; and the effectiveness of the storage bank in the cache module is tested. Finally, according to the test results, the chip is divided into Bins, as shown in the following table: Figure 11 ​

[0139]

[0140] Note 1: Specifically refers to the top layer layout of the chip 4 2x400G serdes on the upper edge;

[0141] Note 2: Specifically refers to the top layer layout of the chip 8 2x400G serdes on the upper edge.

[0142] Exemplarily, if it is detected in the detection process that there is a bad point in the lead or path selector, or the number of failed core modules is greater than 1, or the number of failed memory banks in the cache module is greater than 2, or the number of failed MACs is greater than 1, or the number of failed serial interfaces is greater than 4, the chip can be considered as a bad chip, and the record is made.

[0143] The following provides a specific example in combination with any of the above embodiments:

[0144] The technical scheme of the embodiment of the application contains five parts, the first part is to describe how to make a redundant design for 400G MAC and message cache; the second part is to make a partial good (PG) design for message cache, message processing engine and data channel engine, and serdes; the third part is to describe the test process and key points; the fourth part is to describe how to burn the test results in the eFuse of the chip and how to use the test results when the chip starts; and the fifth part is to describe how to design a global mapping table in the chip to shield the bottom layer physical failure information for the upper layer software.

[0145] 1. Taking the design of four 400G MACs as an example, in order to increase the redundancy, one more 400G MAC is designed. Different from the prior art, the five MACs are not in a full interconnection structure, but in a structure in which each two MACs are backup for each other, and this way can be extended to multiple 400G MACs, such as N 400G MACs. As long as one more 400G MAC is designed, a N+1 structure is formed, so that any 400G MAC failure can be found during the test, and the remaining N MACs can still be considered as good.

[0146] As for the core message cache module, a similar idea is also adopted, for example, the core message cache only needs 128 memory banks (Banks), each Bank contains 1 megabyte of storage unit, and the total message cache is 128 megabytes. One more Bank is designed on the design, so that as long as any Bank fails, the entire message cache can still be considered as good. Therefore, a write address remapping circuit and a read address remapping circuit need to be designed to skip the address range of the failed Bank.

[0147] 2、In one embodiment, there are 8 core modules (Slices) inside a chip, each Slice contains one packet processing engine (PP) and 2 data path engines (DP). All Slices are identical in functionality, each Slice supports 3.2Tbps (1T bps = 10^12 bps) bandwidth processing capability, the whole chip supports 25.6Tbps = 8x3.2Tbps bandwidth processing capability. To support PG design, there are only two kinds of multiplexers (MUX), one is 2-input, only used in Slice#0 and Slice#7, the other MUX structure is 3-input, used in the remaining 6 Slices. The benefit of this is that, considering the top layout of the chip, as long as there is a connection between adjacent Slices, the signal line will not cross the Slice.

[0148] For example, if Slice#2 is found to be failed in testing, only the last 8 400G are not connected to any Slice. That is, if a Slice is failed, the performance of the whole chip is reduced from the original 25.6Tbps to 22.4Tbps. In testing, at least two Bins can be divided, one Bin is given to the 25.6Tbps performance chip, and the other Bin is assigned to the 22.4Tbps chip. Further, the number of failed Slices can be more than 1, so more Bin operations and product series are needed.

[0149] The PG design of serdes is special, because the location of Serdes on the chip corresponds to the solder ball on the package one by one. For example, a chip integrated with 64 400G interfaces, the middle 4 2x400G serdes on the top edge of the chip are directly connected to the MUX input port of Slice#7. Therefore, as long as a certain Slice inside the chip is failed or any one of the 4 2x400G serdes on the top edge of the chip is failed, the use of the 4 2x400G serdes on the top edge of the chip can be disabled, so as to reduce the maximum supported bandwidth of the chip to 22.4Tbps, that is, to be used and sold as a lower product.

[0150] For the PG design of packet cache, if any Bank is found to be failed when testing the packet cache, then this Bank is skipped and the remaining address space is used. The specific method is to write the valid Bank address pointer in the free pointer pool of the packet cache during initialization, and to exclude the failed Bank address pointer range.

[0151] 3. Since PG design needs to ensure that all feedthroughs and MUXs are intact, when doing DFT testing of the chip, it needs to be divided into two tests: the first test only tests whether the feedthrough and MUX logic of the peripheral logic is intact, and as long as there is any failure in the feedthrough or MUX, the test can be stopped immediately and the bad chip is marked.

[0152] The second test then tests the normal function logic of the chip, including the following main function logic parts:

[0153] 1. The logic and memory contained in PP and DP in each Slice core module.

[0154] 2. The packet buffer of the chip.

[0155] 3. All MAC logic and related memory of the chip.

[0156] 4. The interface Serdes of the chip.

[0157] Finally, according to the test results, the chips are divided into the following Bins:

[0158]

[0159] Note 1: Specifically refers to the 4 2x400G Serdes on the top layout of the chip.

[0160] Note 2: Specifically refers to the 8 2x400G Serdes on the top layout of the chip.

[0161] In addition, it is particularly noted that the screening conditions of Bin #1 include the chips of Bin #0, and the screening conditions of Bin #2 include the chips of Bin #1 and Bin #0. Therefore, the chips that truly belong to Bin #1 are the chips left after the selection of Bin #0 is completed, and the chips that truly belong to Bin #2 are the chips left after the selection of Bin #1 and Bin #0 is completed.

[0162] 4. eFuse writing and reading. All module test results and Bin division information need to be written into the eFuse information of the chip for the chip startup process to read, and the chip can decode these test results through a state machine or an embedded CPU, and make corresponding configurations to the internal MUX.

[0163] The encoding in the eFuse is shown in the following table:

[0164]

[0165]

[0166] 5. The encoding of Slice core module in partially good chip needs special processing, because the message needs to be forwarded to specific port in the chip, and the software needs to be shielded from the invalid Slice core module.

[0167] For example, there are 8 Slices in the chip, Slice #2 is invalid (the PP or the logic or storage of two DPs in Slice #2 is invalid), and the remaining 7 Slices are good. However, for the upper software, Slice #0~Slice #6 are always seen as good, and Slice #7 is not used. Therefore, the software does not need to perceive which Slice is invalid when configuring. When the upper software accesses the internal registers or table entries of the chip, and configures the global forwarding table in the chip, Slice #7 is always seen as invalid, and Slice #0~Slice #6 are always seen as good. The same is true for the MAC processing.

[0168] Suppose that the CPU address space of each Slice is 32 bits, and 8 bits are added in front, each bit representing a Slice. In the previous example, suppose that Slice #2 is invalid, as shown in the following table, the software can only perceive that Slice #7 is invalid, and consider that Slice #0~Slice #6 are good.

[0169]

[0170]

[0171] If Slice #0 is invalid, the content of the mapping table will be configured as shown in the following table:

[0172]

[0173] For the internal global forwarding table, as long as there are table entries storing Slice information, a Slice conversion logic must be added behind these table entries. The configuration of these conversion logics is read by the internal state machine or embedded CPU from the eFuse information during the startup of the chip. These information is recorded according to the test results of DFT, and the invalid encoding information of different modules is recorded, and then all the mapping tables of the Slices are configured.

[0174] So, in the MAC, the design of one or several modules is added, the redundancy of the front-end design is increased, the global interconnection line is avoided through the adjacent MUX, and when any MAC fails, the chip can still be considered to be perfect. In the message buffer, the design of adding a Bank increases the redundancy of the front-end design, and when any Bank fails, the chip can still be considered to be perfect. In the design of multiple Slices, when any Slice fails, the chip can still be divided into Bin to reduce the specification and achieve the effect of full utilization. In the message buffer, when the number of failed Banks exceeds 1, the chip can still be divided into Bin to reduce the specification and achieve the effect of full utilization. In the design of multiple Serdes, when any several related and adjacent Serdes fail, the chip can still be divided into Bin to reduce the specification and achieve the effect of full utilization. In the DFT test, it is divided into two tests, the first test is whether the interconnection line and the MUX logic of the chip periphery are perfect, and the second test is the logic function and the memory unit in the chip. If there is any failure in the first test, the test can be stopped immediately, thereby saving the test time. The failure information of some modules in the chip is written into eFuse, and the global MUX is configured through the internal state machine or the embedded CPU. The global mapping table shields the underlying physical information, and the upper software always sees that the first several consecutive Slices are perfect and the last Slice fails, which facilitates software configuration and fault elimination (Debug).

[0175] The embodiment of the present application further provides an electronic device, which comprises a processor and a memory for storing a computer program capable of running on the processor, and when the processor runs the computer program, the steps of the method in the foregoing one or more technical solutions are executed.

[0176] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and when the computer executable instructions are executed by a processor, the method in the foregoing one or more technical solutions can be implemented.

[0177] The computer storage medium provided by the embodiment can be a non-transient storage medium.

[0178] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above described device embodiments are merely exemplary. After the above description of the device embodiments, it will be apparent to those skilled in the art that the unit division is only a logical function division, and there can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling, direct coupling or communication connection between the components can be indirect coupling or communication connection through some interfaces, and can be electrical, mechanical or in other forms.

[0179] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0180] In addition, each functional unit in each embodiment of the present application can be integrated into one processing module, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0181] In some cases, any two of the above technical features can be combined into a new method technical solution without conflict.

[0182] In some cases, any two of the above technical features can be combined into a new device technical solution without conflict.

[0183] Those skilled in the art can understand that all or part of the steps of the above method embodiments can be completed by a program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program is executed to perform steps including the above method embodiments; and the foregoing storage medium includes a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0184] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that, The chip includes: N core modules, N first path selectors, a first path control module, and N media access controller (MAC) modules; where N is a positive integer greater than 2; wherein, the output of one first path selector is connected to one core module, and different first path selectors are connected to different core modules; The first first path selector and the Nth first path selector each have two input terminals; the second to the (N-1)th first path selectors each have three input terminals; The two input terminals of the first first path selector are connected to the first MAC module and the second MAC module, respectively; the two input terminals of the Nth first path selector are connected to the Nth MAC module and the (N-1)th MAC module, respectively. The three input terminals of the m-th first path selector are respectively connected to the (m-1)-th MAC module, the m-th MAC module, and the (m+1)-th MAC module; where m is a positive integer greater than or equal to 2 and less than or equal to N-1. The first path control module is connected to N first path selectors respectively, and is used to control the switching state of the first path selectors when a failure of one of the core modules is detected, so that the 1st to the (N-1)th MAC modules are connected to a valid core module respectively, and the core modules connected to different MAC modules are different.

2. The chip according to claim 1, characterized in that, One of the MAC modules includes: j second path selectors, a second path control module, and j+1 MACs; where j is a positive integer greater than 2; wherein the output of the second path selector is connected to the input of the first path selector; A second path selector has two input terminals, and the two input terminals of the kth second path selector are connected to the kth and (k+1)th MACs, respectively; wherein, k is a positive integer greater than or equal to 1 and less than or equal to j; The second path control module is connected to j second path selectors respectively, and is used to control the switching state of the second path selectors when a MAC failure is detected, so that each second path selector is connected to a valid MAC, and the MAC connected to different second path selectors is different.

3. The chip according to claim 1, characterized in that, The chip also includes: N serial interface modules, the output of one of the serial interface modules is connected to the input of one of the first path selectors, and the inputs of the first to Nth serial interface modules are respectively connected to the first to Nth MAC modules; The two input terminals of the first first path selector are respectively connected to the first MAC module and the second MAC module, including: the two input terminals of the first first path selector are respectively connected to the first serial interface module and the second serial interface module; The two input terminals of the Nth first path selector are respectively connected to the Nth MAC module and the (N-1)th MAC module, including: the two input terminals of the Nth first path selector are respectively connected to the Nth serial interface module and the (N-1)th serial interface module; The three input terminals of the m-th first path selector are respectively connected to the (m-1)-th MAC module, the m-th MAC module, and the (m+1)-th MAC module, including: the three input terminals of the m-th first path selector are respectively connected to the (m-1)-th serial interface module, the m-th serial interface module, and the (m+1)-th serial interface module.

4. The chip according to claim 1, characterized in that, The core module includes: a data processing module; The chip also includes: A caching module is connected to N of the data processing modules and is used to cache data. The caching module includes a number of preset storage units corresponding to the capacity of the caching module and a redundant storage unit. The redundant storage unit is used to replace the failed preset storage unit to perform the caching function when a preset storage unit fails.

5. The chip according to claim 1, characterized in that, The chip also includes: The mapping module is connected to each of the N core modules and is used to map the physical addresses of the N-1 non-failed core modules to N-1 preset logical addresses in sequence when a failure of one of the core modules is detected; the preset logical addresses are used to provide configuration for the upper-layer software.

6. A chip control method, applied to the chip according to any one of claims 1 to 5, characterized in that, The method includes: The system detects whether N core modules in the chip have failed; where N is a positive integer greater than 2. If a failure of one of the core modules is detected, the first to the (N-1)th MAC modules in the chip are controlled to connect to a valid core module, and the core modules connected to different MAC modules are different.

7. The method according to claim 6, characterized in that, The first to N-1 MAC modules in the control chip are each connected to a valid core module, and the core modules connected to different MAC modules are different, including: If the failed core module is the nth core module, then control the 1st to the (n-1st)th MAC modules to connect with the 1st to the (n-1st)th core modules respectively, and control the nth to the (N-1st)th MAC modules to connect with the (n+1th)th to the Nth core modules respectively; where n is a positive integer greater than or equal to 1 and less than or equal to N.

8. The method according to claim 6, characterized in that, The method further includes: The MAC module is used to detect whether the MAC is invalid; each MAC module includes j second path selectors and j+1 MACs; where j is a positive integer greater than 2. If all MAC addresses are detected to be normal, then control the first to jth second path selectors to connect to the first to jth MAC addresses respectively; If the kth MAC fails, the first to the (k-1)th second path selectors are controlled to connect to the first to the (k-1)th MAC respectively, and the k to the jth second path selectors are controlled to connect to the (k+1)th to the (j+1)th MAC respectively; where k is a positive integer greater than or equal to 1 and less than or equal to j.

9. The method according to claim 6, characterized in that, The method further includes: The system detects whether the memory in the cache module of the chip has failed; the memory in the cache module includes: a preset number of memory corresponding to the capacity of the cache module and a redundant memory; the redundant memory is used to replace the failed preset memory to perform the cache function when a preset memory fails. If at least one memory bank fails, the failed memory bank is skipped, and the address pointers of the compliant memory banks are rearranged for data caching.

10. The method according to claim 6, characterized in that, The method further includes: If a failure of one of the core modules is detected, the physical addresses of the N-1 non-failed core modules are sequentially mapped to N-1 preset logical addresses; the preset logical addresses are used to provide configuration for upper-layer software.

11. An electronic device, characterized in that, The electronic device includes: a processor and a memory for storing computer programs capable of running on the processor; wherein, When the processor runs the computer program, it performs the steps of the chip control method according to any one of claims 6 to 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions; when executed by a processor, the computer-executable instructions can implement the chip control method as described in any one of claims 6 to 10.

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