Array substrate, manufacturing method thereof, and display device

Abstract

An array substrate, a manufacturing method thereof, and a display device, the array substrate comprising: a base substrate and a plurality of pixel units located thereon, each pixel unit comprising a driving circuit and a light-emitting device, the driving circuit comprising a plurality of thin-film transistors, the plurality of thin-film transistors being arranged in two layers, the plurality of thin-film transistors comprising a target thin-film transistor, the target thin-film transistor being located in a layer away from the base substrate; the light-emitting device comprising: an anode, a light-emitting layer, and a cathode; the array substrate further comprising: a channel blocking layer, arranged in the same layer as the anode, the positive projection area of the active layer of the target thin-film transistor on the base substrate being located within the positive projection area of the channel blocking layer on the base substrate; an edge area of a surface of the channel blocking layer on a side facing away from the target thin-film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin-film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin-film transistor is located.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display device. Background Art

[0002] With the continuous advancement of display technology, consumer demand for higher-quality and thinner displays is increasing. To meet these demands, major manufacturers are adopting OLED (Organic Light Emitting Diode) displays. OLED displays offer significant advantages over LCDs (Liquid Crystal Displays) in contrast, color gamut, and response time, but are limited by resolution. Currently, stacked TFT (thin-film transistor) technology is being used to reduce the pixel unit area in OLED displays, thereby improving their resolution. Stacked TFTs place the TFTs in the driver circuit of an OLED display in two layers. However, the TFTs in the upper layer are susceptible to light exposure, causing threshold voltage shifts and resulting in uneven display. In current stacked TFTs, some TFTs are shielded by SD (source-drain metal) layers. Due to limited space, some TFTs require a channel shielding layer on the same layer as the anode. However, the channel shielding layer is relatively far from the TFT channel, limiting the shielding space. Light can enter from the edges and illuminate the TFT channel, resulting in uneven display. Summary of the Invention

[0003] The embodiments of the present invention provide an array substrate and a manufacturing method thereof, and a display device, for solving the problem in existing OLED display devices that the thin film transistor channel is easily exposed to light due to the long distance between the thin film transistor and the channel shielding layer, resulting in uneven display.

[0004] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising:

[0006] A base substrate and a plurality of pixel units disposed on the base substrate, each pixel unit comprising a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate, the driving circuit comprising a plurality of thin-film transistors disposed in two layers, the plurality of thin-film transistors including a target thin-film transistor, the target thin-film transistor being located in a layer away from the base substrate; the light-emitting device comprising: an anode, a light-emitting layer, and a cathode disposed in a stacked manner;

[0007] The array substrate further comprises: a channel blocking layer, the channel blocking layer being provided on the same layer as the anode, and the orthographic projection area of the active layer of the target thin film transistor on the base substrate being located within the orthographic projection area of the channel blocking layer on the base substrate;

[0008] In which, the edge area of the surface of the side of the channel blocking layer facing away from the target thin film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin film transistor is located.

[0009] Optionally, the active layer of the thin film transistor that is one layer away from the substrate among the plurality of thin film transistors is made of oxide.

[0010] Optionally, an active layer of a thin film transistor close to a layer of the substrate among the plurality of thin film transistors is made of low temperature polycrystalline silicon (LTPS).

[0011] Optionally, an edge area of a surface of the channel blocking layer facing away from the target thin film transistor is a convex arc surface, or the entire area of the surface of the channel blocking layer facing away from the target thin film transistor is a convex arc surface.

[0012] Optionally, a surface of the channel blocking layer facing the target thin film transistor is flat.

[0013] Optionally, a surface of the channel blocking layer facing the target thin film transistor is a convex arc surface.

[0014] Optionally, the array substrate further includes: a second flat layer, the second flat layer being located between the target thin film transistor and the channel blocking layer, the area of the second flat layer on the side surface away from the target thin film transistor where the channel blocking layer is set matches the shape of the side surface of the channel blocking layer facing away from the target thin film transistor.

[0015] Optionally, the array substrate further includes: a second planar layer, the second planar layer being located between the target thin film transistor and the channel blocking layer, and the thickness of the region of the second planar layer where the channel blocking layer is provided is less than the thickness of the region where the anode is provided.

[0016] Optionally, a region of the second planar layer where the channel blocking layer is disposed has a groove, and the channel blocking layer is disposed in the groove.

[0017] Optionally, the thickness of the second planar layer in a region where the channel shielding layer is provided is 0.4-1.0 μm, and the thickness of the second planar layer in a region where the anode is provided is 1.2-1.8 μm.

[0018] In a second aspect, an embodiment of the present invention provides a method for manufacturing an array substrate, comprising:

[0019] providing a substrate;

[0020] A plurality of pixel units and a channel shielding layer are formed on the substrate, each of the pixel units including a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the substrate, the driving circuit including a plurality of thin film transistors arranged in two layers, the plurality of thin film transistors including a target thin film transistor, the target thin film transistor being located on a layer away from the substrate; the light-emitting device including: an anode, a light-emitting layer, and a cathode arranged in a stacked manner;

[0021] The channel blocking layer is provided on the same layer as the anode, and the orthographic projection area of the active layer of the target thin film transistor on the base substrate is located within the orthographic projection area of the channel blocking layer on the base substrate;

[0022] In which, the edge area of the surface of the side of the channel blocking layer facing away from the target thin film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin film transistor is located.

[0023] In a third aspect, an embodiment of the present invention provides a display device comprising the above array substrate.

[0024] In an embodiment of the present invention, for the target thin film transistor in the array substrate, the edge area of the surface of the channel blocking layer on the side facing away from the target thin film transistor is bent, or by shortening the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located, the light shielding effect of the channel blocking layer can be improved while the occupied area of the channel blocking layer remains the same, thereby preventing light from entering the channel of the target thin film transistor from the edge of the channel blocking layer, thereby improving display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0026] Figure 1 Schematic diagram of the structure of an array substrate according to an embodiment of the present invention;

[0027] Figure 2 Schematic diagram of the positional relationship between a channel blocking layer and an active layer of a target thin film transistor according to an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of the positional relationship between a channel blocking layer and an active layer of a target thin film transistor according to another embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the positional relationship between a channel blocking layer and an active layer of a target thin film transistor according to another embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the positional relationship between a channel blocking layer and an active layer of a target thin film transistor according to another embodiment of the present invention;

[0031] Figure 6 is a structural schematic diagram of an array substrate according to another embodiment of the present invention;

[0032] Figure 7 Schematic diagram of the positional relationship between a channel blocking layer and an active layer of a target thin film transistor according to another embodiment of the present invention;

[0033] Figures 8-12 FIG. 4 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] Please refer to Figure 1 , an embodiment of the present invention provides an array substrate, comprising:

[0036] The base substrate 10 is made of any material, for example, it can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as Figure 1 As shown, the base substrate 10 is a flexible substrate, including a first PI (polyimide) layer 11 , a first barrier layer 12 , a second PI layer 13 , a second barrier layer 14 and a first buffer layer 15 .

[0037] A plurality of pixel units are provided on the base substrate 10, each of the pixel units including a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate 10, the driving circuit including a plurality of thin-film transistors, the plurality of thin-film transistors being provided in two layers, the plurality of thin-film transistors including a target thin-film transistor T4, the target thin-film transistor T4 being located on a layer away from the base substrate 10; the light-emitting device including: a stacked anode 81, a light-emitting layer (not shown), and a cathode (not shown);

[0038] The array substrate further includes: a channel blocking layer 82, which is arranged on the same layer as the anode 81, and the orthographic projection area of the active layer 63 of the target thin film transistor T4 on the base substrate 10 is located within the orthographic projection area of the channel blocking layer 82 on the base substrate 10; wherein the edge area of the surface of the side of the channel blocking layer 82 facing away from the target thin film transistor T4 is bent toward the base substrate 10.

[0039] Please refer to Figure 2 , Figure 2 The positional relationship between the channel blocking layer and the active layer of the target thin film transistor is shown. Figure 2 It can be seen that the channel blocking layer 82 in the embodiment of the present invention is bent toward the base substrate in the edge area of the side surface facing away from the target thin film transistor. Compared with the channel blocking layer 82' in the prior art, it can block more light incident from the edge of the channel blocking layer, thereby improving the light blocking effect and preventing light from entering the channel (i.e., the active layer 63) of the target thin film transistor from the edge of the channel blocking layer, thereby improving display uniformity.

[0040] In the embodiment of the present invention, Figure 1 and Figure 2 As shown, the entire area of the surface of the channel blocking layer 82 facing away from the target thin film transistor is a convex arc surface. Of course, the structure of the channel blocking layer 82 is not limited to this. Please refer to Figure 3 The edge area of the surface of the channel blocking layer 82 on the side facing away from the target thin film transistor is a convex arc surface, while the middle area is a flat surface.

[0041] In addition, please refer to Figure 4 The edge area of the surface of the channel blocking layer 82 facing away from the target thin film transistor may not be a convex arc surface, but a linear slope surface, or may be a concave arc surface.

[0042] Please refer to Figure 1-Figure 4The shape of the surface of the channel blocking layer 82 facing the target thin film transistor is the same as the shape of the surface of the channel blocking layer 82 facing away from the target thin film transistor. For example, please refer to Figure 1 and Figure 2 The surface of the channel blocking layer 82 facing the target thin film transistor has the same shape as the surface of the target thin film transistor, both of which are convex arc surfaces.

[0043] The shape of the surface of the channel blocking layer 82 facing the target thin film transistor and the shape of the surface of the channel blocking layer 82 facing away from the target thin film transistor may also be different. Figure 5 The surface of the channel blocking layer 82 facing the target thin film transistor is a plane, while the surface of the channel blocking layer 82 facing away from the target thin film transistor is a convex arc surface.

[0044] Please refer to Figure 1 The array substrate in the embodiment of the present invention further includes: a second flat layer 70, which is located between the target thin film transistor T4 and the channel blocking layer 82. The shape of the area of the second flat layer 70 on the side away from the target thin film transistor T4 where the channel blocking layer is provided matches the shape of the side of the channel blocking layer 82 facing away from the target thin film transistor, for example, being a convex arc surface.

[0045] Below Figure 1 The film structure of the array substrate shown in FIG. is described in detail. The array substrate includes:

[0046] The base substrate 10 is a flexible substrate and includes a first PI (polyimide) layer 11, a first barrier layer 12, a second PI layer 13, a second barrier layer 14, and a first buffer layer 15. The thickness of the first PI layer 11 and the second PI layer 13 can be 5 μm to 10 μm. The first barrier layer 12 can be SiO2 / a-Si (amorphous silicon), where the thickness of SiO2 can be 4000 Å to 7000 Å and the thickness of a-Si can be 200 Å to 600 Å. The second barrier layer 14 can be SiO2, where the thickness can be 4000 Å to 6500 Å. The first buffer layer 15 can be SiNx / SiO2, where the thickness can be 300 Å to 700 Å and 2000 Å to 3500 Å, respectively.

[0047] Multiple pixel units are provided on the base substrate 10. Each pixel unit includes a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate 10. The driving circuit includes multiple thin-film transistors, which are arranged in two layers. The thin-film transistors located on the layer closer to the base substrate 10 are located in a film layer 30, and the thin-film transistors located on the layer farther from the base substrate 10 are located in a film layer 60. The thin-film transistors located on the layer closer to the base substrate 10 include: an active layer 31, a first gate insulating layer 32, a first gate metal layer 33, a second gate insulating layer 34, a second gate metal layer 35, a first interlayer dielectric layer 36, and a first source-drain metal layer 37. The thin-film transistors located on the layer closer to the base substrate 10 include: a third gate metal layer 61, a third buffer layer 62, an active layer 63, a third gate insulating layer 64, a fourth gate metal layer 65, a second interlayer dielectric layer 66, and a second source-drain metal layer 37. The film layer 60 where the thin film transistor is located on a layer close to the base substrate 10 includes the target thin film transistor T4 .

[0048] The first planar layer 40 and the second buffer layer 50 are located between the film layer 30 and the film layer 60 .

[0049] The second planar layer 70 is located between the film layer 60 and the light-emitting device.

[0050] The light emitting device comprises: an anode 81, a light emitting layer (not shown) and a cathode (not shown);

[0051] The channel blocking layer 82 is arranged on the same layer as the anode 81, and the positive projection area of the active layer 63 of the target thin film transistor T4 on the base substrate 10 is located within the positive projection area of the channel blocking layer 82 on the base substrate 10; wherein, the edge area of the surface of the side of the channel blocking layer 82 facing away from the target thin film transistor T4 is bent toward the base substrate 10.

[0052] The pixel definition layer 90 is used to space the pixel units at different intervals.

[0053] The spacer 90 is disposed on a side of the pixel definition layer 90 away from the base substrate 10 .

[0054] Please refer to Figure 6 , an embodiment of the present invention provides an array substrate, comprising:

[0055] A base substrate 10 and a plurality of pixel units disposed on the base substrate 10, each pixel unit including a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate 10, the driving circuit including a plurality of thin-film transistors disposed in two layers, including a target thin-film transistor T4, which is located in a layer away from the base substrate 10; the light-emitting device including: a stacked anode 81, a light-emitting layer (not shown), and a cathode (not shown);

[0056] The array substrate further includes: a channel blocking layer 82, which is arranged on the same layer as the anode 81, and the orthographic projection area of the active layer of the target thin film transistor T4 on the base substrate 10 is located within the orthographic projection area of the channel blocking layer 82 on the base substrate 10; wherein, the vertical distance between the channel blocking layer 82 and the plane where the active layer 63 of the target thin film transistor T4 is located is smaller than the vertical distance between the anode 81 and the plane where the active layer 63 of the target thin film transistor T4 is located.

[0057] Please refer to Figure 7 , Figure 7 The positional relationship between the channel blocking layer and the active layer of the target thin film transistor is shown. Figure 7 It can be seen that the channel blocking layer 82 in the embodiment of the present invention is compared with the channel blocking layer 82' in the prior art. Since the vertical distance to the channel of the target thin film transistor (i.e., the active layer 63) is closer, more light incident from the edge of the channel blocking layer can be blocked, thereby improving the light blocking effect and preventing light from entering the channel of the target thin film transistor (i.e., the active layer 63) from the edge of the channel blocking layer, thereby improving display uniformity.

[0058] The array substrate of an embodiment of the present invention further includes: a second flat layer 70, which is located between the target thin film transistor T4 and the channel blocking layer 82, and the thickness of the second flat layer 70 in the area where the channel blocking layer 82 is set is less than the thickness of the area where the anode 81 is set.

[0059] In the embodiment of the present invention, optionally, the region of the second planar layer 70 where the channel blocking layer 82 is disposed has a groove, and the channel blocking layer 82 is disposed in the groove.

[0060] In the embodiment of the present invention, optionally, the thickness of the second planar layer 70 in the region where the channel blocking layer 82 is provided is 0.4-1.0 μm, and the thickness of the second planar layer 70 in the region where the anode 81 is provided is 1.2-1.8 μm.

[0061] In the above-described embodiments of the present invention, the active layer 63 of the thin-film transistor located one layer away from the base substrate 10 among the plurality of thin-film transistors may optionally be made of an oxide, such as IGZO (indium gallium zinc oxide). Oxides are unstable and easily affected by light, causing threshold voltage drift and uneven display, thus requiring a shielding layer.

[0062] In the above embodiments of the present invention, optionally, the active layer 63 of the thin film transistor close to the base substrate 10 among the plurality of thin film transistors is made of low temperature polysilicon (LTPS).

[0063] Below Figure 6 The film structure of the array substrate shown in FIG. is described in detail. The array substrate includes:

[0064] The base substrate 10 is a flexible substrate and includes a first PI (polyimide) layer 11, a first barrier layer 12, a second PI layer 13, a second barrier layer 14, and a first buffer layer 15. The thickness of the first PI layer 11 and the second PI layer 13 can be 5 μm to 10 μm. The first barrier layer 12 can be SiO2 / a-Si (amorphous silicon), where the thickness of SiO2 can be 4000 Å to 7000 Å and the thickness of a-Si can be 200 Å to 600 Å. The second barrier layer 14 can be SiO2, where the thickness can be 4000 Å to 6500 Å. The first buffer layer 15 can be SiNx / SiO2, where the thickness can be 300 Å to 700 Å and 2000 Å to 3500 Å, respectively.

[0065] Multiple pixel units are provided on the base substrate 10. Each pixel unit includes a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate 10. The driving circuit includes multiple thin-film transistors, which are arranged in two layers. The thin-film transistors located on the layer closer to the base substrate 10 are located in a film layer 30, and the thin-film transistors located on the layer farther from the base substrate 10 are located in a film layer 60. The thin-film transistors located on the layer closer to the base substrate 10 include: an active layer 31, a first gate insulating layer 32, a first gate metal layer 33, a second gate insulating layer 34, a second gate metal layer 35, a first interlayer dielectric layer 36, and a first source-drain metal layer 37. The thin-film transistors located on the layer closer to the base substrate 10 include: a third gate metal layer 61, a third buffer layer 62, an active layer 63, a third gate insulating layer 64, a fourth gate metal layer 65, a second interlayer dielectric layer 66, and a second source-drain metal layer 37. The film layer 60 where the thin film transistor is located on a layer close to the base substrate 10 includes the target thin film transistor T4 .

[0066] The first planar layer 40 and the second buffer layer 50 are located between the film layer 30 and the film layer 60 .

[0067] The second planar layer 70 is located between the film layer 60 and the light-emitting device.

[0068] The light emitting device comprises: an anode 81, a light emitting layer (not shown) and a cathode (not shown);

[0069] The channel blocking layer 82 is arranged on the same layer as the anode 81, and the orthographic projection area of the active layer 63 of the target thin film transistor T4 on the base substrate 10 is located within the orthographic projection area of the channel blocking layer 82 on the base substrate 10; wherein, the vertical distance between the channel blocking layer 82 and the plane where the active layer 63 of the target thin film transistor T4 is located is smaller than the vertical distance between the anode 81 and the plane where the active layer 63 of the target thin film transistor T4 is located.

[0070] The pixel definition layer 90 is used to space the pixel units at different intervals.

[0071] The spacer 90 is disposed on a side of the pixel definition layer 90 away from the base substrate 10 .

[0072] In an embodiment of the present invention, for a target thin film transistor in an array substrate, an edge area of a surface of a channel blocking layer facing away from the target thin film transistor is bent, or a vertical distance between the channel blocking layer and a plane where an active layer of the target thin film transistor is located is shortened. This can improve the light shielding effect of the channel blocking layer while maintaining the same occupied area of the channel blocking layer, thereby preventing light from entering the channel of the target thin film transistor from the edge of the channel blocking layer, thereby improving display uniformity.

[0073] An embodiment of the present invention further provides a display device, comprising the array substrate according to any of the above embodiments. The display device may be a display panel, a monitor, a mobile phone, a tablet, or the like.

[0074] An embodiment of the present invention further provides a method for manufacturing an array substrate, comprising:

[0075] Step 1: providing a substrate;

[0076] Step 2: forming a plurality of pixel units and a channel shielding layer on the substrate, wherein each pixel unit includes a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the substrate, wherein the driving circuit includes a plurality of thin-film transistors, the plurality of thin-film transistors being arranged in two layers, the plurality of thin-film transistors including a target thin-film transistor, the target thin-film transistor being located in a layer away from the substrate; and the light-emitting device includes a stacked anode, a light-emitting layer, and a cathode.

[0077] Step 3: The channel blocking layer and the anode are provided on the same layer, and the orthographic projection area of the active layer of the target thin film transistor on the base substrate is located within the orthographic projection area of the channel blocking layer on the base substrate;

[0078] In which, the edge area of the surface of the side of the channel blocking layer facing away from the target thin film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin film transistor is located.

[0079] For example, see Figures 8-12 , Figures 8-12 FIG. 1 is a flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention. The method includes:

[0080] Step S1: Please refer to Figure 8A base substrate 10 is formed on a supporting substrate (not shown, such as a glass substrate). The base substrate 10 includes a first PI layer 11, a first barrier layer 12, a second PI layer 13, a second barrier layer 14, and a first buffer layer 15. The thickness of the first PI layer 11 and the second PI layer 13 can be 5 μm to 10 μm. The first barrier layer 12 can be SiO2 / a-Si, where the thickness of SiO2 can be 4000 Å to 7000 Å and the thickness of a-Si can be 200 Å to 600 Å. The second barrier layer 14 can be SiO2, where the thickness can be 4000 Å to 6500 Å. The first buffer layer 15 can be SiNx / SiO2, where the thickness can be 300 Å to 700 Å and 2000 Å to 3500 Å, respectively.

[0081] Step S2: Please refer to Figure 9 A driving circuit, a first planarization layer 40, and a second buffer layer 50 are formed on the base substrate. The driving circuit includes multiple thin film transistors arranged in two layers. The thin film transistors located in a layer closer to the base substrate 10 are located in a film layer 30, and the thin film transistors located in a layer farther from the base substrate 10 are located in a film layer 60. The thin film transistor layer 30 located in a layer closer to the base substrate 10 includes: an active layer 31, a first gate insulating layer 32, a first gate metal layer 33, a second gate insulating layer 34, a second gate metal layer 35, a first interlayer dielectric layer 36, and a first source / drain metal layer 37. The thin film transistor layer 60 located in a layer closer to the base substrate 10 includes: a third gate metal layer 61, a third buffer layer 62, an active layer 63, a third gate insulating layer 64, a fourth gate metal layer 65, a second interlayer dielectric layer 66, and a second source / drain metal layer 37. The thin film transistor layer 60 located in a layer closer to the base substrate 10 includes a target thin film transistor T4.

[0082] The first planar layer 40 and the second buffer layer 50 are located between the film layer 30 and the film layer 60 .

[0083] Step S3: Please refer to Figure 10 A second planar layer 70 is deposited on the base substrate 10 forming the driving circuit. The thickness of the second planar layer 70 may be 1.5 to 2.5 μm.

[0084] Step S4: Please refer to Figure 11 The second planar layer 70 is patterned using halftone technology, and the area of the patterned second planar layer 70 used to set the channel shielding layer 82 is a convex arc surface.

[0085] Step S5: Please refer to Figure 12, an anode metal layer is deposited on the second planar layer 70 , and the anode metal layer is patterned to obtain an anode 81 and a channel blocking layer 82 .

[0086] Step S6: forming a pixel definition layer, a light-emitting layer and a cathode in sequence.

[0087] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. An array substrate, characterized in that: include: A base substrate and a plurality of pixel units disposed on the base substrate, each pixel unit comprising a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the base substrate, the driving circuit comprising a plurality of thin film transistors, the plurality of thin film transistors being disposed in two layers, the plurality of thin film transistors including a target thin film transistor, the target thin film transistor being located on a layer away from the base substrate; The light emitting device comprises: an anode, a light emitting layer and a cathode arranged in layers; The array substrate further comprises: a channel blocking layer, the channel blocking layer being provided on the same layer as the anode, and the orthographic projection area of the active layer of the target thin film transistor on the base substrate being located within the orthographic projection area of the channel blocking layer on the base substrate; In which, the edge area of the surface of the side of the channel blocking layer facing away from the target thin film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin film transistor is located.

2. The array substrate according to claim 1, wherein: The active layer of the thin film transistor that is one layer away from the base substrate among the plurality of thin film transistors is made of oxide.

3. The array substrate according to claim 1, wherein: The active layer of the thin film transistor close to the substrate among the plurality of thin film transistors is made of low temperature polycrystalline silicon (LTPS).

4. The array substrate according to claim 1, wherein: An edge area of a surface of the channel blocking layer facing away from the target thin film transistor is a convex arc surface, or an entire area of the surface of the channel blocking layer facing away from the target thin film transistor is a convex arc surface.

5. The array substrate according to claim 4, wherein: A surface of the channel blocking layer facing the target thin film transistor is flat.

6. The array substrate according to claim 4, wherein: A surface of the channel blocking layer facing the target thin film transistor is an outwardly convex arc surface.

7. The array substrate according to any one of claims 1 to 6, characterized in that: Also includes: A second flat layer, the second flat layer is located between the target thin film transistor and the channel blocking layer, and the area of the second flat layer on the side surface away from the target thin film transistor where the channel blocking layer is set matches the shape of the side surface of the channel blocking layer facing away from the target thin film transistor.

8. The array substrate according to claim 1, wherein: Also includes: A second planar layer is provided between the target thin film transistor and the channel blocking layer, and a thickness of the second planar layer in a region where the channel blocking layer is provided is smaller than a thickness of the region where the anode is provided.

9. The array substrate according to claim 8, wherein: The area of the second planar layer where the channel blocking layer is disposed has a groove, and the channel blocking layer is disposed in the groove.

10. The array substrate according to claim 8 or 9, characterized in that: The thickness of the second planar layer in the region where the channel blocking layer is provided is 0.4-1.0 μm, and the thickness of the second planar layer in the region where the anode is provided is 1.2-1.8 μm.

11. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; A plurality of pixel units and a channel shielding layer are formed on the substrate, each of the pixel units including a driving circuit and a light-emitting device connected to the driving circuit and located on a side of the driving circuit away from the substrate, the driving circuit including a plurality of thin film transistors arranged in two layers, the plurality of thin film transistors including a target thin film transistor, the target thin film transistor being located on a layer away from the substrate; the light-emitting device including: an anode, a light-emitting layer, and a cathode arranged in a stacked manner; The channel blocking layer is provided on the same layer as the anode, and the orthographic projection area of the active layer of the target thin film transistor on the base substrate is located within the orthographic projection area of the channel blocking layer on the base substrate; In which, the edge area of the surface of the side of the channel blocking layer facing away from the target thin film transistor is bent toward the base substrate, or the vertical distance between the channel blocking layer and the plane where the active layer of the target thin film transistor is located is smaller than the vertical distance between the anode and the plane where the active layer of the target thin film transistor is located.

12. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10.

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