A symmetric high-voltage MOS device and its manufacturing method

Abstract

The present invention discloses a symmetrical high-voltage MOS device, which relates to the field of semiconductor technology. It includes a base structure, on the top surface of which a first Si3N4 passivation layer is covered, and a second Si3N4 passivation layer is covered on the first Si3N4 passivation layer. A source metal and a drain metal that penetrate through the first Si3N4 passivation layer and the second Si3N4 passivation layer are respectively arranged on the left and right sides of the top surface of the base structure. Among them, a gate groove is etched in the center of the first Si3N4 passivation layer, and the source metal and the drain metal are symmetrically arranged with respect to the gate groove. An Al2O3 dielectric is deposited in the gate groove, and the top of the Al2O3 dielectric extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer. A gate metal is inserted into the center of the top of the Al2O3 dielectric, and the top of the gate metal extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer and wraps the Al2O3 dielectric. A manufacturing method of the symmetrical high-voltage MOS device is also disclosed. The present invention has the advantages of safety, stability, strong reliability and long service life.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a symmetrical high-voltage MOS device and a manufacturing method thereof. Background Art

[0002] A MOS device (metal-oxide-semiconductor field-effect transistor) is a main device in modern integrated circuits. At present, during the continuous operation of a MOS device under radio frequency and other signals, gate metal leakage is likely to occur. Gate metal leakage will affect the reliability of the continuous operation of the entire MOS device. At the same time, a large gate metal leakage current will directly reduce the breakdown voltage and power-added efficiency of the MOS device, resulting in the current collapse effect, and further affecting the reliability of the use of the entire MOS device. Summary of the Invention

[0003] Aiming at the defects in the prior art, the present invention provides a symmetrical high-voltage MOS device and a manufacturing method thereof.

[0004] A symmetric high-voltage MOS device includes a substrate structure, on the top surface of which a first Si3N4 passivation layer is covered, and a second Si3N4 passivation layer is covered on the first Si3N4 passivation layer. Source metal and drain metal that penetrate through the first Si3N4 passivation layer and the second Si3N4 passivation layer are respectively arranged on the left and right sides of the top surface of the substrate structure. Wherein, a gate groove is etched in the center of the first Si3N4 passivation layer, and the source metal and the drain metal are symmetrically arranged with respect to the gate groove. Al2O3 dielectric is deposited in the gate groove, and the top of the Al2O3 dielectric extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer. A gate metal is inserted in the center of the top of the Al2O3 dielectric, and the top of the gate metal extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer and wraps the Al2O3 dielectric. In the whole symmetric high-voltage MOS device, through the arrangement of the first Si3N4 passivation layer and the second Si3N4 passivation layer, a dual-field plate device structure with a high breakdown voltage and small off-state leakage is formed. At the same time, the Si3N4 material not only serves as the field plate dielectric but also completes the surface passivation of the device, effectively reducing the current collapse effect of the device and improving the reliability of the device. Further, by depositing Al2O3 dielectric in the gate groove and then arranging a gate metal in the center of its top, the forward gate conduction voltage can be effectively increased, so that it can work at a higher gate voltage. At the same time, the Al2O3 dielectric not only has a high breakdown voltage but also has a high dielectric constant, which can effectively compensate for the negative effects such as gate voltage division caused by depositing the dielectric in the gate groove. Further, by symmetrically arranging the source metal and the drain metal with respect to the gate groove, the size ratio of the whole MOS device can be reduced, the top surface area of the whole symmetric high-voltage MOS device can be reduced, and at the same time, the consumption of the first Si3N4 passivation layer and the second Si3N4 passivation layer is reduced, saving production costs. More importantly, by extending the top of the Al2O3 dielectric between the first Si3N4 passivation layer and the second Si3N4 passivation layer, and at the same time, the top of the gate metal extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer and wraps the Al2O3 dielectric, on the basis of realizing the device function, the space utilization rate is greatly improved, the whole device has a higher saturation drain current, the whole gate has a higher breakdown voltage, and the gate leakage problem is minimized.

[0005] Preferably, the substrate structure includes a SiC substrate located at the bottom layer. In the substrate structure, the bottom layer can adopt a SiC substrate or a sapphire substrate, and heteroepitaxial methods can be used to grow each crystal layer.

[0006] Preferably, the substrate structure further includes a first GaN buffer layer, an AlGaN barrier layer, and a second GaN buffer layer that are sequentially grown on the SiC substrate.

[0007] Preferably, a nucleation layer is provided between the SiC substrate and the first GaN buffer layer. In the SiC substrate and the first GaN buffer layer, a nucleation layer, preferably an AlN nucleation layer, is added to release the lattice stress generated by lattice mismatch and thermal mismatch.

[0008] Preferably, isolation grooves are formed around the upper half of the base structure. By forming the isolation grooves, mesa isolation is achieved, with a simple structure and process, saving equipment costs.

[0009] A method for fabricating a symmetric high-voltage MOS device is also provided, including: S1, growing the base structure; S2, evaporating to form the source and drain electrodes of the device while reducing the ohmic contact resistance; S3, forming mesa isolation; S4, depositing the first Si3N4 passivation layer on the top surface of the base structure; S5, etching the first Si3N4 passivation layer to form a gate groove; S6, using atomic layer deposition of Al2O3 dielectric, and then evaporating the gate metal to form a gate electrode; S7, depositing the second Si3N4 passivation layer on the top surface of the first Si3N4 passivation layer; S8, etching the first Si3N4 passivation layer and the second Si3N4 passivation layer to expose the gate metal, the source, and the drain, and then evaporating and interconnecting the metal.

[0010] Preferably, S1 includes using organic compounds and hydrides as crystal growth source materials, and performing vapor phase epitaxy on the SiC substrate by thermal decomposition reaction to sequentially grow the first GaN buffer layer, the AlGaN barrier layer, and the second GaN buffer layer.

[0011] Preferably, S2 also includes reducing the ohmic contact resistance. The processes affecting the ohmic contact of the device are mainly the ratio of evaporated metal and the temperature and time of high-temperature rapid annealing. Surface roughening can improve the contact characteristics of the device, thereby reducing the ohmic contact resistance of the device.

[0012] Preferably, S3 includes using dry etching to form isolation grooves to achieve mesa isolation. There are usually two methods to complete mesa isolation. One is implantation isolation, and the other is mesa etching. Since the implantation equipment is relatively complex, mesa etching is used to complete mesa isolation.

[0013] Preferably, it further includes S9, thickening the electrode. The method of electroplating metal is used to form a thickened electrode. The quality of electroplated metal has a great impact on the device, especially on the reliability and stability of the device during long-term use.

[0014] The beneficial effects of the present invention are as follows:

[0015] In the present invention, by providing the first Si3N4 passivation layer and the second Si3N4 passivation layer, a dual-field plate device structure with a high breakdown voltage and low off-state leakage is formed. At the same time, while the Si3N4 material serves as the field plate dielectric, it also completes the surface passivation of the device, effectively reducing the current collapse effect of the device and improving the reliability of the device. Further, by depositing Al2O3 dielectric in the gate trench and then setting the gate metal at the center of its top, the forward gate conduction voltage can be effectively increased, enabling it to operate at a higher gate voltage. At the same time, the Al2O3 dielectric not only has a high breakdown voltage but also a high dielectric constant, which can effectively compensate for the negative effects such as gate voltage division caused by depositing the dielectric in the gate trench. Further, by symmetrically arranging the source metal and the drain metal with respect to the gate trench, the size ratio of the entire MOS device can be reduced, the top area of the entire symmetric high-voltage MOS device can be decreased, and at the same time, the usage amounts of the first Si3N4 passivation layer and the second Si3N4 passivation layer are reduced, saving production costs. More importantly, by extending the top of the Al2O3 dielectric between the first Si3N4 passivation layer and the second Si3N4 passivation layer, and at the same time extending the top of the gate metal between the first Si3N4 passivation layer and the second Si3N4 passivation layer to wrap the Al2O3 dielectric, on the basis of realizing the device functions, the space utilization rate is greatly improved, the entire device has a higher saturation drain current, the entire gate has a high breakdown voltage, and the gate leakage problem is minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally denoted by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0017] Figure 1 is a schematic structural diagram of the symmetric high-voltage MOS device of the present invention;

[0018] Figure 2 is a schematic structural diagram of the manufacturing method S1 of the symmetric high-voltage MOS device of the present invention;

[0019] Figure 3 is a schematic structural diagram of the manufacturing method S2 of the symmetric high-voltage MOS device of the present invention;

[0020] Figure 4 is a schematic structural diagram of the manufacturing method S3 of the symmetric high-voltage MOS device of the present invention;

[0021] Figure 5 is a schematic structural diagram of the manufacturing method S4 of the symmetric high-voltage MOS device of the present invention;

[0022] Figure 6 It is a schematic structural diagram of Step S5 of the manufacturing method of the symmetric high-voltage MOS device of the present invention;

[0023] Figure 7 It is a schematic structural diagram of Step S6 of the manufacturing method of the symmetric high-voltage MOS device of the present invention;

[0024] Figure 8 It is a schematic structural diagram of Step S7 of the manufacturing method of the symmetric high-voltage MOS device of the present invention;

[0025] Figure 9 It is a schematic structural diagram of Step S8 of the manufacturing method of the symmetric high-voltage MOS device of the present invention.

[0026] Reference numerals:

[0027] 1 - Substrate structure, 11 - SiC substrate, 12 - First GaN buffer layer, 13 - AlGaN barrier layer, 14 - Second GaN buffer layer, 15 - Nucleation layer, 16 - Isolation groove, 2 - First Si3N4 passivation layer, 3 - Second Si3N4 passivation layer, 4 - Source metal, 5 - Drain metal, 6 - Gate groove, 7 - Al2O3 dielectric, 8 - Gate metal. Detailed implementation manners

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0030] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0031] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "inside", "outside", "upper", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the invention product is customarily placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0032] As Figure 1 shown, a symmetrical high-voltage MOS device includes a base structure 1. A first passivation layer 2 covers the top surface of the base structure 1, and a second passivation layer 3 covers the first passivation layer 2. A source metal 4 and a drain metal 5 are respectively arranged on the left and right sides of the top surface of the base structure 1 and penetrate through the first passivation layer 2 and the second passivation layer 3; wherein, a gate groove 6 is etched in the center of the first passivation layer 2, and the source metal 4 and the drain metal 5 are symmetrically arranged with respect to the gate groove 6. A dielectric 7 is deposited in the gate groove 6, and the top of the dielectric 7 extends between the first passivation layer 2 and the second passivation layer 3. A gate metal 8 is inserted into the center of the top of the dielectric 7, and the top of the gate metal 8 extends between the first passivation layer 2 and the second passivation layer 3 and wraps the dielectric 7.

[0033] In this embodiment, it should be noted that in the entire symmetrical high-voltage MOS device, through the setting of the first passivation layer 2 and the second passivation layer 3, a dual field plate device structure with a high breakdown voltage and small off-state leakage is formed. At the same time, while the material serves as the field plate dielectric 7, the surface passivation of the device is also completed, effectively reducing the current collapse effect of the device and improving the reliability of the device; further, by depositing the dielectric 7 in the gate groove 6 and then arranging the gate metal 8 at the center of its top, the forward gate conduction voltage can be effectively increased, so that it can operate at a higher gate voltage. At the same time, the dielectric 7 not only has a high breakdown voltage but also has a high dielectric constant, which can effectively compensate for the negative effects such as gate voltage division caused by depositing the dielectric 7 in the gate groove 6; further, by symmetrically arranging the source metal 4 and the drain metal 5 with respect to the gate groove 6, the size ratio of the entire MOS device can be reduced, the top surface area of the entire symmetrical high-voltage MOS device can be reduced, and at the same time, the usage amount of the first passivation layer 2 and the second passivation layer 3 can be reduced, saving production costs; more importantly, by extending the top of the dielectric 7 between the first passivation layer 2 and the second passivation layer 3, and at the same time, the top of the gate metal 8 extends between the first passivation layer 2 and the second passivation layer 3 and wraps the dielectric 7, on the basis of realizing the device functions, the space utilization rate is greatly improved, the entire device has a higher saturation drain current, the entire gate has a higher breakdown voltage, and the gate leakage problem is minimized.

[0034] Specifically, the base structure 1 includes a SiC substrate 11 located at the bottom layer.

[0035] In this embodiment, it should be noted that in the base structure 1, the bottom layer can use a SiC substrate 11 or a sapphire substrate, and the heteroepitaxial method can be used to grow each crystal layer.

[0036] Specifically, the base structure 1 further includes a first GaN buffer layer 12, an AlGaN barrier layer 13, and a second GaN buffer layer 14 that are sequentially grown on the SiC substrate 11.

[0037] Specifically, a nucleation layer 15 is provided between the SiC substrate 11 and the first GaN buffer layer 12.

[0038] In this embodiment, it should be noted that in the SiC substrate 11 and the first GaN buffer layer 12, a nucleation layer 15, preferably an AlN nucleation layer 15, is added to release the lattice stress generated by lattice mismatch and thermal mismatch.

[0039] Specifically, isolation grooves 16 are formed around the upper half of the base structure 1.

[0040] In this embodiment, it should be noted that by forming the isolation grooves 16, mesa isolation is achieved, and the structure and process are simple, saving equipment costs.

[0041] A method for manufacturing a symmetric high-voltage MOS device is also provided, including: S1, growing the base structure 1; S2, evaporating to form the source and drain electrodes of the device while reducing the ohmic contact resistance; S3, forming mesa isolation; S4, depositing the first passivation layer 2 on the top surface of the base structure 1; S5, etching the first passivation layer 2 to form a gate groove 6; S6, using atomic layer deposition of a dielectric 7, and then evaporating a gate metal to form a gate electrode metal 8; S7, depositing the second passivation layer 3 on the top surface of the first passivation layer 2; S8, etching the first passivation layer 2 and the second passivation layer 3 to expose the gate electrode metal 8, the source, and the drain, and then evaporating and interconnecting the metals.

[0042] In this embodiment, it should be noted that S1, as Figure 2 shown, growing the base structure 1; S2, as Figure 3 shown, evaporating to form the source and drain electrodes of the device while reducing the ohmic contact resistance; S3, as Figure 4 shown, forming mesa isolation; S4, as Figure 5 shown, depositing the first passivation layer 2 on the top surface of the base structure 1; S5, as Figure 6 shown, etching the first passivation layer 2 to form a gate groove 6; S6, as Figure 7 shown, using atomic layer deposition of a dielectric 7, and then evaporating a gate metal to form a gate electrode metal 8; S7, as Figure 8 shown, depositing the second passivation layer 3 on the top surface of the first passivation layer 2; S8, as Figure 9As shown, the first passivation layer 2 and the second passivation layer 3 are etched to expose the gate metal 8, the source, and the drain, and then metal is evaporated and interconnected.

[0043] Specifically, S1 includes using organic compounds and hydrides as crystal growth source materials, and performing vapor phase epitaxy on the SiC substrate 11 through a thermal decomposition reaction to sequentially grow a first GaN buffer layer 12, an AlGaN barrier layer 13, and a second GaN buffer layer 14.

[0044] Specifically, S2 also includes reducing the ohmic contact resistance.

[0045] In this embodiment, it should be noted that the processes affecting the ohmic contact of the device are mainly the ratio of evaporated metal and the temperature and time of high-temperature rapid annealing. Surface roughening can improve the contact characteristics of the device, thereby reducing the ohmic contact resistance of the device.

[0046] Specifically, S3 includes using dry etching to form isolation grooves 16 to form mesa isolation.

[0047] In this embodiment, it should be noted that mesa isolation is usually completed in two ways. One is implantation isolation, and the other is mesa etching. Since the implantation equipment is relatively complex, mesa etching is used to complete mesa isolation.

[0048] Specifically, it also includes S9: thickening the electrode.

[0049] In this embodiment, it should be noted that the thickened electrode is formed by electroplating metal. The quality of the electroplated metal has a great impact on the device, especially on the reliability and stability of the long-term use of the device.

[0050] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

Claims

1. A symmetric high-voltage MOS device, characterized in that, It includes a base structure, the top surface of the base structure is covered with a first Si3N4 passivation layer, the first Si3N4 passivation layer is covered with a second Si3N4 passivation layer, and a source metal and a drain metal that penetrate through the first Si3N4 passivation layer and the second Si3N4 passivation layer are respectively arranged on the left and right sides of the top surface of the base structure; wherein, a gate groove is etched in the center of the first Si3N4 passivation layer, the source metal and the drain metal are symmetrically arranged with respect to the gate groove, an Al2O3 dielectric is deposited in the gate groove, the top of the Al2O3 dielectric extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer, and a gate metal is inserted into the center of the top of the Al2O3 dielectric, and the top of the gate metal extends between the first Si3N4 passivation layer and the second Si3N4 passivation layer and wraps the Al2O3 dielectric.

2. The symmetric high-voltage MOS device according to claim 1, wherein The base structure includes a SiC substrate located at the bottom layer.

3. The symmetric high-voltage MOS device according to claim 2, wherein The base structure further includes a first GaN buffer layer, an AlGaN barrier layer, and a second GaN buffer layer that are sequentially grown on the SiC substrate.

4. The symmetrical high-voltage MOS device according to claim 3, characterized in that, A nucleation layer is arranged between the SiC substrate and the first GaN buffer layer.

5. The symmetrical high-voltage MOS device according to claim 1, wherein Isolation grooves are formed around the upper half of the base structure.

6. A manufacturing method of the symmetric high-voltage MOS device according to any one of claims 1-5, characterized in that, It includes: S1, growing the base structure; S2, evaporating to form the source and drain of the device while reducing the ohmic contact resistance; S3, forming mesa isolation; S4, completing the deposition of the first Si3N4 passivation layer on the top surface of the base structure; S5, etching the first Si3N4 passivation layer to form a gate groove; S6, depositing an Al2O3 dielectric by atomic layer deposition, and then evaporating the gate metal to form a gate electrode; S7, completing the deposition of the second Si3N4 passivation layer on the top surface of the first Si3N4 passivation layer; S8, etching the first Si3N4 passivation layer and the second Si3N4 passivation layer to expose the gate metal, the source, and the drain, and then evaporating the metal and interconnecting.

7. The manufacturing method of the symmetric high-voltage MOS device according to claim 6, characterized in that, The S1 includes using organic compounds and hydrides as crystal growth source materials, and performing vapor phase epitaxy on the SiC substrate by thermal decomposition reaction to sequentially grow a first GaN buffer layer, an AlGaN barrier layer, and a second GaN buffer layer.

8. The manufacturing method of the symmetric high-voltage MOS device according to claim 6, wherein The S3 includes using dry etching to etch out isolation grooves to form mesa isolation.

9. The manufacturing method of the symmetric high-voltage MOS device according to claim 6, characterized in that It further includes S9, thickening the electrodes.

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