Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device. The display substrate comprises: a substrate and a signal line film layer arranged on the substrate; the signal line film layer comprises: a first conductive layer, a second conductive layer and a conductive connection layer, the conductive connection layer and the first conductive layer and the second conductive layer are arranged in different layers, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate, and the conductive connection layer is coupled to the first conductive layer and the second conductive connection layer respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Active matrix organic light emitting diode display panels are increasingly used in the display field. With their popularity in the high-end market, the quality requirements of screens are getting higher and higher, such as achieving higher brightness display and providing users with a better experience outdoors. Therefore, more refined requirements are needed for the design of display panels. Summary of the invention

[0003] An object of the present disclosure is to provide a display substrate and a display device.

[0004] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0005] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a signal line film layer disposed on the substrate; the signal line film layer comprises:

[0006] a first conductive layer and a second conductive layer arranged in a stacked manner; and

[0007] A conductive connection layer, wherein the conductive connection layer and the first conductive layer and the second conductive layer are arranged in different layers, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate, and the conductive connection layer is coupled to the first conductive layer and the second conductive connection layer respectively.

[0008] Optionally, the conductive connection layer includes a plurality of conductive connection patterns;

[0009] The first conductive layer includes a plurality of first conductive patterns arranged along a first direction; the first conductive pattern includes at least a portion extending along a second direction, the second direction intersects with the first direction, and the first conductive pattern includes a plurality of first hollow areas; the first conductive pattern is coupled to the corresponding conductive connection pattern.

[0010] Optionally, the first conductive pattern includes a plurality of first portions and a plurality of second portions, and the first portions and the second portions are alternately arranged along the second direction;

[0011] The width of the first portion in a direction perpendicular to the second direction is smaller than the distance between two boundaries of the second portion that are farthest apart in a direction perpendicular to the second direction; and the second portion includes the first hollow area.

[0012] Optionally, the plurality of first portions include a plurality of first target portions and a plurality of second target portions, the first target portions and the second target portions are alternately arranged, and a width of the first target portion in a direction perpendicular to the second direction is greater than a width of the second target portion in a direction perpendicular to the second direction;

[0013] The first target portion is coupled to the corresponding conductive connection pattern.

[0014] Optionally, the first target portion and the second target portion are staggered along the first direction.

[0015] Optionally, the first conductive layer further includes a plurality of second conductive patterns, and adjacent first conductive patterns are coupled via at least one second conductive pattern.

[0016] Optionally, the second conductive layer includes a plurality of third conductive patterns arranged along a second direction, the third conductive pattern includes at least a portion extending along a first direction, the second direction intersecting with the first direction; the third conductive pattern includes a plurality of second hollow areas; the third conductive pattern is coupled to the corresponding conductive connection pattern.

[0017] Optionally, the third conductive pattern includes a plurality of third portions and a plurality of fourth portions, and the third portions and the fourth portions are alternately arranged along the first direction;

[0018] The width of the third portion in a direction perpendicular to the first direction is smaller than the distance between two boundaries of the fourth portion that are farthest apart in a direction perpendicular to the first direction; and the fourth portion includes the second hollow area.

[0019] Optionally, the first hollow area and the second hollow area at least partially overlap.

[0020] Optionally, the second conductive layer further includes a plurality of fourth conductive patterns, and adjacent third conductive patterns are coupled via at least one fourth conductive pattern.

[0021] Optionally, the conductive connection pattern includes a main body portion, and the main body portion is respectively coupled to the corresponding first conductive pattern and the third conductive pattern.

[0022] Optionally, the conductive connection pattern further includes at least one first extension portion extending from the main body portion.

[0023] Optionally, an orthographic projection of the first extension portion on the substrate at least partially overlaps with an orthographic projection of the second conductive layer on the substrate.

[0024] Optionally, the first extension portion is coupled to the second conductive layer through a via hole.

[0025] Optionally, the display substrate further includes:

[0026] A light shielding layer is formed into a grid structure and is coupled to the signal line film layer.

[0027] Optionally, the display substrate further comprises a peripheral signal line, wherein the peripheral signal line is located in a peripheral area of ​​the display substrate, and the peripheral signal line is coupled to the signal line film layer;

[0028] The light shielding layer includes a peripheral portion located in the peripheral area, and the peripheral portion is coupled to the peripheral signal line.

[0029] Optionally, the first conductive layer is made of a second gate metal layer, the second conductive layer is made of a second source-drain metal layer, and the conductive connection layer is made of a first source-drain metal layer.

[0030] Optionally, the conductive connection pattern includes a main body portion and a second extension portion extending from the main body portion, the main body portion includes at least a portion extending along a second direction, the second extension portion includes at least a portion extending along a first direction, and the first direction intersects with the second direction;

[0031] The display substrate also includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the corresponding second extension portion, and a second electrode of the fifth transistor is coupled to a first electrode of the driving transistor.

[0032] Optionally, the multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged along the second direction; the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits are divided into multiple sub-pixel driving circuit groups, and each sub-pixel driving circuit group includes two adjacent sub-pixel driving circuits;

[0033] The first electrodes of the two fifth transistors included in the sub-pixel driving circuit group are coupled to the corresponding second extension portion of the same conductive connection pattern.

[0034] Optionally, the sub-pixel driving circuit also includes a first transistor and a second transistor; the second electrode of the first transistor and the second electrode of the second transistor are respectively coupled to the gate of the driving transistor through a first conductive part; the main body is located between the two first conductive parts included in the corresponding sub-pixel driving circuit group.

[0035] Optionally, the main body portion includes a symmetrical figure, a symmetry axis of the symmetrical figure extends along the first direction, and the symmetry axis is located between two sub-pixel driving circuits included in the sub-pixel driving circuit group corresponding to the main body portion.

[0036] Optionally, adjacent third conductive patterns are coupled via at least one conductive connecting pattern.

[0037] Optionally, at least part of the conductive connection pattern is respectively coupled to the fourth parts included in two adjacent third conductive patterns.

[0038] Optionally, the display substrate further comprises a plurality of reset lines, a plurality of first scan lines and a plurality of second scan lines, and at least a portion of the reset lines, at least a portion of the first scan lines and at least a portion of the second scan lines extend along the second direction;

[0039] The orthographic projection of the third portion on the substrate overlaps with the orthographic projection of the corresponding reset line on the substrate, overlaps with the orthographic projection of the corresponding first scanning line on the substrate, and overlaps with the orthographic projection of the corresponding second scanning line on the substrate.

[0040] Optionally, the display substrate further includes a plurality of light emitting control lines, a plurality of third scanning lines, a first initialization signal transmission layer, a second initialization signal transmission layer and a third initialization signal transmission layer;

[0041] The orthographic projection of the fourth part on the substrate overlaps with the orthographic projection of the corresponding light-emitting control line on the substrate, overlaps with the orthographic projection of the corresponding third scanning line on the substrate, overlaps with the orthographic projection of the first initialization signal transmission layer on the substrate, overlaps with the orthographic projection of the second initialization signal transmission layer on the substrate, and overlaps with the orthographic projection of the third initialization signal transmission layer on the substrate.

[0042] Optionally, the display substrate further comprises a plurality of data lines, and the data lines include at least a portion extending along the first direction;

[0043] The display substrate further comprises a plurality of sub-pixels, wherein the sub-pixels comprise a sub-pixel driving circuit, wherein the sub-pixel driving circuit comprises a driving transistor, a fourth transistor and a fifth transistor, wherein the fourth transistor is respectively coupled to a first electrode of the first transistor and a corresponding data line, and the fifth transistor is respectively coupled to a first electrode of the driving transistor and a corresponding conductive connection pattern;

[0044] The fourth transistor includes a fourth active layer, the fifth transistor includes a fifth active layer, and an orthographic projection of the fourth portion on the substrate does not overlap with an orthographic projection of the fourth active layer on the substrate, and does not overlap with an orthographic projection of the fifth active layer on the substrate.

[0045] Optionally, the display substrate further includes a second initialization signal transmission layer;

[0046] The display substrate further includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor, a sixth transistor, a seventh transistor, and a light-emitting element, wherein the sixth transistor is respectively coupled to the second electrode of the driving transistor and the light-emitting element, and the seventh transistor is respectively coupled to the light-emitting element and the second initialization signal transmission layer;

[0047] The sixth transistor includes a sixth active layer, the seventh transistor includes a seventh active layer, and the orthographic projection of the fourth portion on the substrate surrounds at least a portion of the orthographic projection of the seventh active layer on the substrate and also surrounds the orthographic projection of the sixth active layer on the substrate.

[0048] Optionally, the display substrate further includes a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor, and an orthographic projection of a gate of the driving transistor on the substrate partially overlaps with an orthographic projection of the fourth portion on the substrate.

[0049] Optionally, the display substrate further includes a third initialization signal transmission layer;

[0050] The display substrate further includes a plurality of sub-pixels, each of the sub-pixels includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and an eighth transistor, a first electrode of the eighth transistor is coupled to the third initialization signal transmission layer, and a second electrode of the eighth transistor is coupled to the first electrode or the second electrode of the driving transistor;

[0051] The eighth transistor includes an eighth active layer, and an orthographic projection of the eighth active layer on the substrate at least partially overlaps with an orthographic projection of the fourth portion on the substrate.

[0052] Optionally, the display substrate further comprises a plurality of data lines, and the data lines include at least a portion extending along the first direction;

[0053] There are two data lines between adjacent third conductive patterns.

[0054] Optionally, the display substrate also includes a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and a storage capacitor, the gate of the driving transistor is multiplexed as the first substrate of the storage capacitor, and the second part is multiplexed as the second plate of the storage capacitor.

[0055] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0057] Figure 1 A first circuit schematic diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0058] Figure 2 A first structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0059] Figure 3 A schematic diagram of a target transmission unit and a non-target transmission unit provided by an embodiment of the present disclosure;

[0060] Figure 4 A second circuit schematic diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0061] Figure 5 A second structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0062] Figure 6 A third structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0063] Figure 7 A third circuit schematic diagram of the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0064] Figure 8 A fourth structural schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0065] Fig. 9 A timing diagram of charging the N1 node by the first initialization signal transmission layer provided in an embodiment of the present disclosure;

[0066] Fig.10 A schematic diagram of the reset speed of the grid-shaped initialization signal transmission layer provided in the embodiment of the present disclosure and the existing initialization signal transmission layer for anode reset;

[0067] Fig.11A schematic diagram of a first layout of sub-pixels provided in an embodiment of the present disclosure;

[0068] Fig.12 A second schematic diagram of the layout of sub-pixels provided in an embodiment of the present disclosure;

[0069] Fig.13 A schematic diagram of the layout of two adjacent sub-pixels provided in an embodiment of the present disclosure;

[0070] Fig.14 for Fig.13 Schematic diagram of the layout of the light shielding layer;

[0071] Fig.15 for Fig.13 Schematic diagram of the layout of the poly active layer;

[0072] Fig.16 for Fig.13 A schematic diagram of the layout of the first gate metal layer;

[0073] Fig.17 for Fig.13 A schematic diagram of the layout of the second gate metal layer;

[0074] Fig.18 for Fig.13 A schematic diagram of the layout of the first connecting hole in FIG.

[0075] Fig.19 for Fig.13 A schematic diagram of the layout of the second connecting hole in FIG.

[0076] Fig. 20 for Fig.13 Schematic diagram of the layout of the third gate metal layer;

[0077] Fig.21 for Fig.13 Schematic diagram of the layout of the oxide active layer;

[0078] Fig. 22 for Fig.13 A schematic diagram of the layout of the first source and drain metal layer;

[0079] Fig.23 for Fig.13 A schematic diagram of the layout of vias formed in the first flat layer;

[0080] Fig.24 for Fig.13 A schematic diagram of the layout of the second source and drain metal layer;

[0081] Fig.25 for Fig.13 Schematic diagram of the layout of the vias formed in the second flat layer.

[0082] Fig.26A schematic diagram of the layout of the second source-drain metal layer and the anode layer provided in an embodiment of the present disclosure;

[0083] Fig. 27 A schematic diagram of the layout of the anode layer provided in an embodiment of the present disclosure;

[0084] Fig.28 A schematic diagram of the layout of pixel openings provided in an embodiment of the present disclosure;

[0085] Fig.29a A layout of sub-pixels provided in an embodiment of the present disclosure;

[0086] Fig.29b Another layout of sub-pixels provided in the embodiment of the present disclosure;

[0087] Fig.30 A driving timing diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0088] Fig.31a for Fig.13 Schematic diagram of the layout of the poly active layer and the first gate metal layer;

[0089] Fig.31b for Fig.13 A schematic diagram of the layout of the middle oxide active layer and the second gate metal layer and the third gate metal layer;

[0090] Fig.32 A first schematic diagram of a signal line film layer provided in an embodiment of the present disclosure;

[0091] Fig.33 A second schematic diagram of a signal line film layer provided in an embodiment of the present disclosure;

[0092] Fig.34 A third schematic diagram of a signal line film layer provided in an embodiment of the present disclosure;

[0093] Fig.35 A fourth schematic diagram of a signal line film layer provided by an embodiment of the present disclosure;

[0094] Fig.36 for Fig.35 Schematic diagram of the layout of the middle shading layer;

[0095] Fig.37 A fifth schematic diagram of a signal line film layer provided in an embodiment of the present disclosure;

[0096] Fig.38 for Fig.37 A schematic diagram of the layout of the conductive connection pattern;

[0097] Fig.39 A schematic diagram of the layout of a display substrate provided in an embodiment of the present disclosure;

[0098] Fig.40 for Fig.39 Schematic diagram of the layout of the middle shading layer;

[0099] Fig.41 for Fig.39 Schematic diagram of the layout of the poly active layer;

[0100] Fig.42 for Fig.39 A schematic diagram of the layout of the first gate metal layer;

[0101] Fig.43 for Fig.39 A schematic diagram of the layout of the second gate metal layer;

[0102] Fig.44 for Fig.39 A schematic diagram of the layout of the first connecting hole in FIG.

[0103] Fig.45 for Fig.39 Schematic diagram of the layout of the oxide active layer in FIG.

[0104] Fig.46 for Fig.39 A schematic diagram of the layout of the second connecting hole in FIG.

[0105] Fig.47 for Fig.39 A schematic diagram of the layout of the third gate metal layer in FIG.

[0106] Fig.48 for Fig.39 A schematic diagram of the layout of the first source and drain metal layer in FIG.

[0107] Fig.49 for Fig.39 A schematic diagram of the layout of vias formed in the first flat layer;

[0108] Fig.50 for Fig.39 A schematic diagram of the layout of the second source and drain metal layer in FIG.

[0109] Fig.51 for Fig.39 A schematic diagram of the layout of the first source-drain metal layer and the second source-drain metal layer;

[0110] Fig.52 A schematic cross-sectional view of a display substrate provided in an embodiment of the present disclosure;

[0111] Fig.53 Another schematic diagram of the layout of a display substrate provided in an embodiment of the present disclosure;

[0112] Fig.54 A schematic diagram of a conductive connection pattern provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below in conjunction with the accompanying drawings.

[0114] In the related art, some signal line film layers have a large voltage drop when transmitting signals, resulting in the display product being unable to meet the screen performance requirements in high-brightness display mode, resulting in poor display uniformity.

[0115] See also Figure 32 to Figure 37 The embodiment of the present disclosure provides a display substrate, comprising: a substrate and a signal line film layer arranged on the substrate; the signal line film layer comprises:

[0116] A first conductive layer (including a first conductive pattern 70 and a second conductive pattern 71) and a second conductive layer (including a third conductive pattern 72) are stacked; and

[0117] A conductive connection layer (including a conductive connection pattern 74), wherein the conductive connection layer and the first conductive layer and the second conductive layer are arranged in different layers, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate, and the conductive connection layer is coupled to the first conductive layer and the second conductive connection layer respectively.

[0118] Exemplarily, the signal line film layer is used to transmit a DC signal with a fixed potential.

[0119] Exemplarily, the signal line film layer includes a positive power signal line film layer (ie, a power line VDD), and the positive power signal line film layer is used to transmit a positive power signal.

[0120] Exemplarily, at least a portion of the conductive connection layer is located between the first conductive layer and the second conductive layer.

[0121] Exemplarily, the first conductive layer, the second conductive layer and the conductive connection layer are all made of metal materials.

[0122] Exemplarily, the first conductive layer and the second conductive layer are both formed into a grid structure.

[0123] Exemplarily, an orthographic projection of the conductive connection layer on the substrate and an orthographic projection of the first conductive layer on the substrate have an overlapping region, and in the overlapping region, the conductive connection layer and the first conductive layer are coupled through at least one via.

[0124] Exemplarily, an orthographic projection of the conductive connection layer on the substrate and an orthographic projection of the second conductive layer on the substrate have an overlapping region, and in the overlapping region, the conductive connection layer and the second conductive layer are coupled through at least one via.

[0125] According to the specific structure of the display substrate provided by the embodiment of the present disclosure, in the display substrate provided by the embodiment of the present disclosure, the signal line film layer is provided to include a first conductive layer, a conductive connection layer, and a second conductive layer that are stacked. This arrangement enables the signal line film layer to be formed into a multi-layer network stacking structure, which effectively reduces the voltage drop generated when the signal line film layer transmits a signal. When the display substrate is applied to a display product, the uniformity of the display of the display product in a high-brightness display mode is ensured. Moreover, forming the signal line film layer into a multi-layer network stacking structure helps to dissipate heat from the display product in a high-brightness display mode.

[0126] See also Figure 32 to Figure 38 , in some embodiments, the conductive connection layer includes a plurality of conductive connection patterns 74;

[0127] The first conductive layer includes a plurality of first conductive patterns 70 arranged along a first direction; the first conductive pattern 70 includes at least a portion extending along a second direction, the second direction intersects with the first direction, and the first conductive pattern 70 includes a plurality of first hollow areas 703; the first conductive pattern 70 is coupled to the corresponding conductive connection pattern 74.

[0128] Exemplarily, the conductive connection layer includes a plurality of conductive connection patterns 74, and the plurality of conductive connection patterns 74 are independent of each other.

[0129] Exemplarily, the plurality of conductive connection patterns 74 are distributed in an array.

[0130] Exemplarily, the structures of the plurality of conductive connection patterns 74 are completely the same.

[0131] Exemplarily, among the plurality of conductive connection patterns 74 , at least some of the conductive connection patterns 74 have different shapes.

[0132] Exemplarily, the display substrate includes a display area and a peripheral area surrounding the display area. The display area is divided into a plurality of display sub-areas, and the plurality of display sub-areas correspond to the plurality of conductive connection patterns 74 one by one, and the conductive connection patterns 74 are located in the corresponding display sub-areas.

[0133] Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0134] like Fig.39 and Fig.52As shown, illustratively, the display substrate includes a plurality of gate lines and a plurality of data lines D1, the gate lines include at least a portion extending along the second direction, and the data lines D1 include at least a portion extending along the first direction.

[0135] Exemplarily, the display substrate includes a plurality of sub-pixels, and the sub-pixels include sub-pixel driving circuits. The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits arranged along a first direction. The first conductive layer includes a plurality of first conductive patterns 70 arranged along the first direction. The plurality of first conductive patterns 70 correspond one-to-one to the plurality of rows of sub-pixel driving circuits.

[0136] Exemplarily, the first conductive pattern 70 is arranged in a layout area where a corresponding sub-pixel driving circuit row is located.

[0137] Exemplarily, each of the first conductive patterns 70 corresponds to at least one conductive connection pattern 74 , and the first conductive pattern 70 is coupled to the corresponding conductive connection pattern 74 .

[0138] Exemplarily, each of the first conductive patterns 70 corresponds to a plurality of conductive connection patterns 74, and the first conductive patterns 70 are respectively coupled to the corresponding plurality of conductive connection patterns 74. Exemplarily, the plurality of conductive connection patterns 74 are arranged at intervals along the second direction.

[0139] Exemplarily, the first conductive pattern 70 includes a plurality of first hollow areas 703 . The sub-pixel driving circuit includes a first node. The first node is located in the first hollow area 703 .

[0140] Exemplarily, the orthographic projection of the boundary of the first hollow area 703 on the substrate 60 surrounds the orthographic projection of the first node on the substrate 60. The first node can pass through the hollow area to couple with other conductive structures.

[0141] In the display substrate provided in the above embodiment, the first conductive layer is provided to include a plurality of first conductive patterns 70 arranged along a first direction, the first conductive pattern 70 is coupled to the corresponding conductive connection pattern 74, and the first conductive pattern 70 includes a plurality of first hollow areas 703; so that the first conductive layer is formed into a grid structure, thereby effectively reducing the voltage drop generated when the signal line film layer transmits a signal. When the display substrate is applied to a display product, the uniformity of the display product in a high-brightness display mode is ensured. Moreover, forming the first conductive layer into a grid structure is helpful for heat dissipation of the display product in a high-brightness display mode.

[0142] See also Figure 32 to Figure 38 , Fig.52In some embodiments, the first conductive pattern 70 includes a plurality of first portions 701 and a plurality of second portions 702, and the first portions 701 and the second portions 702 are alternately arranged along the second direction;

[0143] The width of the first portion 701 in the direction perpendicular to the second direction is smaller than the distance between two boundaries of the second portion 702 which are farthest apart in the direction perpendicular to the second direction; the second portion 702 includes the first hollow area 703 .

[0144] Exemplarily, the first part 701 and the second part 702 are formed as an integral structure.

[0145] Exemplarily, the first portion 701 includes a strip-shaped pattern extending along the second direction.

[0146] Exemplarily, the second portion 702 includes a block-shaped graphic.

[0147] Exemplarily, an orthographic projection of the first portion 701 on the substrate 60 does not overlap with an orthographic projection of the second conductive layer on the substrate 60 .

[0148] Illustratively, an orthographic projection of the first portion 701 on the substrate 60 at least partially overlaps with an orthographic projection of the second conductive layer on the substrate 60 .

[0149] Illustratively, an orthographic projection of the second portion 702 on the substrate 60 at least partially overlaps with an orthographic projection of the second conductive layer on the substrate 60 .

[0150] Exemplarily, an orthographic projection of the first portion 701 on the substrate 60 and an orthographic projection of a corresponding conductive connection pattern 74 on the substrate 60 have an overlapping region, and in the overlapping region, the first portion 701 is coupled to the corresponding conductive connection pattern 74 .

[0151] Exemplarily, an orthographic projection of the second portion 702 on the substrate 60 and an orthographic projection of a corresponding conductive connection pattern 74 on the substrate 60 have an overlapping region, and in the overlapping region, the second portion 702 is coupled to the corresponding conductive connection pattern 74 .

[0152] Exemplarily, the width of the first portion 701 in the direction perpendicular to the second direction is smaller than the minimum distance between two boundaries of the second portion 702 that are farthest apart in the direction perpendicular to the second direction.

[0153] Exemplarily, the width of the first portion 701 in the direction perpendicular to the second direction is smaller than the maximum distance between two boundaries of the second portion 702 that are farthest apart in the direction perpendicular to the second direction.

[0154] In the display substrate provided in the above embodiment, the first conductive pattern 70 is arranged to include a plurality of first parts 701 and a plurality of second parts 702, and the first parts 701 and the second parts 702 are alternately arranged along the second direction; and the width of the first part 701 in a direction perpendicular to the second direction is set to be smaller than the distance between the two boundaries of the second part 702 in a direction perpendicular to the second direction that are farthest apart; so that the first conductive layer effectively utilizes the limited layout space while avoiding a short circuit with the surrounding conductive structure, better realizes the gridding of the first conductive layer, and greatly reduces the voltage drop generated when the first conductive layer transmits a signal.

[0155] In the display substrate provided by the above embodiment, by setting the width of the first part 701 in the direction perpendicular to the second direction to be smaller than the distance between the two farthest boundaries of the second part 702 in the direction perpendicular to the second direction; the second part 702 includes the first hollow area 703; not only can a larger hollow area be formed, but also the difficulty of forming the hollow area can be effectively reduced.

[0156] See also Figure 32 to Figure 38 In some embodiments, the multiple first parts 701 include multiple first target parts 7011 and multiple second target parts 7012, the first target parts 7011 and the second target parts 7012 are alternately arranged, the width of the first target part 7011 in a direction perpendicular to the second direction is greater than the width of the second target part 7012 in a direction perpendicular to the second direction; the first target part 7011 is coupled to the corresponding conductive connection pattern 74.

[0157] Exemplarily, the second conductive layer includes a plurality of third conductive patterns 72 arranged along the second direction, the third conductive pattern 72 includes at least a portion extending along the first direction, and the third conductive pattern 72 includes a plurality of second hollow areas 721. The orthographic projection of the boundary of the second hollow area 721 on the substrate 60 surrounds the orthographic projection of the second target portion 7012 on the substrate 60.

[0158] Exemplarily, the orthographic projection of the second hollow area 721 on the substrate 60 does not overlap with the orthographic projection of the first target portion 7011 on the substrate 60 .

[0159] Exemplarily, the orthographic projection of the second hollow area 721 on the substrate 60 at least partially overlaps with the orthographic projection of the second target portion 7012 on the substrate 60 .

[0160] Illustratively, the first hollow area 703 and the second hollow area 721 at least partially overlap.

[0161] Illustratively, the first target portion 7011 or the second target portion 7012 is disposed between adjacent second portions 702 .

[0162] Exemplarily, the second part 702 is disposed between adjacent first target parts 7011 and second target parts 7012 .

[0163] Illustratively, in the same first conductive pattern 70 , the first target portion 7011 , the second portion 702 , the second target portion 7012 and the second portion 702 arranged in sequence constitute a repeating unit, and the first conductive pattern 70 includes a plurality of the repeating units.

[0164] Exemplarily, the orthographic projection of the first target portion 7011 on the substrate 60 and the orthographic projection of the corresponding conductive connection pattern 74 on the substrate 60 have an overlapping area, and in the overlapping area, the first target portion 7011 is coupled to the corresponding conductive connection pattern 74 through a via.

[0165] In the display substrate provided by the above embodiment, the multiple first parts 701 are arranged to include multiple first target parts 7011 and multiple second target parts 7012, the first target parts 7011 and the second target parts 7012 are alternately arranged, and the width of the first target part 7011 in a direction perpendicular to the second direction is greater than the width of the second target part 7012 in a direction perpendicular to the second direction; so that the first conductive layer can effectively utilize the limited layout space while avoiding short circuit with the surrounding conductive structure, better realize the gridding of the first conductive layer, and greatly reduce the voltage drop generated when the first conductive layer transmits signals.

[0166] In the display substrate provided by the above embodiment, by setting the first target portion 7011 to be coupled with the corresponding conductive connection pattern 74 , the stability and reliability of the electrical connection performance between the first conductive layer and the conductive connection pattern 74 can be well guaranteed.

[0167] See also Figure 32 to Figure 38 In some embodiments, the first target portion 7011 and the second target portion 7012 are arranged to be staggered along the first direction.

[0168] The above configuration makes it possible for the first conductive layer to effectively utilize limited layout space while avoiding short circuit with surrounding conductive structures, better realizes the gridding of the first conductive layer, and effectively reduces the voltage drop generated when the first conductive layer transmits signals.

[0169] See also Fig.33 In some embodiments, the first conductive layer further includes a plurality of second conductive patterns 71 , and adjacent first conductive patterns 70 are coupled via at least one second conductive pattern 71 .

[0170] Exemplarily, the second conductive pattern 71 includes at least a portion extending along the first direction.

[0171] Exemplarily, the second conductive pattern 71 is formed as a strip structure.

[0172] Exemplarily, the second conductive pattern 71 and the first conductive pattern 70 are formed into an integral structure.

[0173] Exemplarily, the second conductive patterns 71 located in the same column along the first direction are coupled in sequence to form an integrated structure.

[0174] Exemplarily, adjacent first conductive patterns 70 are coupled via a plurality of second conductive patterns 71 .

[0175] Exemplarily, an orthographic projection of the second conductive pattern 71 on the substrate 60 at least partially overlaps with an orthographic projection of the conductive connection pattern 74 on the substrate 60 .

[0176] Exemplarily, an orthographic projection of the second conductive pattern 71 on the substrate 60 at least partially overlaps with an orthographic projection of the first portion 701 on the substrate 60 .

[0177] Exemplarily, an orthographic projection of the second conductive pattern 71 on the substrate 60 at least partially overlaps with an orthographic projection of the first target portion 7011 on the substrate 60 .

[0178] Exemplarily, the orthographic projection of the second conductive pattern 71 on the substrate 60 does not overlap with the orthographic projection of the second target portion 7012 on the substrate 60 .

[0179] Exemplarily, the orthographic projection of the second conductive pattern 71 on the substrate 60 does not overlap with the orthographic projection of the second portion 702 on the substrate 60 .

[0180] Exemplarily, the second conductive pattern 71 can be made of an oxide active layer (such as an IGZO film layer), and the oxide active layer can be formed into a conductor through a conductorization process, so as to transmit a positive power signal.

[0181] In the display substrate provided in the above embodiment, the first conductive layer is provided to further include a plurality of second conductive patterns 71, and adjacent first conductive patterns 70 are coupled by at least one second conductive pattern 71, thereby further expanding the grid veins of the first conductive layer. The voltage drop generated when the signal line film layer transmits a signal is effectively reduced. When the display substrate is applied to a display product, the uniformity of the display product in a high-brightness display mode is ensured. Moreover, the signal line film layer is formed into a multi-layer network stacking structure, which helps to dissipate heat of the display product in a high-brightness display mode.

[0182] See also Figure 32 to Figure 38 , in some embodiments, the conductive connection layer includes a plurality of conductive connection patterns 74;

[0183] The second conductive layer includes a plurality of third conductive patterns 72 arranged along a second direction, the third conductive pattern 72 includes at least a portion extending along a first direction, and the second direction intersects with the first direction; the third conductive pattern 72 includes a plurality of second hollow areas 721; the third conductive pattern 72 is coupled to the corresponding conductive connection pattern 74.

[0184] Exemplarily, the conductive connection layer includes a plurality of conductive connection patterns 74, and the plurality of conductive connection patterns 74 are independent of each other.

[0185] Exemplarily, the plurality of conductive connection patterns 74 are distributed in an array.

[0186] Exemplarily, the structures of the plurality of conductive connection patterns 74 are completely the same.

[0187] Exemplarily, among the plurality of conductive connection patterns 74 , at least some of the conductive connection patterns 74 have different shapes.

[0188] Exemplarily, the display substrate includes a display area and a peripheral area surrounding the display area. The display area is divided into a plurality of display sub-areas, and the plurality of display sub-areas correspond to the plurality of conductive connection patterns 74 one by one, and the conductive connection patterns 74 are located in the corresponding display sub-areas.

[0189] Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0190] Exemplarily, the display substrate includes a plurality of gate lines and a plurality of data lines D1 , the gate lines include at least a portion extending along the second direction, and the data lines D1 include at least a portion extending along the first direction.

[0191] Exemplarily, the display substrate includes a plurality of sub-pixels, and the sub-pixels include sub-pixel driving circuits. The plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of sub-pixel driving circuit columns arranged along the second direction. The second conductive layer includes a plurality of third conductive patterns 72 arranged along the second direction. The plurality of third conductive patterns 72 correspond one-to-one to the plurality of sub-pixel driving circuit columns.

[0192] Exemplarily, at least a portion of the third conductive pattern 72 is arranged within a layout area where a corresponding sub-pixel driving circuit column is located.

[0193] Exemplarily, each of the third conductive patterns 72 corresponds to at least one conductive connection pattern 74 , and the third conductive pattern 72 is coupled to the corresponding conductive connection pattern 74 .

[0194] Exemplarily, each of the third conductive patterns 72 corresponds to a plurality of conductive connection patterns 74, and the third conductive patterns 72 are respectively coupled to the corresponding plurality of conductive connection patterns 74. Exemplarily, the third conductive patterns 72 are respectively coupled to the corresponding plurality of conductive connection patterns 74 through vias. Exemplarily, the plurality of conductive connection patterns 74 are arranged at intervals along the first direction.

[0195] Exemplarily, adjacent third conductive patterns 72 are electrically connected via at least one conductive connecting pattern 74 .

[0196] Exemplarily, adjacent third conductive patterns 72 are electrically connected via a plurality of conductive connection patterns 74. The plurality of conductive connection patterns 74 are arranged at intervals along the first direction.

[0197] In the display substrate provided in the above embodiment, the second conductive layer is provided to include a plurality of third conductive patterns 72 arranged along the second direction, and the third conductive pattern 72 includes a plurality of second hollow areas 721; the third conductive pattern 72 is coupled with the corresponding conductive connection pattern 74; so that the second conductive layer is formed into a grid structure, thereby effectively reducing the voltage drop generated when the signal line film layer transmits the signal. When the display substrate is applied to a display product, the uniformity of the display product in a high-brightness display mode is ensured. Moreover, forming the first conductive layer into a grid structure is helpful for heat dissipation of the display product in a high-brightness display mode.

[0198] In some embodiments, the first hollow area 703 and the second hollow area 721 are arranged to at least partially overlap.

[0199] The above configuration is beneficial to improving the transmittance of the display substrate.

[0200] See also Figure 32 to Figure 38In some embodiments, the third conductive pattern 72 includes a plurality of third portions 722 and a plurality of fourth portions 723, and the third portions 722 and the fourth portions 723 are alternately arranged along the first direction;

[0201] The width of the third portion 722 in the direction perpendicular to the first direction is smaller than the distance between two boundaries of the fourth portion 723 that are farthest apart in the direction perpendicular to the first direction; the fourth portion 723 includes the second hollow area 721 .

[0202] Exemplarily, the third portion 722 and the fourth portion 723 are formed as an integral structure.

[0203] Exemplarily, the fourth portion 723 includes a strip-shaped pattern extending at least partially along the first direction.

[0204] Exemplarily, the third portion 722 includes a block-shaped graphic.

[0205] Exemplarily, an orthographic projection of the third portion 722 on the substrate 60 does not overlap with an orthographic projection of the first conductive layer on the substrate 60 .

[0206] Illustratively, an orthographic projection of the third portion 722 on the substrate 60 at least partially overlaps with an orthographic projection of the first conductive layer on the substrate 60 .

[0207] Illustratively, an orthographic projection of the fourth portion 723 on the substrate 60 at least partially overlaps with an orthographic projection of the second conductive layer on the substrate 60 .

[0208] Exemplarily, an orthographic projection of the third portion 722 on the substrate 60 and an orthographic projection of a corresponding conductive connection pattern 74 on the substrate 60 have an overlapping region, and in the overlapping region, the third portion 722 is coupled to the corresponding conductive connection pattern 74 .

[0209] Exemplarily, an orthographic projection of the fourth portion 723 on the substrate 60 and an orthographic projection of a corresponding conductive connection pattern 74 on the substrate 60 have an overlapping region, and in the overlapping region, the fourth portion 723 is coupled to the corresponding conductive connection pattern 74 .

[0210] Exemplarily, the width of the third portion 722 in the direction perpendicular to the first direction is smaller than the minimum distance between two boundaries of the fourth portion 723 that are farthest apart in the direction perpendicular to the first direction.

[0211] Exemplarily, the width of the third portion 722 in the direction perpendicular to the first direction is smaller than the maximum distance between two boundaries of the fourth portion 723 that are farthest apart in the direction perpendicular to the first direction.

[0212] In the display substrate provided in the above embodiment, the third conductive pattern 72 is arranged to include a plurality of third parts 722 and a plurality of fourth parts 723, and the third parts 722 and the fourth parts 723 are alternately arranged along the first direction; and the width of the third part 722 in a direction perpendicular to the first direction is set to be smaller than the distance between the two farthest boundaries of the fourth part 723 in a direction perpendicular to the first direction; so that the second conductive layer can effectively utilize the limited layout space while avoiding a short circuit with the surrounding conductive structure, better realize the gridding of the second conductive layer, and greatly reduce the voltage drop generated when the second conductive layer transmits signals.

[0213] In the display substrate provided by the above embodiment, by setting the width of the third part 722 in the direction perpendicular to the first direction to be smaller than the distance between the two farthest boundaries of the fourth part 723 in the direction perpendicular to the first direction; the fourth part 723 includes the second hollow area 721; not only can a larger hollow area be formed, but also the difficulty of forming the hollow area can be effectively reduced.

[0214] like Fig.34 As shown, in some embodiments, the second conductive layer further includes a plurality of fourth conductive patterns 73 , and adjacent third conductive patterns 72 are coupled via at least one fourth conductive pattern 73 .

[0215] Exemplarily, the fourth conductive pattern 73 and the third conductive pattern 72 form an integrated structure.

[0216] Exemplarily, the fourth conductive pattern 73 includes a strip-shaped pattern extending along the second direction.

[0217] Exemplarily, adjacent third conductive patterns 72 are coupled via a plurality of fourth conductive patterns 73 , and the plurality of fourth conductive patterns 73 are arranged at intervals along the first direction.

[0218] Exemplarily, the fourth conductive patterns 73 and the conductive connection patterns 74 are alternately arranged along the first direction.

[0219] Exemplarily, an orthographic projection of the fourth conductive pattern 73 on the substrate 60 at least partially overlaps with an orthographic projection of the conductive connection pattern 74 on the substrate 60 .

[0220] Exemplarily, the orthographic projection of the fourth conductive pattern 73 on the substrate 60 does not overlap with the orthographic projection of the conductive connection pattern 74 on the substrate 60 .

[0221] Exemplarily, an orthographic projection of the fourth conductive pattern 73 on the substrate 60 at least partially overlaps with an orthographic projection of the second conductive pattern 71 on the substrate 60 .

[0222] Exemplarily, an orthographic projection of the fourth conductive pattern 73 on the substrate 60 does not overlap with an orthographic projection of the first conductive pattern 70 on the substrate 60 .

[0223] In the display substrate provided in the above embodiment, the second conductive layer is provided to further include a plurality of fourth conductive patterns 73, and the adjacent third conductive patterns 72 are coupled by at least one fourth conductive pattern 73; the grid veins of the second conductive layer are further expanded. The voltage drop generated when the signal line film layer transmits the signal is effectively reduced. When the display substrate is applied to a display product, the uniformity of the display product in a high-brightness display mode is ensured. Moreover, the signal line film layer is formed into a multi-layer network stacking structure, which helps to dissipate heat of the display product in a high-brightness display mode.

[0224] See also Figure 32 to Figure 36 In some embodiments, the conductive connection pattern 74 includes a main body portion 741, and the main body portion 741 is respectively coupled to the corresponding first conductive pattern 70 and the third conductive pattern 72.

[0225] Exemplarily, the main body 741 includes a block-shaped pattern.

[0226] Exemplarily, the orthographic projection of the main body 741 on the substrate 60 at least partially overlaps with the orthographic projection of the first conductive pattern 70 on the substrate 60. The orthographic projection of the main body 741 on the substrate 60 at least partially overlaps with the orthographic projection of the third conductive pattern 72 on the substrate 60.

[0227] Exemplarily, the main body 741 is coupled to the corresponding first conductive pattern 70 and the third conductive pattern 72 through vias.

[0228] like Fig.37 and Fig.38 As shown, in some embodiments, the conductive connection pattern 74 further includes at least one first extension portion 742 extending from the main body portion 741 .

[0229] Exemplarily, the main body portion 741 and the first extension portion 742 are formed as an integral structure.

[0230] Illustratively, the first extension portion 742 includes at least a portion extending along the first direction.

[0231] Exemplarily, the conductive connection pattern 74 includes four first extension portions 742 .

[0232] In the display substrate provided in the above embodiment, the conductive connection pattern 74 further includes at least one first extension portion 742 extending from the main body portion 741 , so that the conductive connection pattern 74 has multiple branch lines, which helps the conductive connection pattern 74 to dissipate heat.

[0233] like Fig.54 As shown, in some embodiments, the conductive connection pattern 74 further includes a first extension portion 742, and the first extension portion 742 is made of an oxide active layer (such as an IGZO film layer). The oxide active layer can be formed into a conductor through a conductorization process. The two ends of the first extension portion formed by the conductorized oxide active layer can be electrically connected to the main body (made of the first source and drain metal layer) and the third conductive pattern 72 (made of the second source and drain metal layer) through vias, respectively, to achieve transmission of the positive power supply signal.

[0234] like Fig.51 and Fig.54 As shown, illustratively, the conductive connection pattern 74 further includes a connection portion 744 , and the first extension portion 742 is coupled to the connection portion 744 through a via Via.

[0235] Exemplarily, the connection portion 744 and the main body portion 741 are provided in the same layer and with the same material.

[0236] The above-mentioned use of the conductive oxide active layer to form the first extension portion can well avoid the first conductive portion 81 and the seventh conductive portion 87, which is beneficial to improving the yield of the display substrate.

[0237] like Fig.37 and Fig.38 As shown, in some embodiments, the orthographic projection of the first extension portion 742 on the substrate 60 at least partially overlaps with the orthographic projection of the second conductive layer on the substrate 60 .

[0238] Illustratively, the orthographic projection of the first extension portion 742 on the substrate 60 is located inside the orthographic projection of the second conductive layer on the substrate 60 .

[0239] Exemplarily, the orthographic projection of the first extension portion 742 on the substrate 60 does not overlap with the orthographic projection of the second conductive pattern 71 on the substrate 60 .

[0240] Exemplarily, an orthographic projection of a portion of the first extension portion 742 on the substrate 60 at least partially overlaps with an orthographic projection of the first conductive pattern 70 on the substrate 60 .

[0241] In the display substrate provided in the above embodiment, by arranging the orthographic projection of the first extension portion 742 on the substrate 60 to at least partially overlap with the orthographic projection of the second conductive layer on the substrate 60 , the layout difficulty of the first extension portion 742 is effectively reduced.

[0242] like Fig.37 and Fig.38 As shown, in some embodiments, the first extension portion 742 is coupled to the second conductive layer through a via.

[0243] Exemplarily, an orthographic projection of the first extension portion 742 on the substrate 60 and an orthographic projection of the second conductive layer on the substrate 60 have an overlapping region, and in the overlapping region, the first extension portion 742 is coupled to the second conductive layer through a via.

[0244] The above arrangement of coupling the first extension portion 742 to the second conductive layer through the via hole increases the area of ​​the second conductive layer at the via hole, thereby effectively reducing the voltage drop of the signal line film layer.

[0245] like Fig.35 and Fig.36 As shown, in some embodiments, the display substrate further includes:

[0246] The light shielding layer LS is formed into a grid structure, and the light shielding layer LS is coupled to the signal line film layer.

[0247] Exemplarily, the light shielding layer is located between the sub-pixel driving circuit and the substrate 60. The sub-pixel driving circuit includes a driving transistor (such as a third transistor T3), and the orthographic projection of the light shielding layer on the substrate 60 at least partially overlaps with the orthographic projection of the channel portion of the driving transistor on the substrate 60. This arrangement enables the light shielding layer to block light from the side of the substrate 60 to the channel portion, thereby ensuring the stability of the characteristics of the driving transistor.

[0248] By setting the light shielding layer to be coupled with the signal line film layer, the light shielding layer has a stable potential, so that the light shielding layer can just shield the influence of peripheral charges on the channel part, thereby ensuring the stability of the characteristics of the driving transistor.

[0249] By setting the light shielding layer to couple with the signal line film layer, it is equivalent to further expanding the grid structure of the signal line film layer at another spatial level, effectively reducing the voltage drop generated when the signal line film layer transmits signals. When the display substrate is applied to display products, the uniformity of the display of the display product in high-brightness display mode is guaranteed. Moreover, the signal line film layer is formed into a multi-layer network stacking structure, which helps to dissipate heat of the display product in high-brightness display mode.

[0250] In some embodiments, the display substrate further includes a peripheral signal line, the peripheral signal line is located in a peripheral area of ​​the display substrate, and the peripheral signal line is coupled to the signal line film layer;

[0251] The light shielding layer includes a peripheral portion located in the peripheral area, and the peripheral portion is coupled to the peripheral signal line.

[0252] Exemplarily, the display substrate further includes a driving chip, the peripheral signal line is coupled to the driving chip, the peripheral signal line is also coupled to the signal line film layer, and the peripheral signal line is used to transmit the signal provided by the driving chip to the signal line film layer.

[0253] Exemplarily, the orthographic projection of the peripheral signal line on the substrate 60 has an overlapping area with the orthographic projection of the peripheral portion of the light shielding layer on the substrate 60, and in the overlapping area, the peripheral signal line is coupled to the peripheral portion of the light shielding layer through a via. The light shielding layer LS is coupled to the signal line film layer in the peripheral area through the peripheral signal line.

[0254] In some embodiments, the first conductive layer is made of a second gate metal layer, the second conductive layer is made of a second source-drain metal layer, and the conductive connection layer is made of a first source-drain metal layer.

[0255] like Fig.52 As shown, exemplarily, the display substrate includes: a first buffer layer Buf, a light shielding layer LS, an isolation layer Bar, a poly active layer POL, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a first interlayer insulating layer ILD, a second buffer layer, an oxide active layer (such as IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source and drain metal layer SD1, a passivation layer PVX, a first planarizing layer PLN1, a second source and drain metal layer SD2, a second planarizing layer PLN2, an anode layer 50, a pixel defining layer PDL, a spacer layer PS, a light-emitting functional layer, a cathode layer and an encapsulation layer.

[0256] In the display substrate provided in the above embodiment, by setting the first conductive layer to be made of the second gate metal layer, the second conductive layer to be made of the second source and drain metal layer, and the conductive connection layer to be made of the first source and drain metal layer, it is possible to utilize the existing film layer in the display substrate to manufacture the signal line film layer without adding additional patterning processes, thereby effectively simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0257] In the display substrate provided in the above embodiment, the first conductive layer is made of the second gate metal layer, the second conductive layer is made of the second source-drain metal layer, the conductive connection layer is made of the first source-drain metal layer, and the conductive connection layer serves as a bridge to be coupled to the second conductive layer through vias penetrating the passivation layer and the first planar layer, and to be coupled to the first conductive layer through vias penetrating the first interlayer insulating layer, the second buffer layer, the third gate insulating layer and the second interlayer insulating layer.

[0258] Exemplarily, the display substrate undergoes a 13-mask process, and the process sequence includes:

[0259] Choose between rigid or flexible substrates;

[0260] A buffer layer is formed on the substrate using materials such as SiOx and SiNx;

[0261] Through 1mask process, Mo metal material is used to form the light shielding layer LS;

[0262] Through the 2mask process, P-Si material is used to form a poly active layer;

[0263] A first gate insulating layer GI1 is formed by using SiO x material;

[0264] Through the 3-mask process, Mo metal material is used to form the first gate metal layer Gate1.

[0265] A second gate insulating layer GI2 is formed by using materials such as SiOx and SiNx;

[0266] Through a 4-mask process, a second gate metal layer Gate2 is formed using a Mo metal material;

[0267] Through the 5-mask process, an interlayer insulating layer ILD is formed using materials such as SiOx and SiNx;

[0268] Through the 6-mask process, a via hole is formed between the first source-drain metal layer SD1 and the light shielding layer LS;

[0269] Through the 7-mask process, a first source-drain metal layer SD1 of a Ti-Al-Ti stacked structure is formed;

[0270] Through the 8mask process, SiOx or SiNx is used to form the passivation layer PVX;

[0271] A first planar layer PLN1 is formed by using an organic material through a 9-mask process;

[0272] Through a 10-mask process, a second source-drain metal layer SD2 of a Ti-Al-Ti stacked structure is formed;

[0273] A second planar layer PLN2 is formed by using an organic material through an 11mask process;

[0274] The anode layer 50 is formed by using indium tin oxide through a 12-mask process;

[0275] Through the 13-mask process, a pixel definition layer PDL and a spacer layer PS are formed using organic materials.

[0276] like Figure 39 to Figure 53 As shown, in some embodiments, the conductive connection pattern 74 includes a main body portion 741 and a second extension portion 743 extending from the main body portion 741, the main body portion 741 includes at least a portion extending along the second direction, and the second extension portion 743 includes at least a portion extending along the first direction, and the first direction intersects with the second direction;

[0277] The display substrate also includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a fifth transistor T5, wherein a first electrode of the fifth transistor T5 is coupled to the corresponding second extension portion 743, and a second electrode of the fifth transistor T5 is coupled to a first electrode of the driving transistor.

[0278] Exemplarily, the main body portion 741 and the second extension portion 743 are formed as an integral structure.

[0279] Exemplarily, the second extending portion 743 includes a strip structure extending along the first direction.

[0280] Exemplarily, the display substrate further includes a plurality of light emitting control lines E1, and the light emitting control lines E1 include at least a portion extending along the second direction.

[0281] Exemplarily, the plurality of sub-pixel driving circuits in the display substrate are divided into a plurality of rows of sub-pixel driving circuits, and the plurality of rows of sub-pixel driving circuits correspond one-to-one to the plurality of light emitting control lines E1.

[0282] Exemplarily, the gates of the fifth transistors T5 included in each row of the sub-pixel driving circuit are respectively coupled to the corresponding light emitting control line E1. The first electrode of the fifth transistor T5 is coupled to the corresponding second extension portion 743, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the driving transistor.

[0283] The coupling of the first electrode of the fifth transistor T5 with the corresponding second extension portion 743 can reduce the difficulty of display substrate layout while achieving connection of the first electrode of the fifth transistor T5 to the power signal.

[0284] like Figure 39 to Figure 53As shown, in some embodiments, the multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged along the second direction; the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits are divided into multiple sub-pixel driving circuit groups, and each sub-pixel driving circuit group includes two adjacent sub-pixel driving circuits;

[0285] The first electrodes of the two fifth transistors T5 included in the sub-pixel driving circuit group are coupled to the corresponding second extending portion 743 of the same conductive connection pattern 74 .

[0286] Exemplarily, the multiple conductive connection patterns 74 included in the display substrate are divided into multiple rows of conductive connection patterns 74, each row of conductive connection patterns 74 includes multiple conductive connection patterns 74 arranged along the second direction, and the multiple rows of conductive connection patterns 74 correspond one-to-one to the multiple rows of sub-pixel driving circuits.

[0287] Exemplarily, the multiple conductive connection patterns 74 included in the display substrate are divided into multiple columns of conductive connection patterns 74, each column of conductive connection patterns 74 includes multiple conductive connection patterns 74 arranged along the first direction, and the conductive connection patterns 74 are arranged alternately with the third conductive patterns 72.

[0288] Exemplarily, the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits are divided into multiple sub-pixel driving circuit groups, each sub-pixel driving circuit group includes two adjacent sub-pixel driving circuits, and each sub-pixel driving circuit belongs to only one sub-pixel driving circuit group.

[0289] Exemplarily, the plurality of sub-pixel driving circuit groups in the display substrate correspond one-to-one to the plurality of conductive connection patterns 74 .

[0290] The above arrangement that the first electrodes of the two fifth transistors T5 included in the sub-pixel driving circuit group are coupled to the corresponding second extension portion 743 of the same conductive connection pattern 74 effectively reduces the layout difficulty of the display substrate.

[0291] like Figure 39 to Figure 53 As shown, in some embodiments, the sub-pixel driving circuit also includes a first transistor T1 and a second transistor T2; the second electrode of the first transistor T1 and the second electrode of the second transistor T2 are respectively coupled to the gate of the driving transistor (i.e., the gate T3-g of the third transistor T3) through the first conductive portion 81; the main body 741 is located between the two first conductive portions 81 included in the corresponding sub-pixel driving circuit group.

[0292] Exemplarily, the display substrate further includes a plurality of second scan lines S2 and a plurality of reset lines R1 , and at least a portion of the second scan lines S2 and at least a portion of the reset lines R1 extend along the second direction.

[0293] Exemplarily, the multiple rows of sub-pixel driving circuits in the display substrate correspond one-to-one to the multiple second scan lines S2. The multiple rows of sub-pixel driving circuits in the display substrate correspond one-to-one to the multiple reset lines R1.

[0294] Exemplarily, the gates of the first transistors T1 included in each row of sub-pixel driving circuits are respectively coupled to the corresponding second scan lines S2 , and the gates of the second transistors T2 included in each row of sub-pixel driving circuits are respectively coupled to the corresponding reset lines R1 .

[0295] Exemplarily, each sub-pixel driving circuit includes a first conductive portion 81 .

[0296] The main body 741 is arranged between the two first conductive parts 81 included in the corresponding sub-pixel driving circuit group, which can not only reduce the layout difficulty of the display substrate, but also facilitate the working stability of the sub-pixel driving circuit.

[0297] like Figure 39 to Figure 53 As shown, in some embodiments, the main body 741 is configured to include a symmetrical figure, the symmetry axis of the symmetrical figure extends along the first direction, and the symmetry axis is located between two sub-pixel driving circuits included in the sub-pixel driving circuit group corresponding to the main body 741.

[0298] Exemplarily, the second extension portion 743 is also symmetrical about the symmetry axis.

[0299] The above configuration not only reduces the layout difficulty of the display substrate, but also helps to improve the working stability of the sub-pixel driving circuit.

[0300] like Figure 39 to Figure 53 As shown, in some embodiments, adjacent third conductive patterns 72 are coupled via at least one conductive connection pattern 74 .

[0301] In some embodiments, at least a portion of the conductive connection pattern 74 is coupled to the fourth portions 723 of two adjacent third conductive patterns 72 .

[0302] Exemplarily, adjacent third conductive patterns 72 are coupled via a plurality of conductive connection patterns 74 .

[0303] The above arrangement reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0304] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a plurality of reset lines R1, a plurality of first scan lines S1 and a plurality of second scan lines S2, and at least a portion of the reset lines R1, at least a portion of the first scan lines S1 and at least a portion of the second scan lines S2 extend along the second direction;

[0305] The orthographic projection of the third portion 722 on the substrate 60 is set to overlap with the orthographic projection portion of the corresponding reset line R1 on the substrate 60, overlap with the orthographic projection portion of the corresponding first scanning line S1 on the substrate 60, and overlap with the orthographic projection portion of the corresponding second scanning line S2 on the substrate 60.

[0306] Exemplarily, the multiple rows of sub-pixel driving circuits in the display substrate correspond one-to-one to the multiple first scan lines S1.

[0307] Exemplarily, all the third portions 722 included in the display substrate are divided into a plurality of rows of third portions 722 , and each row of third portions 722 includes a plurality of third portions 722 arranged along the second direction.

[0308] Exemplarily, the multiple rows of third portions 722 correspond one-to-one to the multiple reset lines R1; the multiple rows of third portions 722 correspond one-to-one to the multiple first scan lines S1; and the multiple rows of third portions 722 correspond one-to-one to the multiple second scan lines S2.

[0309] The above arrangement reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0310] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a plurality of light emitting control lines E1, a plurality of third scanning lines S3, a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2 and a third initialization signal transmission layer Vinit3;

[0311] The orthographic projection of the fourth portion 723 on the substrate 60 overlaps with the orthographic projection portion of the corresponding light-emitting control line E1 on the substrate 60, overlaps with the orthographic projection portion of the corresponding third scanning line S3 on the substrate 60, overlaps with the orthographic projection portion of the first initialization signal transmission layer Vinit1 on the substrate 60, overlaps with the orthographic projection portion of the second initialization signal transmission layer Vinit2 on the substrate 60, and overlaps with the orthographic projection portion of the third initialization signal transmission layer Vinit3 on the substrate 60.

[0312] Exemplarily, the multiple rows of sub-pixel driving circuits in the display substrate correspond one-to-one to the multiple third scan lines S3.

[0313] Exemplarily, the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3 all include a first transmission portion, and the first transmission portion includes at least a portion extending along the second direction.

[0314] Exemplarily, all the fourth parts 723 included in the display substrate are divided into multiple rows of fourth parts 723, each row of fourth parts 723 includes multiple fourth parts 723 arranged along the second direction. Multiple rows of fourth parts 723 correspond one-to-one to multiple rows of sub-pixel driving circuits in the display substrate.

[0315] Exemplarily, the plurality of rows of fourth portions 723 correspond one-to-one to the plurality of third scan lines S3. The plurality of rows of fourth portions 723 correspond one-to-one to the plurality of first transmission portions included in the first initialization signal transmission layer Vinit1. The plurality of rows of fourth portions 723 correspond one-to-one to the plurality of first transmission portions included in the second initialization signal transmission layer Vinit2. The plurality of rows of fourth portions 723 correspond one-to-one to the plurality of first transmission portions included in the third initialization signal transmission layer Vinit3.

[0316] The above arrangement reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0317] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a plurality of data lines D1, and the data lines D1 include at least a portion extending along the first direction;

[0318] The display substrate further includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor, a fourth transistor T4 and a fifth transistor T5, wherein the fourth transistor T4 is respectively coupled to a first electrode of the first transistor T1 and a corresponding data line D1, and the fifth transistor T5 is respectively coupled to a first electrode of the driving transistor and a corresponding conductive connection pattern 74;

[0319] The fourth transistor T4 includes a fourth active layer 34 , the fifth transistor T5 includes a fifth active layer 35 , and the orthographic projection of the fourth portion 723 on the substrate 60 does not overlap with the orthographic projection of the fourth active layer 34 on the substrate 60 , and does not overlap with the orthographic projection of the fifth active layer 35 on the substrate 60 .

[0320] Exemplarily, the multiple sub-pixel driving circuits included in the display substrate are divided into multiple columns of sub-pixel driving circuits, which correspond one-to-one to the multiple data lines D1, and the first electrode of each fourth transistor T4 in each column of the sub-pixel driving circuit is respectively coupled to the corresponding data line D1.

[0321] Exemplarily, the display substrate includes a plurality of first scan lines S1 , and the gates of the fourth transistors T4 in each row of the sub-pixel driving circuit are respectively coupled to the corresponding first scan lines S1 .

[0322] Exemplarily, the fourth transistor T4 includes a fourth active layer 34 , and the fourth active layer 34 can form a channel region of the fourth transistor T4 .

[0323] Exemplarily, the fifth transistor T5 includes a fifth active layer 35 , and the fifth active layer 35 can form a channel region of the fifth transistor T5 .

[0324] The above-mentioned setting of the orthographic projection of the fourth part 723 on the substrate 60 does not overlap with the orthographic projection of the fourth active layer 34 on the substrate 60, and does not overlap with the orthographic projection of the fifth active layer 35 on the substrate 60; the layout difficulty of the display substrate is reduced, the grid structure of the signal line film layer is optimized, which is beneficial to reducing the voltage drop of the signal line film layer and improving the heat dissipation performance of the signal line film layer.

[0325] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a second initialization signal transmission layer Vinit2;

[0326] The display substrate further includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor, a sixth transistor T6, a seventh transistor T7 and a light-emitting element O1, wherein the sixth transistor T6 is respectively coupled to the second electrode of the driving transistor and the light-emitting element O1, and the seventh transistor T7 is respectively coupled to the light-emitting element O1 and the second initialization signal transmission layer Vinit2;

[0327] The sixth transistor T6 includes a sixth active layer 36 , the seventh transistor T7 includes a seventh active layer 37 , and the orthographic projection of the fourth portion 723 on the substrate 60 surrounds at least part of the orthographic projection of the seventh active layer 37 on the substrate 60 , and also surrounds the orthographic projection of the sixth active layer 36 on the substrate 60 .

[0328] Exemplarily, the gates of the sixth transistors T6 in each row of the sub-pixel driving circuit are respectively coupled to the corresponding light emitting control line E1 .

[0329] Exemplarily, the gates of the seventh transistors T7 in each row of the sub-pixel driving circuit are respectively coupled to the corresponding third scan lines S3 .

[0330] The above-mentioned setting of the orthographic projection of the fourth part 723 on the substrate 60 surrounds at least part of the orthographic projection of the seventh active layer 37 on the substrate 60, and also surrounds the orthographic projection of the sixth active layer 36 on the substrate 60; this reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improving the heat dissipation performance of the signal line film layer.

[0331] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate is further provided with a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor, and the gate of the driving transistor has an orthographic projection on the substrate 60 that partially overlaps with the orthographic projection of the fourth portion 723 on the substrate 60.

[0332] The above arrangement reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0333] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a third initialization signal transmission layer Vinit3;

[0334] The display substrate also includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and an eighth transistor T8, wherein a first electrode of the eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3, and a second electrode of the eighth transistor T8 is coupled to a first electrode or a second electrode of the driving transistor; the eighth transistor T8 includes an eighth active layer 38, and an orthographic projection of the eighth active layer 38 on the substrate 60 at least partially overlaps with an orthographic projection of the fourth portion 723 on the substrate 60.

[0335] Exemplarily, the third initialization signal transmitted by the third initialization signal transmission layer Vinit3 may be a high level signal, for example, a positive power signal, or 0.5 to 1.5 times the voltage value of the positive power signal.

[0336] Exemplarily, when the third initialization signal is a positive power signal, the third initialization signal transmission layer Vinit3 can be coupled to the signal line film layer in the peripheral area of ​​the display substrate; or, in the display area, in the area where the third initialization signal transmission layer Vinit3 overlaps with the second conductive layer, the third initialization signal transmission layer Vinit3 can be coupled to the second conductive layer through a via.

[0337] like Fig.53 As shown, in the display area, in the area where the third initialization signal transmission layer Vinit3 overlaps with the second conductive layer, the third initialization signal transmission layer Vinit3 is coupled to the second conductive layer through a via 90, but is not limited thereto.

[0338] Exemplarily, the gates of the eighth transistors T8 in each row of sub-pixel driving circuits are respectively coupled to the corresponding third scan lines S3 .

[0339] Exemplarily, the first electrodes of the eighth transistors T8 in each row of the sub-pixel driving circuit are respectively coupled to the corresponding first transmission parts in the third initialization signal transmission layer Vinit3.

[0340] The above-mentioned setting makes the orthographic projection of the eighth active layer 38 on the substrate 60 at least partially overlap with the orthographic projection of the fourth part 723 on the substrate 60, which reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0341] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate further includes a plurality of data lines D1 , and the data lines D1 include at least a portion extending along the first direction; there are two data lines D1 between adjacent third conductive patterns 72 .

[0342] Exemplarily, the two data lines D1 between the adjacent third conductive patterns 72 are symmetrically arranged about the symmetry axis.

[0343] like Figure 39 to Figure 53 As shown, in some embodiments, the display substrate is provided to further include a plurality of sub-pixels, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and a storage capacitor, the gate of the driving transistor is reused as the first substrate of the storage capacitor, and the second portion 702 is reused as the second plate of the storage capacitor.

[0344] The above arrangement reduces the layout difficulty of the display substrate, optimizes the grid structure of the signal line film layer, is beneficial to reducing the voltage drop of the signal line film layer, and improves the heat dissipation performance of the signal line film layer.

[0345] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0346] In the display substrate provided in the above embodiment, the signal line film layer includes a first conductive layer, a conductive connection layer, and a second conductive layer that are stacked. This arrangement enables the signal line film layer to be formed into a multi-layer network stacking structure, effectively reducing the voltage drop generated when the signal line film layer transmits a signal. When the display substrate is applied to a display product, the uniformity of the display product in a high-brightness display mode is ensured. Moreover, forming the signal line film layer into a multi-layer network stacking structure helps to dissipate heat in the display product in a high-brightness display mode.

[0347] The display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, and also has the above-mentioned beneficial effects, which will not be described in detail here.

[0348] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0349] As screen sizes get bigger and refresh rates get higher, the loading (load) faced by the panel is getting bigger and bigger, and the problem of insufficient charging time is becoming more and more serious. Therefore, reducing loading and reducing charging time are issues that need to be solved urgently.

[0350] See also Figure 2 , Figure 3 , Figure 5 , Figure 6 and Figure 8 The embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate, the sub-pixels comprising a sub-pixel driving circuit, the orthographic projection of the sub-pixel driving circuit on the substrate having a maximum first width along a second direction; the display substrate further comprises: an initialization signal transmission layer (such as: a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2 and a third initialization signal transmission layer Vinit3) arranged on the substrate; the initialization signal transmission layer comprises a plurality of first transmission parts 20 and a plurality of second transmission parts 21; the plurality of first transmission parts 20 are arranged along a first direction, the first transmission part 20 comprises at least a portion extending along a second direction, the second direction intersecting with the first direction; the second transmission part 21 comprises at least a portion extending along the first direction, and adjacent first transmission parts 20 are coupled via at least one second transmission part 21;

[0351] The multiple first transmission parts 20 include a target transmission part 201, and the target transmission part 201 includes at least a portion extending along the second direction. The second transmission part 21 located between the target transmission part 201 and the previous adjacent first transmission part 20 is staggered by a first distance in the second direction from the second transmission part 21 located between the target transmission part 201 and the next adjacent first transmission part 20, and the first distance is greater than or equal to the first width.

[0352] Exemplarily, the first distance is equal to the first width; or the first distance is an integer multiple of the first width.

[0353] Exemplarily, the second transmission parts 21 staggered along the second direction are connected to sub-pixel driving circuits of different columns.

[0354] Need to explain, Figure 3 The thicker lines are target transmission parts 201 , and the thinner lines are non-target transmission parts 202 . Figure 2 , Figure 5 , Figure 6 and Figure 8 The fan-out region FO, the gate drive circuit GOA, and the negative power line VSS are also illustrated.

[0355] It is worth noting that Figure 1 , Figure 4 and Figure 7 In the embodiment, the timing of the signals transmitted by the reset line R1, the first scan line S1, the second scan line S2, the third scan line S3 and the light emitting control line E1 can be set according to actual needs. For example, when the eighth transistor T8 is not included, the timing of the signals transmitted by the first scan line S1, the second scan line S2 and the third scan line S3 can be set to be the same, but it is not limited thereto.

[0356] It is worth noting that the target transmission unit 201 and the non-target transmission unit 202 in the present disclosure are both used to transmit initialization signals, and are not related to being or not being a transmission target. They are just different names defined according to the different layout methods of the second transmission unit 21 to which they are coupled.

[0357] Exemplarily, the initialization signal transmission layer is used to transmit an initialization signal.

[0358] Exemplarily, the display substrate includes a display area AA and a peripheral area 40 surrounding the display area AA, and the first transmission portion 20 can extend from the display area AA to the peripheral area 40 and can be coupled to a corresponding signal line of the peripheral area 40 to receive a corresponding initialization signal.

[0359] Exemplarily, the display substrate includes a plurality of sub-pixels, the plurality of sub-pixels include a plurality of sub-pixel driving circuits, the plurality of sub-pixel driving circuits are distributed in an array and can be divided into a plurality of rows of sub-pixel driving circuits arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the second direction.

[0360] Exemplarily, the arrangement of the plurality of sub-pixels includes: RGBG, GGRB, etc.

[0361] Fig.29a FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an embodiment of the present disclosure. Fig.29a As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one pixel unit P may include a first color sub-pixel P1 emitting a first color light, a second color sub-pixel P2 emitting a second color light, and two third color sub-pixels P3 emitting a third color light, and the four sub-pixels may each include a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit in each sub-pixel is respectively connected to a scan line, a data line, and a light-emitting control line, and the sub-pixel driving circuit is configured to receive a data voltage transmitted by the data line under the control of the scan line and the light-emitting control line, and output a corresponding current to the light-emitting element. The light-emitting element in each sub-pixel is respectively connected to the sub-pixel driving circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the sub-pixel driving circuit of the sub-pixel.

[0362] In an exemplary embodiment, the first color sub-pixel P1 may be a red sub-pixel (R) emitting red light, and the sub-pixel driving circuit of the sub-pixel P1 is electrically connected to the first electrode (i.e., anode) of the light-emitting element emitting red light, the second color sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the sub-pixel driving circuit of the sub-pixel P2 is electrically connected to the first electrode of the light-emitting element emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light, and the sub-pixel driving circuit of the sub-pixel P3 is electrically connected to the first electrode of the light-emitting element emitting green light. In an exemplary embodiment, the main shape of the first electrode of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. The first electrodes of the four sub-pixels may be arranged in a square manner to form a GGRB pixel arrangement, such as Fig.29a As shown; it can also be arranged in a diamond manner to form an RGBG pixel arrangement, such as Fig.29b In an exemplary embodiment, the four sub-pixels may be arranged in parallel horizontally or vertically, and in an exemplary embodiment, the pixel unit may include three sub-pixels, and the first electrodes of the three sub-pixels may be arranged in parallel horizontally, vertically or in a triangle, which is not limited in the present disclosure.

[0363] Exemplarily, the multiple rows of sub-pixel driving circuits correspond one-to-one to the multiple first transmission parts 20 , and each sub-pixel driving circuit in each row of sub-pixel driving circuits is respectively coupled to the corresponding first transmission part 20 .

[0364] Exemplarily, the first transmission portion 20 includes a portion extending along the second direction and a portion extending along the first direction.

[0365] Exemplarily, the first transmission portion 20 includes a portion extending along the second direction, a portion extending along the first direction, and a portion extending along a third direction, wherein the third direction intersects both the first direction and the second direction.

[0366] Exemplarily, adjacent first transmission parts 20 are coupled via a plurality of second transmission parts 21. The number of the plurality of second transmission parts 21 is less than or equal to the number of sub-pixel driving circuits included in a row of sub-pixel driving circuits.

[0367] Exemplarily, part of the second transmission portion 21 can extend from the display area AA to the peripheral area 40. Exemplarily, the part of the second transmission portion 21 can also be coupled to a corresponding signal line of the peripheral area 40 to receive a corresponding initialization signal.

[0368] Exemplarily, the first transmission unit 20 and the second transmission unit 21 are arranged at the same layer or at different layers.

[0369] Exemplarily, the multiple first transmission parts 20 include at least one target transmission part 201, and the second transmission part 21 located between the target transmission part 201 and the adjacent previous first transmission part 20 is staggered in the second direction with the second transmission part 21 located between the target transmission part 201 and the adjacent next first transmission part 20.

[0370] Exemplarily, the staggered distance is greater than or equal to the maximum width of an orthographic projection of a sub-pixel driving circuit on the substrate in the second direction.

[0371] Exemplarily, the first direction includes a longitudinal direction, and the second direction includes a transverse direction.

[0372] Exemplarily, the display substrate includes a plurality of gate lines and a plurality of data lines, the gate lines include at least a portion extending along the second direction, and the data lines include at least a portion extending along the first direction.

[0373] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, the initialization signal transmission layer is provided to include a plurality of first transmission parts 20 and a plurality of second transmission parts 21; the first transmission part 20 includes at least a portion extending along the second direction, the second transmission part 21 includes at least a portion extending along the first direction, and adjacent first transmission parts 20 are coupled by at least one second transmission part 21. The above-mentioned setting method enables the initialization signal transmission layer to be formed into a grid shape. Compared with the conventional initialization signal transmission layer including only the lateral part, this grid-shaped initialization signal transmission layer can reduce the initialization signal loading by about 20%, so that the initialization signal is charged faster, and the reset effect of the corresponding node is better. This beneficial effect is more significant for large-screen high-frequency panels.

[0374] In more detail, Fig. 9 As shown, it is a simulation of the initialization signal transmission layer using a mesh design. During the period when the reset signal inputted at the reset end is at an effective low level, the initialization signal transmitted by the initialization signal transmission layer can fully complete the writing and realize the reset of the N1 node.

[0375] like Fig.10 As shown, the reset speed when the grid-shaped initialization signal transmission layer is used is faster than the reset speed when the initialization signal transmission layer only includes the transverse part. When the initialization signal transmission layer only includes the transverse part is used, the reset speed that can be achieved at the edge of the transverse part is faster than the reset speed that can be achieved in the middle of the transverse part.

[0376] In the display substrate provided by the embodiment of the present disclosure, the plurality of first transmission parts 20 are provided including a target transmission part 201, and the second transmission part 21 located between the target transmission part 201 and the previous adjacent first transmission part 20 thereof is staggered in the second direction from the second transmission part 21 located between the target transmission part 201 and the next adjacent first transmission part 20 thereof. This arrangement is conducive to increasing the spacing between the second transmission parts 21 adjacent to each other along the first direction, reducing the layout density of the second transmission parts 21, and overcoming the problem of insufficient layout space.

[0377] like Figure 5 and Figure 6 As shown, in some embodiments, the display substrate is provided to include a first initialization signal transmission layer Vinit1 and a second initialization signal transmission layer Vinit2;

[0378] The initialization signal transmission layer is the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2; or,

[0379] The display substrate includes at least two initialization signal transmission layers, a first one of the at least two initialization signal transmission layers is the first initialization signal transmission layer Vinit1, and a second one of the at least two initialization signal transmission layers is the second initialization signal transmission layer Vinit2.

[0380] Exemplarily, the first initialization signal transmission layer Vinit1 is used to transmit a first initialization signal, and the second initialization signal transmission layer Vinit2 is used to transmit a second initialization signal.

[0381] Exemplarily, the initialization signal transmission layer is the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2, so that the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2 includes the first transmission part 20 and the second transmission part 21, so that the first initialization signal transmission layer Vinit1 or the second initialization signal transmission layer Vinit2 is formed into a grid shape.

[0382] Exemplarily, the display substrate includes at least two initialization signal transmission layers, the first of the at least two initialization signal transmission layers is the first initialization signal transmission layer Vinit1, and the second of the at least two initialization signal transmission layers is the second initialization signal transmission layer Vinit2, so that the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 both include the first transmission part 20 and the second transmission part 21, so that the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 are both formed into a grid shape.

[0383] Exemplarily, the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 are insulated from each other.

[0384] The above configuration enables at least one of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 to form a grid structure, which is beneficial to reducing the loading of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2.

[0385] like Figure 8 As shown, in some embodiments, the display substrate is further provided with a third initialization signal transmission layer Vinit3.

[0386] Exemplarily, the third initialization signal transmission layer Vinit3 is used to transmit a third initialization signal.

[0387] Exemplarily, the first initialization signal, the second initialization signal and the third initialization signal are different.

[0388] Exemplarily, at least two of the first initialization signal, the second initialization signal, and the third initialization signal are different.

[0389] Exemplarily, the third initialization signal may be a high level signal.

[0390] Exemplarily, the third initialization signal transmission layer Vinit3 only includes a plurality of the first transmission parts 20. This arrangement enables the layout space occupied by the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3 to be reduced when the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3 are laid out, thereby reducing the layout difficulty of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3.

[0391] In some embodiments, the third of the at least two initialization signal transmission layers is the third initialization signal transmission layer Vinit3.

[0392] Exemplarily, the display substrate includes two initialization signal transmission layers, one of the two initialization signal transmission layers is the first initialization signal transmission layer Vinit1, the other of the two initialization signal transmission layers is the third initialization signal transmission layer Vinit3, and the second initialization signal transmission layer Vinit2 only includes multiple first transmission parts 20.

[0393] Exemplarily, the display substrate includes two initialization signal transmission layers, one of the two initialization signal transmission layers is the second initialization signal transmission layer Vinit2, the other of the two initialization signal transmission layers is the third initialization signal transmission layer Vinit3, and the first initialization signal transmission layer Vinit1 only includes multiple first transmission parts 20.

[0394] Exemplarily, the display substrate includes three initialization signal transmission layers, the first of the three initialization signal transmission layers is the first initialization signal transmission layer Vinit1, the second of the three initialization signal transmission layers is the second initialization signal transmission layer Vinit2, and the third of the three initialization signal transmission layers is the third initialization signal transmission layer Vinit3.

[0395] In the display substrate provided in the above embodiment, among the first initialization signal transmission line, the second initialization signal transmission line and the third initialization signal transmission line, at least two initialization signal transmission lines adopt a grid structure, which is beneficial to reducing the loading of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and / or the third initialization signal transmission layer Vinit3.

[0396] like Figure 8 As shown, in some embodiments, the display substrate is provided to include a first initialization signal transmission layer Vinit1, a second initialization signal transmission layer Vinit2 and a third initialization signal transmission layer Vinit3; the initialization signal transmission layer is one of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3.

[0397] Exemplarily, the initialization signal transmission layer is one of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3, and the remaining two of the first initialization signal transmission layer Vinit1, the second initialization signal transmission layer Vinit2 and the third initialization signal transmission layer Vinit3 only include multiple first transmission parts 20.

[0398] The above configuration is not only conducive to reducing the loading of the initialization signal transmission line, but also can overcome the problem of insufficient layout space and reduce the difficulty of layout.

[0399] like Figure 2 and Figure 3 As shown, in some embodiments, the multiple first transmission parts 20 are provided to include a non-target transmission part 202, and the second transmission part 21 located between the non-target transmission part 202 and the adjacent previous first transmission part 20 is located in the same column along the first direction as the second transmission part 21 located between the non-target transmission part 202 and the adjacent next first transmission part 20.

[0400] Exemplarily, the multiple first transmission parts 20 include multiple non-target transmission parts 202, and the multiple non-target transmission parts 202 include at least two adjacent non-target transmission parts 202, that is, there is no target transmission part 201 between the at least two adjacent non-target transmission parts 202.

[0401] Exemplarily, the second transmission unit 21 that is not misaligned can span 2 to 3 sub-pixel driving circuit layout areas along the first direction, that is, the second transmission unit 21 that is not misaligned can be connected to two sub-pixel driving circuits located in the same column in the first direction, or connected to three sub-pixel driving circuits located in the same column.

[0402] Taking the second initialization signal transmission layer Vint2 including the first transmission part 20 and the second transmission part 21 as an example, the second transmission part 21 can electrically connect two or three sub-pixel driving circuits located in the same column in the first direction at the same time.

[0403] Exemplarily, the second transmission part 21 located between the non-target transmission part 202 and the previous adjacent first transmission part 20 forms an integrated structure with the second transmission part 21 located between the non-target transmission part 202 and the next adjacent first transmission part 20 .

[0404] Exemplarily, the second transmission part 21 located between the non-target transmission part 202 and the adjacent previous first transmission part 20 does not misalign with the second transmission part 21 located between the non-target transmission part 202 and the adjacent next first transmission part 20 in the second direction. The above arrangement can effectively utilize limited layout space, better realize the grid shape of the initialization signal line, and more effectively reduce the loading of the initialization signal line.

[0405] like Figure 6 As shown, in some embodiments, the second transmission portion 21 in the first initialization signal transmission layer Vinit1 and the second transmission portion 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction.

[0406] Exemplarily, a distance between the second transmission portion 21 in the first initialization signal transmission layer Vinit1 and the second transmission portion 21 in the second initialization signal transmission layer Vinit2 in the second direction is greater than or equal to a maximum layout space occupied by a sub-pixel driving circuit in the second direction.

[0407] The above configuration can not only reduce the mutual interference between the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2, but also reduce the layout difficulty of the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2.

[0408] In some embodiments, an orthographic projection of the second transmission portion 21 in the first initialization signal transmission layer Vinit1 on the substrate and an orthographic projection of the second transmission portion 21 in the second initialization signal transmission layer Vinit2 on the substrate are set to at least partially overlap.

[0409] The above configuration can better utilize the effective layout space, so that the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 can better realize a grid layout.

[0410] In some embodiments, the second transmission portion 21 in the first initialization signal transmission layer Vinit1 and the second transmission portion 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; and / or,

[0411] The second transmission portion 21 in the first initialization signal transmission layer Vinit1 and the second transmission portion 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction; and / or,

[0412] The second transmission portion 21 in the second initialization signal transmission layer Vinit2 and the second transmission portion 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction.

[0413] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction.

[0414] Exemplarily, the “staggered” of the two second transmission parts 21 mentioned in the present disclosure means that the sub-pixel driving circuit layout areas where the two second transmission parts 21 are located are not in the same column.

[0415] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; or, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction; or, the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction.

[0416] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not staggered in the second direction.

[0417] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not staggered in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction.

[0418] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are not offset in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are offset in the second direction.

[0419] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are not misaligned in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not misaligned in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are staggered in the second direction.

[0420] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are not misaligned in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not misaligned in the second direction.

[0421] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are staggered in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not staggered in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not staggered in the second direction.

[0422] Exemplarily, the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the second initialization signal transmission layer Vinit2 are not misaligned in the second direction; the second transmission part 21 in the first initialization signal transmission layer Vinit1 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not misaligned in the second direction; the second transmission part 21 in the second initialization signal transmission layer Vinit2 and the second transmission part 21 in the third initialization signal transmission layer Vinit3 are not misaligned in the second direction.

[0423] The above configuration can better utilize the effective layout space, so that the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 can better realize a grid layout.

[0424] In some embodiments, the display substrate further includes a plurality of sub-pixels, and the sub-pixels include sub-pixel driving circuits; the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits, and each sub-pixel driving circuit in each row of sub-pixel driving circuits is respectively coupled to the corresponding first transmission unit 20;

[0425] Adjacent first transmission parts 20 are coupled via a plurality of second transmission parts 21, wherein a distance between adjacent second transmission parts 21 is greater than or equal to a maximum width of a positive projection of a sub-pixel driving circuit on the substrate in the second direction.

[0426] Exemplarily, the sub-pixel driving circuit includes a structure such as 7T1C (ie, 7 transistors and one capacitor) or 8T1C (ie, 8 transistors and one capacitor), but is not limited thereto.

[0427] Exemplarily, adjacent first transmission parts 20 are coupled via a plurality of second transmission parts 21, and a distance between adjacent second transmission parts 21 among the plurality of second transmission parts 21 is equal to a maximum width in the second direction of a positive projection of two sub-pixel driving circuits on the substrate.

[0428] Exemplarily, adjacent first transmission parts 20 are coupled via a plurality of second transmission parts 21, and a distance between adjacent second transmission parts 21 among the plurality of second transmission parts 21 is equal to a maximum width in the second direction of a positive projection of four sub-pixel driving circuits on the substrate.

[0429] The above configuration can better utilize the effective layout space, so that the first initialization signal transmission layer Vinit1 and the second initialization signal transmission layer Vinit2 can better realize a grid layout.

[0430] like Figures 13 to 26 As shown, in some embodiments, in the sub-pixel driving circuits located in the same row, adjacent sub-pixel driving circuits are arranged symmetrically as a whole; the sub-pixels also include multiple data lines and multiple power lines VDD, and the data lines adjacent to each other along the second direction are arranged symmetrically, and the power lines VDD adjacent to each other along the second direction are arranged symmetrically.

[0431] It should be noted that overall symmetrical distribution means that the transistor channels are symmetrically distributed and the sub-pixel driving circuit is generally symmetrical as a whole, but it is not required that each film layer is completely symmetrical. For example, the second conductive portion 82 made of the second source and drain metal layer is asymmetrical.

[0432] Exemplarily, the display substrate further includes: a plurality of first scan lines S1, a plurality of second scan lines S2, a plurality of third scan lines S3, a plurality of reset lines R1 and a plurality of light-emitting control lines E1. The display substrate includes a plurality of drive circuit layout areas, each of which is provided with a corresponding sub-pixel drive circuit. The first scan line S1 is symmetrically located in two adjacent drive circuit layout areas along the second direction, and the axis of symmetry is located at the junction of the two adjacent drive circuit layout areas and extends along the first direction.

[0433] The second scan line S2 is symmetrically located in parts of two adjacent drive circuit layout areas along the second direction, and the symmetry axis is located at the junction of the two adjacent drive circuit layout areas and extends along the first direction.

[0434] The third scan line S3 is symmetrically located in parts of two adjacent drive circuit layout areas along the second direction, and the symmetry axis is located at the junction of the two adjacent drive circuit layout areas and extends along the first direction.

[0435] The reset line R1 is symmetrically located in parts of two adjacent drive circuit layout areas along the second direction, and the symmetry axis is located at the junction of the two adjacent drive circuit layout areas and extends along the first direction.

[0436] The light emitting control line E1 is symmetrically located in parts of two adjacent driving circuit layout areas along the second direction, and the symmetry axis is located at the junction of the two adjacent driving circuit layout areas and extends along the first direction.

[0437] Exemplarily, the sub-pixel further includes a light-emitting element, the light-emitting element includes an anode, and the anode is located on a side of the sub-pixel driving circuit facing away from the substrate.

[0438] The above arrangement makes the structures below the anode (i.e., between the anode and the substrate) (such as the sub-pixel driving circuit, the first scanning line S1, the second scanning line S2, the third scanning line S3, the reset line R1, the light emitting control line E1, the data line and the power line VDD, etc.) arranged symmetrically, which can well improve the flatness of the anode 50. Moreover, the transmittance of the pixel can be improved.

[0439] Need to explain, such as Figure 26 to Figure 28 As shown, the display substrate includes a pixel defining layer, and the pixel defining layer defines a pixel opening 51 .

[0440] In some embodiments, the first transmission part 20 and the second transmission part 21 are arranged to form an integrated structure.

[0441] The above arrangement enables the first transmission part 20 and the second transmission part 21 to be formed simultaneously in the same patterning process and connected, thereby greatly simplifying the manufacturing process of the initialization signal transmission layer and reducing the manufacturing cost.

[0442] In some embodiments, Figure 7 As shown, the sub-pixel driving circuit includes a storage capacitor C, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8.

[0443] The storage capacitor C is coupled to the power line VDD and the gate of the third transistor T3 respectively. Exemplarily, the gate of the third transistor T3 is reused as the first plate of the storage capacitor C, and the second plate C-2 of the storage capacitor C is coupled to the power line VDD.

[0444] The gate of the first transistor T1 is coupled to the second scan line S2, the first electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3, and the second electrode of the first transistor T1 is coupled to the gate of the third transistor T3;

[0445] The gate of the second transistor T2 is coupled to the reset line R1, the first electrode of the second transistor T2 is coupled to the first initialization signal transmission layer Vinit1, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3;

[0446] A gate of the fourth transistor T4 is coupled to the first scan line S1, a first electrode of the fourth transistor T4 is coupled to the light emitting control line E1, and a second electrode of the fourth transistor T4 is coupled to a first electrode of the third transistor T3;

[0447] The gate of the fifth transistor T5 is coupled to the light emitting control line E1, the first electrode of the fifth transistor T5 is coupled to the power line VDD, and the second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3;

[0448] A gate of the sixth transistor T6 is coupled to the light emitting control line E1 , a first electrode of the sixth transistor T6 is coupled to a second electrode of the third transistor T3 , and a second electrode of the sixth transistor T6 is coupled to the light emitting element O1 .

[0449] A gate of the seventh transistor T7 is coupled to the third scan line S3 , a first electrode of the seventh transistor T7 is coupled to the second initialization signal transmission layer Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the light emitting element O1 .

[0450] A gate of the eighth transistor T8 is coupled to the third scan line S3 , a first electrode of the eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3 , and a second electrode of the eighth transistor T8 is coupled to the first electrode or the second electrode of the third transistor T3 .

[0451] Need to explain, Figure 7 The N1 node is also illustrated in the figure. The N1 node is a node to which the gate of the third transistor T3 is connected. The third transistor T3 is a driving transistor.

[0452] In some embodiments, the first transistor T1 and the second transistor T2 are oxide thin film transistors.

[0453] Exemplarily, the first transistor T1 and the second transistor T2 include oxide transistors, that is, the pixel driving circuit may include both low temperature polysilicon transistors (Low Temperature Poly-Silicon, LTPS for short) and oxide transistors (Oxide), that is, LTPO technology is adopted.

[0454] By setting the first transistor T1 and the second transistor T2 as oxide thin film transistors, it is beneficial to reduce the gate leakage of the driving transistor and ensure the stability of the gate potential of the driving transistor.

[0455] like Fig.30 As shown, Figure 7 The timing diagram corresponding to the driving method of the neutron pixel driving circuit, the driving method may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light emitting stage t4.

[0456] In the reset stage t1: the light-emitting control line E1, the reset line R1, and the first scan line S1 output high-level signals, the second scan line S2 and the third scan line S3 output low-level signals, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initialization signal transmission layer Vinit1 inputs the first initialization signal, the power line VDD inputs the power signal, and the second initialization signal transmission layer Vinit2 inputs the second initialization signal. The voltages of the first initialization signal and the second initialization signal may be the same or different.

[0457] In the threshold compensation stage t2: the light-emitting control line E1, the second scan line S2, and the third scan line S3 output high-level signals, the reset line R1 and the first scan line S1 output low-level signals, the first transistor T1 and the fourth transistor T4 are turned on, and the data line D1 writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage value corresponding to the data signal, and Vth is the threshold voltage of the driving transistor.

[0458] In the buffer stage t3: the light emitting control line E1, the third scanning line S3, and the first scanning line S1 output high-level signals, the second scanning line S2 and the reset line R1 output low-level signals, and all transistors are turned off.

[0459] In the light-emitting stage t4: the third scan line S3 and the first scan line S1 output high-level signals, the light-emitting control line E1, the second scan line S2, and the reset line R1 output low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0460] It should be understood that in other exemplary embodiments, the driving method may not include a buffer stage; the second transistor T2 and the seventh transistor T7 may also be turned on at different stages. In the threshold compensation stage t2, the effective level (low level) duration corresponding to the first scan line S1 may be shorter than the effective level (high level) duration corresponding to the second scan line S2. In the threshold compensation stage t2, the first scan line S1 may scan a row of sub-pixel drive circuits, and the second scan line S2 may scan multiple rows of sub-pixel drive circuits, such as two rows of sub-pixel drive circuits, row by row.

[0461] By providing a high potential to the source of the driving transistor through T8, the afterimage problem caused by the different gate-source voltage differences of the driving transistor under different data signals in the sub-pixel driving circuit can be effectively improved.

[0462] Exemplarily, the reset line R1 includes two layers, one of which is made of the second gate metal layer, and the other is made of the third gate metal layer.

[0463] Exemplarily, the second scan line S2 includes two layers, one of which is made of the second gate metal layer, and the other is made of the third gate metal layer.

[0464] like Figures 11 to 25 As shown, in some embodiments, the display substrate further includes a plurality of sub-pixels; the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor (ie, a third transistor T3);

[0465] The orthographic projection of the second transmission portion 21 on the substrate partially overlaps with the orthographic projection of the gate of the corresponding driving transistor (ie, the gate T3 - g of the third transistor T3 ) on the substrate.

[0466] Need to explain, Fig.15 The third active layer 33 and the seventh active layer 37 are illustrated in FIG. Fig.21 The second active layer 32 is illustrated in FIG.

[0467] like Figures 12 to 25 As shown, in some embodiments, the display substrate includes a plurality of data lines D1, and the data lines D1 include at least a portion extending along the first direction;

[0468] The sub-pixel driving circuit further includes: a first transistor T1 and a fourth transistor T4, wherein the first transistor T1 is coupled to the first electrode and the second electrode of the driving transistor respectively, and the fourth transistor T4 is coupled to the first electrode of the driving transistor and the corresponding data line respectively; the first transistor T1 includes a first active layer 31, and the fourth transistor T4 includes a fourth active layer 34;

[0469] At least a portion of the orthographic projection of the second transmission portion 21 on the substrate is located between the orthographic projection of the first active layer 31 on the substrate and the orthographic projection of the fourth active layer 34 on the substrate.

[0470] like Figures 12 to 25 As shown, in some embodiments, the display substrate further includes a power line VDD; the sub-pixel further includes a light-emitting element O1; the sub-pixel driving circuit further includes a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 is respectively coupled to the first electrode of the driving transistor and the corresponding power line VDD, and the sixth transistor T6 is respectively coupled to the second electrode of the driving transistor and the light-emitting element O1; the fifth transistor T5 includes a fifth active layer 35, and the sixth transistor T6 includes a sixth active layer 36;

[0471] At least a portion of the orthographic projection of the second transmission portion 21 on the substrate is located between the orthographic projection of the fifth active layer 35 on the substrate and the orthographic projection of the sixth active layer 36 on the substrate.

[0472] like Figures 12 to 25 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of sub-pixel groups, each sub-pixel group including a first sub-pixel and a second sub-pixel;

[0473] The first sub-pixel and the second sub-pixel both include a second conductive portion 82, and the second conductive portion 82 in the first sub-pixel is coupled to the second conductive portion 82 in the second sub-pixel;

[0474] The fifth transistor T5 in the first sub-pixel is coupled to the second conductive portion 82; the fifth transistor T5 in the second sub-pixel is coupled to the second conductive portion 82, and the second conductive portion 82 in the second sub-pixel is coupled to the corresponding power line VDD;

[0475] At least part of the second transmission portion 21 is located in the sub-pixel driving circuit layout area in the first sub-pixel, and the orthographic projection of the second transmission portion 21 on the substrate does not overlap with the orthographic projection of the second conductive portion 82 in the first sub-pixel on the substrate.

[0476] like Fig.13 , Fig. 22 , Fig.31a and Fig.31bAs shown, the first transistor T1 and the second transistor T2 are coupled to the gate of the third transistor T3 through the first conductive part 81. The fifth transistor T5 is coupled to the power line VDD through the second conductive part 82. The fourth transistor T4 is coupled to the corresponding data line through the third conductive part 83. The second transistor T2 is coupled to the first initialization signal transmission layer Vinit1 through the fourth conductive part 84. The first transistor T1 is coupled to the third transistor T3 through the fifth conductive part 85. The sixth transistor T6 and the seventh transistor T7 are coupled to the anode through the sixth conductive part 86. The eighth transistor T8 is coupled to the third transistor T3 through the seventh conductive part 87. The eighth transistor T8 is coupled to the third initialization signal transmission layer Vinit3 through the eighth conductive part 88.

[0477] Exemplarily, at least a portion of the second transmission portion 21 is located in a sub-pixel driving circuit layout area in the first sub-pixel, and the second transmission portion 21 is not located in a sub-pixel driving circuit layout area in the second sub-pixel.

[0478] Exemplarily, the second conductive portion 82 in the first sub-pixel and the second conductive portion 82 in the second sub-pixel form an integrated structure.

[0479] Exemplarily, the area of ​​the second conductive portion 82 in the first sub-pixel is smaller than the area of ​​the second conductive portion 82 in the second sub-pixel.

[0480] Exemplarily, the orthographic projection of the second transmission portion 21 on the substrate does not overlap with the orthographic projection of the second conductive portion 82 in the first sub-pixel on the substrate. Exemplarily, the orthographic projection of the second transmission portion 21 on the substrate is aligned with the orthographic projection of the second conductive portion 82 in the first sub-pixel on the substrate along the second direction.

[0481] The above configuration is beneficial to compensate for the symmetry of the second conductive portion 82 in the first sub-pixel and the second sub-pixel.

[0482] like Figures 12 to 25 As shown, in some embodiments, the sub-pixel driving circuit further includes an eighth transistor T8, the eighth transistor T8 is coupled to the first electrode or the second electrode of the driving transistor, and the eighth transistor T8 is used to reset the first electrode or the second electrode;

[0483] The eighth transistor T8 includes an eighth active layer 38 , and at least a portion of an orthographic projection of the second transmission portion 21 on the substrate is aligned with an orthographic projection of the eighth active layer 38 on the substrate along the second direction.

[0484] Exemplarily, in the same sub-pixel, the orthographic projection of the second transmission portion 21 on the substrate is located between the orthographic projection of the seventh active layer 37 on the substrate and the orthographic projection of the eighth active layer 38 on the substrate.

[0485] In some embodiments, an orthographic projection of the second transmission portion 21 on the substrate partially overlaps with an orthographic projection of the reset line R1 on the substrate.

[0486] In some embodiments, the orthographic projection of the second transmission portion 21 on the substrate partially overlaps with the orthographic projection of the first scanning line S1 on the substrate.

[0487] In some embodiments, the orthographic projection of the second transmission portion 21 on the substrate partially overlaps with the orthographic projection of the second scanning line S2 on the substrate.

[0488] In some embodiments, the orthographic projection of the second transmission portion 21 on the substrate partially overlaps with the orthographic projection of the third scanning line S3 on the substrate.

[0489] In the display substrate provided by the above embodiment, the second transmission part 21 is arranged at the above position, which is beneficial to reducing the layout difficulty of the second transmission part 21 and is beneficial to the overall working stability of the sub-pixel driving circuit.

[0490] like Figure 1 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor, and further includes:

[0491] a second transistor T2, wherein the second transistor T2 is respectively coupled to the gate of the driving transistor and the initialization signal transmission layer;

[0492] A seventh transistor T7, wherein the seventh transistor T7 is coupled to the light emitting element O1 and the initialization signal transmission layer respectively.

[0493] Exemplarily, the second transistor T2 is coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1 respectively; the seventh transistor T7 is coupled to the light emitting element O1 and the first initialization signal transmission layer Vinit1 respectively.

[0494] like Figure 4 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor, and further includes:

[0495] a second transistor T2, wherein the second transistor T2 is respectively coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1;

[0496] A seventh transistor T7, wherein the seventh transistor T7 is respectively coupled to the light emitting element O1 and the second initialization signal transmission layer Vinit2.

[0497] like Figure 7 As shown, in some embodiments, the display substrate includes a plurality of sub-pixels, and the sub-pixels include a light-emitting element O1 and a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor, and further includes:

[0498] a second transistor T2, wherein the second transistor T2 is respectively coupled to the gate of the driving transistor and the first initialization signal transmission layer Vinit1;

[0499] a seventh transistor T7, wherein the seventh transistor T7 is respectively coupled to the light emitting element O1 and the second initialization signal transmission layer Vinit2;

[0500] An eighth transistor T8, wherein the eighth transistor T8 is respectively coupled to the first electrode of the driving transistor and the third initialization signal transmission layer Vinit3.

[0501] like Figure 2 As shown, in some embodiments, the display substrate further includes a display area AA and a peripheral area 40 surrounding the display area AA, and the display substrate further includes:

[0502] A first signal line 11, the first signal line 11 is located in the peripheral area 40 of the display substrate, the first signal line 11 includes at least a portion extending along the first direction, and the first signal line 11 is coupled to the first initialization signal transmission layer Vinit1;

[0503] The first signal line 11 is made of a second source-drain metal layer, and the first transmission part 20 included in the first initialization signal transmission layer Vinit1 is made of a first gate metal layer.

[0504] Exemplarily, the first signal lines 11 are located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the first signal lines 11 .

[0505] Exemplarily, the first signal line 11 is coupled to the first transmission part 20 of the first initialization signal transmission layer Vinit1.

[0506] Exemplarily, the display substrate includes: a light-shielding layer LS, an isolation layer, a first buffer layer, a poly active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, a second buffer layer, an oxide active layer (such as IGZO), a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a first source-drain metal layer, a passivation layer, a first flat layer, a second source-drain metal layer, a second flat layer, an anode layer, a pixel defining layer, a spacer layer, a light-emitting functional layer, a cathode layer and an encapsulation layer.

[0507] Exemplarily, the orthographic projection of the light shielding layer on the substrate at least partially overlaps with the orthographic projection of the channel portion of the third transistor T3 on the substrate, which can shield the influence of light on the channel portion and shield the influence of nearby charges on the channel portion. Exemplarily, the light shielding layer has a stable potential, such as a power supply potential. Exemplarily, the light shielding layer is formed as a whole layer structure.

[0508] Exemplarily, the first signal line 11 is coupled to the first initialization signal transmission layer Vinit1 through a conductive connection portion, and the conductive connection portion is coupled to the first signal line 11 and the first transmission portion 20 of the first initialization signal transmission layer Vinit1 through vias, respectively. Exemplarily, the conductive connection portion is made of the first source-drain metal layer.

[0509] like Figure 5 and Figure 6 As shown, in some embodiments, the display substrate further includes:

[0510] a second signal line 12, the second signal line 12 is located in the peripheral area 40 of the display substrate, the second signal line 12 includes at least a portion extending along the first direction, the orthographic projection of the first signal line 11 on the substrate is located between the display area AA and the orthographic projection of the second signal line 12 on the substrate, and the second signal line 12 is coupled to the second initialization signal transmission layer Vinit2;

[0511] The second signal line 12 and the first transmission part 20 included in the second initialization signal transmission layer Vinit2 are both made of the first source-drain metal layer.

[0512] Exemplarily, the second signal lines 12 are located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the second signal lines 12 .

[0513] Exemplarily, the second signal line 12 is coupled to the first transmission part 20 of the second initialization signal transmission layer Vinit2.

[0514] Exemplarily, the second signal line 12 and the first transmission part 20 of the second initialization signal transmission layer Vinit2 form an integrated structure.

[0515] like Figure 8 As shown, in some embodiments, the display substrate further includes:

[0516] A third signal line 13, the orthographic projection of the third signal line 13 on the substrate is located between the orthographic projection of the first signal line 11 on the substrate and the orthographic projection of the second signal line 12 on the substrate, and the third signal line 13 is coupled to the third initialization signal transmission layer Vinit3;

[0517] The third signal line 13 is made of a first source-drain metal layer, and the third initialization signal transmission layer Vinit3 is made of a third gate metal layer.

[0518] Exemplarily, the third signal lines 13 are located on the left and right sides of the display area AA, the left and right sides are arranged along the second direction, and the display area AA is located between the third signal lines 13 .

[0519] Exemplarily, the third signal line 13 is coupled to the first transmission part 20 of the third initialization signal transmission layer Vinit3.

[0520] Exemplarily, the third signal line 13 is coupled to the first transmission part 20 of the third initialization signal transmission layer Vinit3 through a via.

[0521] Exemplarily, the first signal line, the second signal line and the third signal line may be arranged only in a frame area on one side of the display substrate, such as: in a left frame, a right frame, an upper frame or a lower frame.

[0522] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0523] Exemplarily, the display device comprises an active matrix organic light emitting diode display device.

[0524] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0525] In the display substrate provided in the above embodiment, the initialization signal transmission layer is provided to include a plurality of first transmission parts 20 and a plurality of second transmission parts 21; the first transmission part 20 includes at least a portion extending along the second direction, the second transmission part 21 includes at least a portion extending along the first direction, and adjacent first transmission parts 20 are coupled by at least one second transmission part 21. The above arrangement enables the initialization signal transmission layer to be formed into a grid shape. Compared with the conventional initialization signal transmission layer including only the lateral part, the grid-shaped initialization signal transmission layer can reduce the initialization signal loading by about 20%, so that the initialization signal is charged faster, and the reset effect of the corresponding node is better. This beneficial effect is more significant for large-screen high-frequency panels.

[0526] In the display substrate provided in the above embodiment, the plurality of first transmission parts 20 include a target transmission part 201, and the second transmission part 21 located between the target transmission part 201 and the previous adjacent first transmission part 20 is staggered in the second direction from the second transmission part 21 located between the target transmission part 201 and the next adjacent first transmission part 20. This arrangement is conducive to increasing the spacing between the second transmission parts 21 adjacent to each other along the first direction, reducing the layout density of the second transmission parts 21, and overcoming the problem of insufficient layout space.

[0527] Therefore, the display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0528] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0529] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying any creative work, changes to the sequence of the steps are also within the protection scope of the present disclosure.

[0530] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0531] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0532] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0533] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0534] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A substrate and a signal line film layer disposed on the substrate; the signal line film layer comprises: a first conductive layer and a second conductive layer arranged in a stacked manner; and a conductive connection layer, wherein the conductive connection layer and the first conductive layer and the second conductive layer are arranged in different layers, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the conductive connection layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate, and the conductive connection layer is coupled to the first conductive layer and the second conductive layer respectively; The conductive connection layer includes a plurality of conductive connection patterns; The first conductive layer includes a plurality of first conductive patterns arranged along a first direction; the first conductive pattern includes at least a portion extending along a second direction, the second direction intersecting the first direction, and the first conductive pattern includes a plurality of first hollow areas; the first conductive pattern is coupled to the corresponding conductive connection pattern; The first conductive pattern includes a plurality of first portions and a plurality of second portions, wherein the first portions and the second portions are alternately arranged along the second direction; The width of the first portion in a direction perpendicular to the second direction is smaller than the distance between two boundaries of the second portion that are farthest apart in a direction perpendicular to the second direction; and the second portion includes the first hollow area.

2. The display substrate according to claim 1, wherein: The plurality of first portions include a plurality of first target portions and a plurality of second target portions, the first target portions and the second target portions are arranged alternately, and a width of the first target portion in a direction perpendicular to the second direction is greater than a width of the second target portion in a direction perpendicular to the second direction; The first target portion is coupled to the corresponding conductive connection pattern.

3. The display substrate according to claim 2, wherein: The first target portion is offset from the second target portion along the first direction.

4. The display substrate according to any one of claims 1 to 3, wherein: The second conductive layer includes a plurality of third conductive patterns arranged along a second direction, the third conductive patterns include at least a portion extending along a first direction, the second direction intersects with the first direction; the third conductive patterns include a plurality of second hollow areas; the third conductive patterns are coupled to the corresponding conductive connection patterns.

5. The display substrate according to claim 4, wherein: The third conductive pattern includes a plurality of third portions and a plurality of fourth portions, and the third portions and the fourth portions are alternately arranged along the first direction; The width of the third portion in a direction perpendicular to the first direction is smaller than the distance between two boundaries of the fourth portion that are farthest apart in a direction perpendicular to the first direction; and the fourth portion includes the second hollow area.

6. The display substrate according to claim 4, wherein: The first hollow area and the second hollow area at least partially overlap.

7. The display substrate according to claim 4, wherein: The second conductive layer further includes a plurality of fourth conductive patterns, and adjacent third conductive patterns are coupled via at least one of the fourth conductive patterns.

8. The display substrate according to claim 4, wherein: The conductive connection pattern includes a main body portion, and the main body portion is coupled to the corresponding first conductive pattern and the third conductive pattern respectively.

9. The display substrate according to claim 8, wherein: The conductive connection pattern further includes at least one first extension portion extending from the main body portion.

10. The display substrate according to claim 9, wherein: An orthographic projection of the first extension portion on the substrate at least partially overlaps with an orthographic projection of the second conductive layer on the substrate.

11. The display substrate according to claim 9, wherein: The first extension portion is coupled to the second conductive layer through a via hole.

12. The display substrate according to claim 1, wherein: The conductive connection pattern includes a main body and a second extension portion extending from the main body, the main body includes at least a portion extending along a second direction, the second extension portion includes at least a portion extending along a first direction, and the first direction intersects with the second direction; The display substrate also includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the corresponding second extension portion, and a second electrode of the fifth transistor is coupled to a first electrode of the driving transistor.

13. The display substrate according to claim 12, wherein: The multiple sub-pixel driving circuits included in the multiple sub-pixels are divided into multiple rows of sub-pixel driving circuits, and each row of sub-pixel driving circuits includes multiple sub-pixel driving circuits arranged along the second direction; the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits are divided into multiple sub-pixel driving circuit groups, and each sub-pixel driving circuit group includes two adjacent sub-pixel driving circuits; The first electrodes of the two fifth transistors included in the sub-pixel driving circuit group are coupled to the corresponding second extension portion of the same conductive connection pattern.

14. The display substrate according to claim 13, wherein: The sub-pixel driving circuit also includes a first transistor and a second transistor; the second electrode of the first transistor and the second electrode of the second transistor are respectively coupled to the gate of the driving transistor through a first conductive portion; the main body is located between the two first conductive portions included in the corresponding sub-pixel driving circuit group.

15. The display substrate according to claim 12, wherein: The main body portion includes a symmetrical figure, a symmetry axis of the symmetrical figure extends along the first direction, and the symmetry axis is located between two sub-pixel driving circuits included in the sub-pixel driving circuit group corresponding to the main body portion.

16. The display substrate according to claim 5, wherein: Adjacent third conductive patterns are coupled via at least one conductive connection pattern.

17. The display substrate according to claim 16, wherein: At least part of the conductive connection pattern is respectively coupled to the fourth portions included in two adjacent third conductive patterns.

18. The display substrate according to claim 5, wherein: The display substrate further comprises a plurality of reset lines, a plurality of first scan lines and a plurality of second scan lines, at least a portion of the reset lines, at least a portion of the first scan lines and at least a portion of the second scan lines all extend along a second direction; The orthographic projection of the third portion on the substrate overlaps with the orthographic projection of the corresponding reset line on the substrate, overlaps with the orthographic projection of the corresponding first scanning line on the substrate, and overlaps with the orthographic projection of the corresponding second scanning line on the substrate.

19. The display substrate according to claim 5, wherein: The display substrate further includes a plurality of light emitting control lines, a plurality of third scanning lines, a first initialization signal transmission layer, a second initialization signal transmission layer and a third initialization signal transmission layer; The orthographic projection of the fourth part on the substrate overlaps with the orthographic projection of the corresponding light-emitting control line on the substrate, overlaps with the orthographic projection of the corresponding third scanning line on the substrate, overlaps with the orthographic projection of the first initialization signal transmission layer on the substrate, overlaps with the orthographic projection of the second initialization signal transmission layer on the substrate, and overlaps with the orthographic projection of the third initialization signal transmission layer on the substrate.

20. The display substrate according to claim 5, wherein: The display substrate further includes a plurality of data lines, the data lines including at least a portion extending along the first direction; The display substrate further comprises a plurality of sub-pixels, wherein the sub-pixels comprise a sub-pixel driving circuit, wherein the sub-pixel driving circuit comprises a driving transistor, a fourth transistor and a fifth transistor, wherein the fourth transistor is respectively coupled to a first electrode of the first transistor and a corresponding data line, and the fifth transistor is respectively coupled to a first electrode of the driving transistor and a corresponding conductive connection pattern; The fourth transistor includes a fourth active layer, the fifth transistor includes a fifth active layer, and an orthographic projection of the fourth portion on the substrate does not overlap with an orthographic projection of the fourth active layer on the substrate, and does not overlap with an orthographic projection of the fifth active layer on the substrate.

21. The display substrate according to claim 5, wherein: The display substrate further includes a second initialization signal transmission layer; The display substrate further includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor, a sixth transistor, a seventh transistor, and a light-emitting element, wherein the sixth transistor is respectively coupled to the second electrode of the driving transistor and the light-emitting element, and the seventh transistor is respectively coupled to the light-emitting element and the second initialization signal transmission layer; The sixth transistor includes a sixth active layer, the seventh transistor includes a seventh active layer, and the orthographic projection of the fourth portion on the substrate surrounds at least a portion of the orthographic projection of the seventh active layer on the substrate and also surrounds the orthographic projection of the sixth active layer on the substrate.

22. The display substrate according to claim 5, wherein: The display substrate further comprises a plurality of sub-pixels, each of which comprises a sub-pixel driving circuit, wherein the sub-pixel driving circuit comprises a driving transistor, and an orthographic projection of a gate of the driving transistor on the substrate partially overlaps with an orthographic projection of the fourth portion on the substrate.

23. The display substrate according to claim 5, wherein: The display substrate further includes a third initialization signal transmission layer; The display substrate further includes a plurality of sub-pixels, each of the sub-pixels includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and an eighth transistor, a first electrode of the eighth transistor is coupled to the third initialization signal transmission layer, and a second electrode of the eighth transistor is coupled to the first electrode or the second electrode of the driving transistor; The eighth transistor includes an eighth active layer, and an orthographic projection of the eighth active layer on the substrate at least partially overlaps with an orthographic projection of the fourth portion on the substrate.

24. The display substrate according to claim 1, wherein: The display substrate also includes a plurality of sub-pixels, each of which includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a driving transistor and a storage capacitor, wherein the gate of the driving transistor is reused as a first substrate of the storage capacitor, and the second portion is reused as a second plate of the storage capacitor.

25. A display device comprising the display substrate according to any one of claims 1 to 24.

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