Alternating current sensor and wireless charging chip

Abstract

The application provides an alternating current sensor and a wireless charging chip. The alternating current sensor comprises an integration circuit, a differential circuit and a calibration circuit. The integration circuit is used for integrating the filtered voltage across the inductor in the TX coil. The differential circuit is used for differentiating the filtered voltage across the capacitor in the TX coil. The calibration circuit is used for sampling and comparing the output signals of the integration circuit and the differential circuit, and adjusting the output results of the integration circuit and the differential circuit until they are the same. At this time, the output result of the differential circuit can be used to calculate the current flowing through the TX coil. The whole device has a current calibration function. The calibration process does not need to use a commercial current sensor to provide a reference current. The time constants of the differential circuit and the integration circuit can be calibrated, so that they are not affected by process changes. After calibration, the current detection precision is not affected by the parameters of on-chip elements, the current measurement precision is high, the structure is compact, and the integration is easy.

Description

Technical Field

[0001] This application relates to the field of wireless power transmission, and in particular to an alternating current sensor and a wireless charging chip. Background Technology

[0002] The charging of smart devices is gradually shifting from wired to wireless charging. Wireless charging works by transmitting power through circuit coupling between a transmitter and a receiver. The transmitter is located within the wireless charging device, and the receiver is located within the smart device. The transmitter contains a transmitting coil (TX coil), and the receiver contains a receiving coil (RX coil). The accuracy of the coupling between the TX coil and the corresponding RX coil determines whether the wireless charging device can accurately charge the smart device. The accuracy of this coupling depends on the transmitter's accurate measurement of the current in the receiver's RX coil. The transmitter can also use current measurement to determine whether the receiver needs charging or has completed charging.

[0003] The transmitter can measure the current in the TX coil by setting an AC current sensor, and then calculate the current in the RX coil. The TX coil typically includes an inductor and a capacitor connected in series. A conventional AC current sensor can use a secondary coil to be placed close to the inductor and measure the current in the secondary coil. Since the current in the secondary coil is proportional to the current in the primary coil, the current in the inductor can be obtained from the current in the secondary coil and the ratio, and the current in the inductor can be used as the measured current in the TX coil.

[0004] However, this type of AC current sensor cannot be integrated because it relies on a secondary coil for measurement, thus occupying a large area and having a relatively large measurement error. Summary of the Invention

[0005] This application provides an AC current sensor and a wireless charging chip, which can be used to solve the technical problems of low accuracy and difficulty in integration of conventional AC current sensors when measuring the current of the TX coil.

[0006] In a first aspect, embodiments of this application provide an alternating current sensor, comprising:

[0007] An integrating circuit is configured to receive a first inductor voltage V through a first input terminal of the integrating circuit. L * and the voltage V of the first inductor L * Integrating, a second inductor voltage V is generated. L ** The first inductor voltage V L * V is the voltage across the inductor in the TX coil. LThe voltage obtained after filtering, the integrating circuit includes a first adjustable resistor;

[0008] A differentiating circuit is configured to receive a first capacitor voltage V through a first input terminal of the differentiating circuit. C * and the voltage V of the first capacitor C * Differentiate to generate the second capacitor voltage V C ** The first capacitor voltage V C * V is the voltage across the capacitor in the TX coil. C The voltage obtained after filtering, the differentiating circuit includes a second adjustable resistor;

[0009] The calibration circuit is configured to be based on the first capacitor voltage V c * A clock signal is generated, and based on the clock signal, the resistance values ​​of the first adjustable resistor and the second adjustable resistor are adjusted simultaneously, while the voltage V of the third inductor is compared in real time. L *** and the voltage V of the third capacitor C *** Until the third inductor voltage V L *** With the third capacitor voltage V C *** Same, calibration complete, the third inductor voltage V L *** The voltage V of the second inductor L ** The third capacitor voltage V obtained after peak sampling C *** The voltage V of the second capacitor C ** Obtained after peak sampling;

[0010] Among them, after calibration, the second capacitor voltage V output by the differentiating circuit C ** It is used to convert the current flowing through the TX coil according to a preset conversion relationship.

[0011] In conjunction with the first aspect, in one possible implementation of the first aspect, the calibration circuit includes:

[0012] The clock circuit is configured to operate based on the voltage V of the first capacitor. c * Generate the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4;

[0013] A logic circuit, the output of which is coupled to the second input of the integrator circuit and the second input of the differentiator circuit respectively, and the logic circuit is used to adjust the resistance values ​​of the first adjustable resistor and the second adjustable resistor simultaneously according to the fourth clock signal CLK4.

[0014] A first sample-and-hold circuit is configured to adjust the second inductor voltage V based on the first clock signal CLK1 and the second clock signal CLK2. The first input terminal of the first sample-and-hold circuit is coupled to the output terminal of the integrator circuit. L ** Peak sampling is performed to obtain the third inductor voltage V. L *** ;

[0015] A second sample-and-hold circuit is provided, wherein its first input is coupled to the output of the differentiating circuit. This second sample-and-hold circuit is used to adjust the voltage V of the second capacitor according to the first clock signal CLK1 and the second clock signal CLK2. C ** Peak sampling is performed to obtain the voltage V of the third capacitor. C *** ;

[0016] The comparator has its first input terminal coupled to the output terminal of the first sample-and-hold circuit, and its second input terminal coupled to the output terminal of the second sample-and-hold circuit. The comparator is used to compare the third inductor voltage V in real time according to the third clock signal CLK3. L *** and the third capacitor voltage V C *** The comparison result is output, and the comparison result is used to indicate the voltage V of the third inductor. L *** and the third capacitor voltage V C *** Are they the same?

[0017] In conjunction with the first aspect, in one possible implementation of the first aspect, the first adjustable resistor and the second adjustable resistor have the same structure, both including:

[0018] A fixed resistor and multiple variable resistors are connected in series, and the resistance value of each variable resistor has a preset proportional relationship with the resistance value of the fixed resistor;

[0019] Multiple adjustable switches are provided, each corresponding to a multiple variable resistor. The adjustable switches are connected in parallel across the corresponding variable resistors. Each adjustable switch includes a control input terminal for receiving a switch control signal, and is used to switch on and off under the control of the switch control signal.

[0020] In conjunction with the first aspect, in one possible implementation of the first aspect, the logic circuit includes: a plurality of flip-flops and a plurality of logic gates connected in sequence, wherein the plurality of flip-flops and the plurality of logic gates correspond one-to-one with a plurality of adjustable switches of the first adjustable resistor or a plurality of adjustable switches of the second adjustable resistor;

[0021] The first input terminal of the logic gate is coupled to the first output terminal of the corresponding flip-flop, and the output terminal of the logic gate is coupled to the second input terminal of the next logic gate and the first input terminal of the flip-flop corresponding to the next logic gate, respectively. The second input terminal of the first logic gate and the first input terminal of the corresponding flip-flop are used to receive the status signal output by the comparator.

[0022] The second input terminal of each of the flip-flops is used to receive the fourth clock signal CLK4, the third input terminal of each of the flip-flops is used to receive the first enable signal, the second output terminal of each of the flip-flops is coupled to the control input terminal of the corresponding adjustable switch, and the second output terminal of each of the flip-flops is used to output the switching control signal of the corresponding adjustable switch.

[0023] In conjunction with the first aspect, in one possible implementation of the first aspect, the first sample-and-hold circuit and the second sample-and-hold circuit have the same structure, both including a first trigger switch, a first operational amplifier, a second trigger switch, and a second operational amplifier;

[0024] The first terminal of the first trigger switch is used to receive the corresponding second inductor voltage V. L ** Or the voltage V of the second capacitor C ** The second terminal of the first trigger switch is coupled to the non-inverting input terminal of the first operational amplifier, and the inverting input terminal of the first operational amplifier is coupled to the output terminal of the first operational amplifier. The output terminal of the first operational amplifier is also coupled to the first terminal of the second trigger switch. The second terminal of the second trigger switch is coupled to the non-inverting input terminal of the second operational amplifier, and the inverting input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier. The output terminal of the second operational amplifier is used to output the corresponding third inductor voltage V. L *** Or the third capacitor voltage V C *** ;

[0025] The second terminal of the first trigger switch is also connected to a first grounding capacitor, and the second terminal of the second trigger switch is also connected to a second grounding capacitor. The third terminal of the first trigger switch is used to receive the first clock signal CLK1, and the third terminal of the second trigger switch is used to receive the second clock signal CLK2.

[0026] In conjunction with the first aspect, in one possible implementation of the first aspect, the integrating circuit further includes: a first capacitor connected in series with the first adjustable resistor;

[0027] The end of the first adjustable resistor furthest from the first capacitor, and the end of the first capacitor furthest from the first adjustable resistor, are both configured as the first input terminal of the integrating circuit. The voltage across the first capacitor is configured as the voltage V of the second inductor. L ** .

[0028] In conjunction with the first aspect, in one possible implementation of the first aspect, the differentiating circuit further includes: a second capacitor connected in series with the second adjustable resistor;

[0029] The end of the second adjustable resistor furthest from the second capacitor, and the end of the second capacitor furthest from the second adjustable resistor, are both configured as the first input terminal of the differentiating circuit. The voltage across the second adjustable resistor is configured as the voltage V of the second capacitor. C ** .

[0030] In conjunction with the first aspect, one possible implementation of the first aspect also includes:

[0031] A first filter circuit is used to filter the voltage V across the inductor in the TX coil. L After attenuation, low-pass filtering, and subtraction, the first inductor voltage V is obtained. L * ;

[0032] The second filter circuit is used to filter the voltage V across the capacitor in the TX coil. C After attenuation, low-pass filtering, and subtraction, the voltage V of the first capacitor is obtained. C * .

[0033] In conjunction with the first aspect, in one possible implementation of the first aspect, the current flowing through the TX coil is determined by the following formula:

[0034]

[0035] Among them, ITX Where β is the current flowing through the TX coil, and C is the attenuation coefficient. TX The capacitance value of the TX coil is related to L. TX Resonance, L TX V is the inductance value of the TX coil. C ** This is the voltage of the second capacitor.

[0036] Secondly, embodiments of this application also provide a wireless charging chip, including an AC current sensor as described in the first aspect and various implementable methods.

[0037] This application provides an AC current sensor and a wireless charging chip. The AC current sensor has a current calibration function. The calibration process does not require the use of a commercial current sensor to provide a reference current. It can calibrate the time constants of the differentiating circuit and the integrating circuit, so that they are not affected by process changes. Therefore, the current detection accuracy after calibration is not affected by the on-chip component parameters, resulting in high current measurement accuracy. Moreover, it has a compact structure and is easy to integrate. Attached Figure Description

[0038] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the circuit structure of a conventional AC current sensor;

[0040] Figure 2 This is a schematic diagram of the overall structure of an AC current sensor provided in an embodiment of this application;

[0041] Figure 3 yes Figure 2 A schematic diagram of the structure of an integrator circuit;

[0042] Figure 4 yes Figure 2 A schematic diagram of the structure of a differential circuit;

[0043] Figure 5 yes Figure 3 The first adjustable resistor and Figure 4 A schematic diagram of the structure of the second adjustable resistor;

[0044] Figure 6 This is a schematic diagram of the clock circuit provided in an embodiment of this application;

[0045] Figure 7 yes Figure 6 The diagram shows an example of the signal timing waveform output by the clock circuit.

[0046] Figure 8 This is a schematic diagram of the logic circuit provided in the embodiments of this application;

[0047] Figure 9 This is a schematic diagram of the structure of the first sample-and-hold circuit and the second sample-and-hold circuit provided in the embodiments of this application;

[0048] Figure 10 This is a schematic diagram of the comparator provided in an embodiment of this application;

[0049] Figure 11 yes Figure 10 A schematic diagram of the output of the comparator shown;

[0050] Figure 12 This is a schematic diagram of the overall timing logic of the calibration circuit provided in the embodiments of this application;

[0051] Figure 13 yes Figure 2 Schematic diagrams of the first and second filter circuits in the circuit;

[0052] Figure 14 This is a schematic diagram of the signal waveform timing of the second inductor voltage and the second capacitor voltage during the calibration process of the AC current sensor provided in this application embodiment;

[0053] Figure 15 This is a schematic diagram of the voltage measurement circuit provided in the embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0055] The following section will first introduce conventional AC current sensors.

[0056] Figure 1 This is a schematic diagram of the circuit structure of a conventional AC current sensor. (Refer to...) Figure 1 As shown, the TX coil in the transmitter typically includes an inductor L connected in series. TX and a capacitor C TX .

[0057] The AC current sensor shown in structure a inserts a known resistor as the sensing resistor R. SEN By measuring the detection resistance R SEN Voltage V across the terminals SEN To calculate the current I in the TX coil. TX However, this method typically introduces a 10% to 15% manufacturing error in the resistance value, which not only affects the accuracy of current measurement but also causes power loss and reduces efficiency.

[0058] The AC current sensor shown in structure b uses a secondary coil to approach the inductor L. TX The current in the secondary coil is measured. Since the current in the secondary coil is proportional to the current in the primary coil, the inductance L can be obtained based on the current in the secondary coil and the ratio. TX The current, and the inductor L TX The current is taken as the measured current I of the TX coil. TX However, this method increases cost and area, cannot be integrated, and has a larger measurement error.

[0059] The AC current sensor shown in structure c is constructed by creating a SensFET device in parallel with a power transistor, detecting the current passing through the SensFET device, and then determining the current passing through the transistor based on the width of the transistor and the SensFET device. However, in this method, transistor size mismatch will reduce the current detection accuracy.

[0060] The AC current sensor shown in structure d is widely used in DC-DC converters (Direct current-Direct current converters). However, when there are multiple TX coils in the transmitter, the coupling between the RX coil and the TX coil will affect the current detection accuracy.

[0061] By examining the implementation structure of conventional AC current sensors, it can be observed that they suffer from low accuracy in measuring the current of the TX coil and are difficult to integrate. To address these issues, this application discloses an AC current sensor through the following embodiments. The AC current sensor provided in this application is applied to a wireless charging device to measure the current flowing through the corresponding TX coil. It should be noted that a wireless charging device can have one or multiple TX coils; this application does not specifically limit this.

[0062] Figure 2 This is a schematic diagram of the overall structure of an AC current sensor provided in an embodiment of this application. (Refer to...) Figure 2 As shown, the AC current sensor provided in this embodiment includes an integrating circuit 100, a differentiating circuit 200, and a calibration circuit 300. The integrating circuit 100 is configured to receive a first inductor voltage V through its first input terminal. L * And the first inductor voltage V L * Integrating, a second inductor voltage V is generated. L ** First inductor voltage VL *The inductance L in the TX coil TX Voltage V across the terminals L The voltage obtained after filtering. The integrating circuit 100 includes a first adjustable resistor. In some embodiments, for the inductor L TX Voltage V across the terminals L Filtering can be achieved through the first filter circuit 400.

[0063] Differentiating circuit 200 is configured to receive first capacitor voltage V through its first input terminal. C * and the voltage V of the first capacitor C * Differentiate to generate the second capacitor voltage V C ** The voltage of the first capacitor V C * The capacitance C in the TX coil TX Voltage V across the terminals C The voltage obtained after filtering. The differentiating circuit 200 includes a second adjustable resistor. In some embodiments, the capacitor C... TX Voltage V across the terminals C Filtering can be achieved through the second filter circuit 500.

[0064] The calibration circuit 300 is configured to be based on the first capacitor voltage V c * A clock signal is generated, and based on the clock signal, the resistance values ​​of the first and second adjustable resistors are adjusted simultaneously, while the voltage V of the third inductor is compared in real time. L *** and the voltage V of the third capacitor C *** Until the third inductor voltage V L *** With the voltage V of the third capacitor C *** Same as above, calibration complete. Among them, the third inductor voltage V... L *** The voltage V of the second inductor L ** The voltage V of the third capacitor obtained after peak sampling C *** The voltage V of the second capacitor C ** The voltage V of the second capacitor is obtained after peak sampling. After calibration, the voltage V output by the differentiating circuit 200 is... C ** Used to convert the current I flowing through the TX coil according to a preset conversion relationship. TX .

[0065] Thus, the AC current sensor provided in this application embodiment has a current calibration function. The calibration process does not require the use of a commercial current sensor to provide a reference current. It can calibrate the time constants of the differentiating circuit and the integrating circuit, making them unaffected by process changes. As a result, the current detection accuracy after calibration is not affected by the on-chip component parameters, resulting in high current measurement accuracy. Moreover, it has a compact structure and is easy to integrate.

[0066] The various circuits of the AC current sensor provided in the embodiments of this application will be described below.

[0067] Figure 3 yes Figure 2 A schematic diagram of an integrator circuit. (Refer to...) Figure 3 As shown, in some embodiments, the integrating circuit 100 may include a first adjustable resistor 110 and a first capacitor 120 connected in series with the first adjustable resistor 110. The end of the first adjustable resistor 110 away from the first capacitor 120 and the end of the first capacitor 120 away from the first adjustable resistor 110 are both configured as the first input terminal of the integrating circuit 100, and the voltage across the first capacitor 120 is configured as the second inductor voltage V. L ** In other embodiments, the integrating circuit 100 may also employ other implementation structures, such as including a first adjustable resistor 110, a first capacitor 120, a parallel resistor, and an operational amplifier. One end of the first adjustable resistor 110 is configured as the first input terminal of the integrating circuit 100, and the other end of the first adjustable resistor 110 is coupled to the inverting input terminal of the operational amplifier. The first capacitor 120 is connected in parallel between the inverting input terminal and the output terminal of the operational amplifier. The first capacitor 120 is also connected in parallel with the parallel resistor. The non-inverting input terminal of the operational amplifier is used to receive the voltage divider signal, and the output terminal of the operational amplifier is used to output the second inductor voltage V. L ** The specific structure of the integrating circuit 100 is not limited in the embodiments of this application.

[0068] Figure 4 yes Figure 2 A schematic diagram of a differential circuit. (Refer to...) Figure 4 As shown, in some embodiments, the differentiating circuit 200 may include a second adjustable resistor 210 and a second capacitor 220 connected in series with the second adjustable resistor 210. The end of the second adjustable resistor 210 away from the second capacitor 220 and the end of the second capacitor 220 away from the second adjustable resistor 210 are both configured as the first input terminal of the differentiating circuit 200, and the voltage across the second adjustable resistor 210 is configured as the voltage V across the second capacitor. C **In other embodiments, the differentiating circuit 200 may also employ other implementation structures, such as including a parasitic resistor, a second capacitor 220, a second adjustable resistor 210, a parallel capacitor, and an operational amplifier. One end of the parasitic resistor is configured as the first input terminal of the differentiating circuit 200, and the other end of the parasitic resistor is connected in series with the second capacitor 220 and coupled to the inverting input terminal of the operational amplifier. The second adjustable resistor 210 is connected in parallel between the inverting input terminal and the output terminal of the operational amplifier. The second adjustable resistor 210 is also connected in parallel with the parallel capacitor. The non-inverting input terminal of the operational amplifier is used to receive the voltage divider signal, and the output terminal of the operational amplifier is used to output the voltage V of the second capacitor. C ** The specific structure of the differentiating circuit 200 is not limited in the embodiments of this application.

[0069] Figure 5 yes Figure 3 The first adjustable resistor and Figure 4 A schematic diagram of the second adjustable resistor. (Refer to...) Figure 5 As shown in the embodiments of this application, the first adjustable resistor 110 and the second adjustable resistor 210 have the same structure, both including a fixed resistor 111, multiple variable resistors 112, and multiple adjustable switches 113 arranged in series. The resistance value of each variable resistor 112 has a preset proportional relationship with the resistance value of the fixed resistor 111. In one example, such as Figure 5 As shown, the number of variable resistors 112 can be 5, with resistance values ​​of R respectively. u R u / 2、R u / 4、R u / 8、R u / 16, where R u The resistance value of the fixed resistor 111 is set. Thus, multiple variable resistors 112 can form various different combinations. Multiple adjustable switches 113 correspond one-to-one with multiple variable resistors 112, and are connected in parallel across the corresponding variable resistor 112. Each adjustable switch 113 includes a control input terminal for receiving switch control signals (e.g., SW4, SW3, SW2, SW1, SW0), and is used to switch on and off under the control of the switch control signals. In some embodiments, the adjustable switch 113 can be a transistor, specifically an N-type MOS transistor (NMOS transistor). In one example, such as... Figure 5 As shown, the total resistance of the first adjustable resistor 110 or the second adjustable resistor 210 is determined by R. u R u / 2、R u / 4、R u / 8、R uThis is achieved through various combinations of / 16. For example: when the switch control signal SW4 of the adjustable switch 113 corresponding to the first variable resistor 112 is low, and the switch control signals SW3, SW2, SW1, and SW0 of the adjustable switches 113 corresponding to the second, third, fourth, and fifth variable resistors 112 are all high, then the adjustable switch 113 corresponding to the first variable resistor 112 is open, and the adjustable switches 113 corresponding to the second, third, fourth, and fifth variable resistors 112 are closed. At this time, the total resistance R of the first adjustable resistor 110 or the second adjustable resistor 210 is R = R U +R U Thus, both the first adjustable resistor 110 and the second adjustable resistor 210 are 5-bit binary weighted resistor arrays.

[0070] In some embodiments, the calibration circuit provided in this application may include a clock circuit, a logic circuit, a first sample-and-hold circuit, a second sample-and-hold circuit, and a comparator.

[0071] Figure 6 This is a schematic diagram of the clock circuit provided in an embodiment of this application. The clock circuit 310 is configured to operate according to the first capacitor voltage V. c * Generate the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4. Figure 7 yes Figure 6 The diagram shows an example of the timing waveform of the signal output by the clock circuit.

[0072] Reference Figure 6 As shown, in some embodiments, the clock circuit 310 may include a first zero-crossing detector 311, a first inverter 3121, a second inverter 3122, a third inverter 3123, a fourth inverter 3124, a fifth inverter 3125, a sixth inverter 3126, a seventh inverter 3127, a delay unit 313, a first AND gate circuit 3141, a second AND gate circuit 3142, a third AND gate circuit 3143, a fourth AND gate circuit 3144, a first signal frequency value acquisition circuit 3151, a second signal frequency value acquisition circuit 3152, and an OR gate circuit 316. The first capacitor voltage V c * and voltage divider signal V BThe input is a first zero-crossing detector 311. The output of the first zero-crossing detector 311 is coupled to the input of the first inverter 3121 and the first input of the first AND gate 3141. The output of the first inverter 3121 is coupled to the input of the delay unit 313. The output of the delay unit 313 is coupled to the inputs of the second inverter 3122, the fifth inverter 3125, and the second input of the second AND gate 3142. The input of the first inverter 3121 is also coupled to the inputs of the third inverter 3123 and the fourth inverter 3124. The output of the second inverter 3122 is coupled to the second input of the first AND gate 3141. The output of the third inverter 3123 is coupled to the first input of the second AND gate 3142. The output of the fourth inverter 3124 is coupled to the input of the first signal frequency acquisition circuit 3151. The output of the first signal frequency acquisition circuit 3151 is coupled to the input of the sixth inverter 3126. The output of the sixth inverter 3126 is coupled to the first input of the third AND gate circuit 3143. The output of the fifth inverter 3125 is coupled to the input of the second signal frequency acquisition circuit 3152. The output of the second signal frequency acquisition circuit 3152 is coupled to the second input of the third AND gate circuit 3143. The output of the third AND gate circuit 3143 is coupled to the second input of the fourth AND gate circuit 3144 and the second input of the OR gate circuit 316. The state signal STATE of the clock circuit 310 is input to the first input of the fourth AND gate circuit 3144 and the first input of the OR gate circuit 316 via the seventh inverter 3127. The enable signal EN is input to the first signal frequency acquisition circuit 3151 and the second signal frequency acquisition circuit 3152. Ultimately, the output of the first AND gate 3141 outputs the first clock signal CLK1, the output of the second AND gate 3142 outputs the second clock signal CLK2, the output of the fourth AND gate 3144 outputs the third clock signal CLK3, and the output of the OR gate 316 outputs the fourth clock signal CLK4. The delay unit 313 is configured to delay by one-quarter of a cycle, and the first signal frequency acquisition circuit 3151 and the second signal frequency acquisition circuit 3152 are configured to acquire one-sixteenth of the signal frequency. Voltage divider signal V B An additional voltage divider circuit can be set up to obtain the voltage, which will not be detailed here. As an example, Figure 7 The clock circuit 310 is shown based on the first capacitor voltage V. c * Generate the first clock signal CLK1, the second clock signal CLK2, and the voltage V of the first capacitor by the differentiator. c * The second capacitor voltage V generated by differentiation C **The signal timing waveform diagram.

[0073] Figure 8 This is a schematic diagram of the logic circuit provided in an embodiment of this application. The output terminal of the logic circuit 320 is coupled to the second input terminal of the integrator circuit and the second input terminal of the differentiator circuit, respectively. The logic circuit 320 is used to adjust the resistance values ​​of the first adjustable resistor and the second adjustable resistor simultaneously according to the fourth clock signal CLK4.

[0074] Reference Figure 8 As shown, in some embodiments, the logic circuit 320 may include a plurality of flip-flops 321 and a plurality of logic gates 322 connected in sequence. The plurality of flip-flops 321 and the plurality of logic gates 322 correspond one-to-one with a plurality of adjustable switches of the first adjustable resistor or a plurality of adjustable switches of the second adjustable resistor. The first input terminal of the logic gate 322 is coupled to the first output terminal (Q terminal) of the corresponding flip-flop 321. The output terminal of the logic gate 322 is coupled to the second input terminal of the next logic gate 322 and the first input terminal of the flip-flop 321 corresponding to the next logic gate 322. The second input terminal of the first logic gate 322 and the first input terminal (T terminal) of the corresponding flip-flop 321 are used to receive the state signal STATE output by the comparator. The second input (>) of each flip-flop 321 is used to receive the fourth clock signal CLK4, the third input (CLR) of each flip-flop 321 is used to receive the first enable signal EN, the second output (QB) of each flip-flop 321 is coupled to the control input of the corresponding adjustable switch, and the second output (QB) of each flip-flop 321 is used to output the switching control signal of the corresponding adjustable switch. For example: combined with Figure 5 and Figure 8 The second output terminal of the first flip-flop 321 outputs the switch control signal SW0 for the adjustable switch corresponding to the fifth variable resistor; the second output terminal of the second flip-flop 321 outputs the switch control signal SW1 for the adjustable switch corresponding to the fourth variable resistor; the second output terminal of the third flip-flop 321 outputs the switch control signal SW2 for the adjustable switch corresponding to the third variable resistor; the second output terminal of the fourth flip-flop 321 outputs the switch control signal SW3 for the adjustable switch corresponding to the second variable resistor; and the second output terminal of the fifth flip-flop 321 outputs the switch control signal SW4 for the adjustable switch corresponding to the first variable resistor.

[0075] Figure 9 This is a schematic diagram of the structure of the first sample-and-hold circuit and the second sample-and-hold circuit provided in the embodiments of this application. In the embodiments of this application, the first input terminal of the first sample-and-hold circuit 330 is coupled to the output terminal of the integrator circuit. The first sample-and-hold circuit 330 is used to measure the second inductor voltage V according to the first clock signal CLK1 and the second clock signal CLK2.L ** Peak sampling is performed to obtain the third inductor voltage V. L *** The first input terminal of the second sample-and-hold circuit 340 is coupled to the output terminal of the differentiating circuit. The second sample-and-hold circuit 340 is used to measure the voltage V of the second capacitor according to the first clock signal CLK1 and the second clock signal CLK2. C ** Peak sampling is performed to obtain the voltage V of the third capacitor. C *** .

[0076] Reference Figure 9 As shown, in some embodiments, the first sample-and-hold circuit 330 and the second sample-and-hold circuit 340 have the same structure, both including a first trigger switch 331, a first operational amplifier 332, a second trigger switch 333, and a second operational amplifier 334. The first terminal of the first trigger switch 331 is used to receive the corresponding second inductor voltage V. L ** Or the voltage V of the second capacitor C ** The second terminal of the first trigger switch 331 is coupled to the non-inverting input (+) of the first operational amplifier 332, and the inverting input (-) of the first operational amplifier 332 is coupled to its output. The output of the first operational amplifier 332 is also coupled to the first terminal of the second trigger switch 333. The second terminal of the second trigger switch 333 is coupled to the non-inverting input (+) of the second operational amplifier 334, and the inverting input (-) of the second operational amplifier 334 is coupled to its output. The output of the second operational amplifier 334 is used to output the corresponding third inductor voltage V. L *** Or the voltage V of the third capacitor C *** The second terminal of the first trigger switch 331 is also connected to a first grounding capacitor 335, and the second terminal of the second trigger switch 333 is also connected to a second grounding capacitor 336. The third terminal of the first trigger switch 331 is used to receive the first clock signal CLK1, and the third terminal of the second trigger switch 333 is used to receive the second clock signal CLK2. The first trigger switch 331 and the second trigger switch 333 can be transistors. The first grounding capacitor 335 and the second grounding capacitor 336 are used for filtering. Thus, in this embodiment, since V... C ** (or V) L ** Since the current is alternating current, the sample-and-hold circuit (S&H) can store its peak value as V at the appropriate time. C *** (or V)L *** In other embodiments, the first sample-and-hold circuit 330 and the second sample-and-hold circuit 340 may also employ other structures, for example, they may include a first operational amplifier 332, a second operational amplifier 334, a second trigger switch 333, and a grounding capacitor, wherein the non-inverting input terminal of the first operational amplifier 332 is used to receive the corresponding second inductor voltage V. L ** Or the voltage V of the second capacitor C ** The inverting input of the first operational amplifier 332 is coupled to the inverting input of the second operational amplifier 334 through an equivalent resistance. The output of the first operational amplifier 332 is coupled to the first terminal of the second trigger switch 333, and the second terminal of the second trigger switch 333 is coupled to the non-inverting input of the second operational amplifier 334. The second terminal of the second trigger switch 333 is also connected to a grounding capacitor. The third terminal of the second trigger switch 333 is used to receive the second clock signal CLK2, and the output of the second operational amplifier 334 is used to output the corresponding third inductor voltage V. L *** Or the voltage V of the third capacitor C *** The embodiments of this application do not specifically limit the structure of the sampling circuit.

[0077] Figure 10 This is a schematic diagram of the comparator provided in an embodiment of this application. In this embodiment, the first input terminal of comparator 350 is coupled to the output terminal of the first sample-and-hold circuit, and the second input terminal of comparator 350 is coupled to the output terminal of the second sample-and-hold circuit. Comparator 350 is used to compare the third inductor voltage V in real time according to the third clock signal CLK3. L *** and the voltage V of the third capacitor C *** The comparison result is output as a status signal STATE, which indicates the voltage V of the third inductor. L *** and the voltage V of the third capacitor C *** Are they the same?

[0078] Reference Figure 10 As shown, in some embodiments, structure e is the logic structure of comparator 350, and structure f is the specific design structure of comparator 350. Structure e and structure f represent the same structure. Wherein, S represents the SET terminal, R represents the RESET terminal, EN represents the enable terminal, and V... DD 351 represents the power input terminal, STATE represents the output status signal, 351 represents a NAND gate, and 352 represents a transistor.

[0079] Figure 11 yes Figure 10 A schematic diagram of the comparator's output is shown. (Refer to...) Figure 11 As shown, since the resistance values ​​of both the first and second adjustable resistors are initially at their minimum values, V L *** >V C *** The comparator output STATE is high. As the resistance values ​​of the first and second adjustable resistors increase, V... L *** Decrease, V C *** Simultaneously increase until V L *** Less than V C *** The comparison result STATE output by the comparator is low.

[0080] Figure 12 This is a schematic diagram of the overall timing logic of the calibration circuit provided in the embodiments of this application. (Refer to...) Figure 12 As shown, CLK1 is a clock signal with a frequency of f0. Initially at point E, the enable signal EN is low, and the logic circuit is driven to a reset state. When the comparator output status signal STATE is high, the switch control signals SW0-4 received by the adjustable switches (i.e., switches 0-4) are all high. As the enable signal EN goes high, calibration begins. The comparator compares V when clock signal 3 is high. L *** and V C *** Since the resistance R of the first and second adjustable resistors is at its minimum value, V L *** >V C *** The falling edge of clock signal 4 triggers the logic circuit, causing SW0-4 to continue counting downwards. The integrator and differentiator circuits require time to recover to a stable state after a change in resistance R; therefore, the frequency of clock signal 4 is set to f0 / 16. As the resistance R increases, V... L *** Decrease, V C *** Simultaneously increase until V L *** Less than V C *** At this point, the comparator output status signal STATE is low, and the calibration ends on the falling edge. After calibration, clock signals 3 and 4 at point F are pulled low and high, respectively. The comparator and logic circuit stop working, and STATE remains high until the measurement is complete.

[0081] Figure 13 yes Figure 2 A schematic diagram of the first and second filter circuits is shown in this embodiment. In this application embodiment, the first filter circuit is used to filter the inductance L in the TX coil. TX Voltage V across the terminals L After attenuation, low-pass filtering, and subtraction, the first inductor voltage V is obtained. L * The second filter circuit is used to filter the capacitor C in the TX coil. TX Voltage V across the terminals C After attenuation, low-pass filtering, and subtraction, the voltage V of the first capacitor is obtained. C * .

[0082] Reference Figure 13 As shown, in some embodiments, the first filtering circuit includes a first attenuator 410, a first low-pass filter (LPF) 420, a second attenuator 430, a second low-pass filter (LPF) 440, and a first differential circuit 450. Specifically, the voltage at the first connection point A is attenuated by the first attenuator 410 and low-pass filtered by the first low-pass filter 420 to eliminate frequency components other than frequency f0. The resulting signal is input to the first differential circuit 450. The voltage at the second connection point B is attenuated by the second attenuator 430 and low-pass filtered by the second low-pass filter 440 to eliminate frequency components other than frequency f0. The resulting signal is also input to the first differential circuit 450. The difference between the two voltage signals yields the first inductor voltage V. L * The second connection point B is located at inductor L. TX and capacitor C TX Between, the first connection point A is located at inductor L TX One side.

[0083] The second filtering circuit includes a third attenuator 510, a third low-pass filter (LPF) 520, a fourth attenuator 430, a fourth low-pass filter (LPF), and a second differential circuit 530. The fourth attenuator and the fourth low-pass filter (LPF) can be replaced by the second attenuator 430 and the second low-pass filter (LPF) 440, respectively, meaning the voltage at the second connection point B can be combined into a single filtering path. Specifically, the voltage at the second connection point B is attenuated by the second attenuator 430 and low-pass filtered by the second low-pass filter 440, eliminating frequency components other than frequency f0. The resulting signal is simultaneously input to the second differential circuit 530. Similarly, the voltage at the third connection point C is attenuated by the third attenuator 510 and low-pass filtered by the third low-pass filter 520, eliminating frequency components other than frequency f0. The resulting signal is also input to the second differential circuit 530. The difference between the two voltage signals yields the first capacitor voltage V. C * The third connection point C is located at capacitor C. TX On the other side.

[0084] In this embodiment, the attenuation coefficients of all attenuators in the first and second filter circuits are the same, β. Thus, the low-pass filter is used to eliminate any frequency components other than f0. To ensure that the loss at f0 is negligible and the frequency component at 3f0 is sufficiently reduced, a fifth-order Chebyshev filter can be selected, in which the loss at f0 is included. Since both the voltage across the TX coil and the current flowing through the TX coil are affected by β, changes in β will not reduce the reliability of the circuit performance.

[0085] Figure 14 This is a schematic diagram showing the signal waveform timing of the second inductor voltage and the second capacitor voltage during the calibration process of the AC current sensor provided in this application embodiment. (Refer to...) Figure 14 As shown, for on-chip implementation, the time constant RC used by the differentiating and integrating circuits is the same. However, due to variations in the time constant RC with the manufacturing process, the current detection accuracy decreases. Therefore, to compensate for the changes in the resistance R and capacitance C of the differentiating circuit in the current sensor, the voltage V across the inductor in the TX coil is... L and the voltage V across the capacitor C Both are measured, and the adjustable resistor R in the differentiating and integrating circuits is calibrated using a 5-bit digital calibrator, so that the second inductor voltage V... L ** =Second capacitor voltage V C ** The second inductor voltage signal V is obtained by integrating across the inductor. L **During calibration, the voltage gradually decreases, and the second capacitor voltage signal V obtained by differentiating the capacitor terminals is... C ** The time constant RC is gradually increased during calibration until they become equal. After calibration, the time constant RC can be determined by the following formula (1):

[0086]

[0087] In formula (1), f0 is the voltage V of the first inductor. L * and the voltage V of the first capacitor C * The frequency, ω0 is L TX The angular frequency of resonance.

[0088] In this embodiment of the application, after time constant RC calibration, the second capacitor voltage V output by the differentiating circuit is... C ** It can be used to convert the current flowing through the TX coil according to a preset conversion relationship. Specifically, it can be determined by the following formula (2):

[0089]

[0090] In formula (2), I TX Where β is the current flowing through the TX coil, and C is the attenuation coefficient. TX The capacitance value of the TX coil is related to L. TX Resonance, L TX V is the inductance value of the TX coil. C ** This is the voltage of the second capacitor.

[0091] Formula (2) can be derived from the following formula (3):

[0092]

[0093] In formula (3), I TX Where β is the current flowing through the TX coil, and C is the attenuation coefficient. TX The capacitance value of the TX coil is related to L. TX Resonance, L TX f is the inductance value of the TX coil, and f0 is the voltage V across the first inductor. L * and the voltage V of the first capacitor C * The frequency, V C C TX The voltage across the terminals, V L For L TX The voltage across the terminals, V C **V is the voltage of the second capacitor. L ** V is the voltage across the second inductor. C *** The voltage of the third capacitor is V. L *** RC is the voltage of the third inductor and the time constant.

[0094] After calibration, V C *** =V L *** Formula (2) can then be derived. The calibrated time constant RC can be calculated from f0, because C TX and L TX Given that V C ** The amplitude is measured by V C *** Therefore, we can obtain the accurate I. TX After calibration, the total resistance of the integrating and differentiating circuits remains unchanged, and the AC current sensor begins to operate.

[0095] In addition, the AC current sensor provided in this application embodiment may also include a voltage measurement circuit, which can be used to measure the voltage and phase information across the TX coil.

[0096] Figure 15 This is a schematic diagram of the voltage measurement circuit provided in an embodiment of this application. (Refer to...) Figure 15 As shown, the voltage measurement circuit 600 includes a third differential circuit 610, a third sample-and-hold circuit (S&H) 620, a second clock circuit (CLKgenerator II) 630, a second zero-crossing detector 640, a third zero-crossing detector 650, an XOR gate 660, and a fifth low-pass filter (LPF) 670. The third differential circuit 610 measures the voltage V at the first connection point A. A and the voltage V at the third connection point C C After subtraction, the voltage across the TX coil is obtained, and then AMP_V is obtained through the third sample-and-hold circuit 620. This AMP_V is simultaneously input to the input of the second clock circuit 630 and the input of the third zero-crossing detector 650. The input of the third zero-crossing detector 650 also receives a voltage divider signal V. B Voltage divider signal V B With the voltage V of the third capacitor C *** The outputs of the second zero-crossing detector 640 and the third zero-crossing detector 650 are fed into a common input. After passing through an XOR gate 660 and a fifth low-pass filter 670, the phase information PHASE is obtained.

[0097] Thus, the AC current sensor provided in this application embodiment has a current calibration function. The calibration process does not require the use of a commercial current sensor to provide a reference current. It can calibrate the time constants of the differentiating circuit and the integrating circuit, making them unaffected by process changes. As a result, the current detection accuracy after calibration is not affected by the on-chip component parameters, resulting in high current measurement accuracy. Moreover, it has a compact structure and is easy to integrate.

[0098] In addition, this application embodiment also provides a wireless charging chip, including the AC current sensor in the above application embodiment. It has a compact structure, a high degree of integration, a small overall area, and the current detection accuracy is not affected by the on-chip component parameters, resulting in high current measurement accuracy.

[0099] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. An alternating current sensor, characterized by The calibration circuit comprises: An integrating circuit is configured to receive a first inductor voltage V through a first input terminal of the integrating circuit. L * and the voltage V of the first inductor L * Integrating, a second inductor voltage V is generated. L ** The first inductor voltage V L * V is the voltage across the inductor in the TX coil. L The voltage obtained after filtering, the integrating circuit includes a first adjustable resistor; A differentiating circuit is configured to receive a first capacitor voltage V through a first input terminal of the differentiating circuit. C * and the voltage V of the first capacitor C * Differentiate to generate the second capacitor voltage V C ** The first capacitor voltage V C * V is the voltage across the capacitor in the TX coil. C The voltage obtained after filtering, the differentiating circuit includes a second adjustable resistor; a calibration circuit configured to calibrate the first capacitor voltage V c * generate a clock signal, and simultaneously adjust resistance values of the first adjustable resistor and the second adjustable resistor according to the clock signal, and compare the third inductor voltage V L *** and the third capacitor voltage V C *** , until the third inductor voltage V L *** is the same as the third capacitor voltage V C *** , calibration is completed, the third inductor voltage V L *** is obtained after peak sampling of the second inductor voltage V L ** , and the third capacitor voltage V C *** is obtained after peak sampling of the second capacitor voltage V C ** ; Wherein, after the calibration is completed, the second capacitor voltage V C ** for converting into a current flowing through the TX coil according to a preset conversion relationship; the current flowing through the TX coil is determined by the following formula: where I TX is the current flowing through the TX coil, β is a decay coefficient, C TX is the capacitance value of the TX coil, and L TX is the inductance value of the TX coil, V TX C ** is the second capacitor voltage.​ 2. The alternating current sensor of claim 1, wherein, The logic circuit is coupled with the second input end of the integral circuit and the second input end of the differential circuit respectively, and is configured to adjust the resistance values of the first adjustable resistor and the second adjustable resistor simultaneously according to the fourth clock signal CLK4. a clock circuit configured to generate a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4 in accordance with the first capacitor voltage V c * a clock circuit configured to generate a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4 in accordance with the first capacitor voltage V The first adjustable resistor and the second adjustable resistor are of the same structure and each comprises: a first sample-and-hold circuit, a first input terminal of the first sample-and-hold circuit being coupled with an output terminal of the integration circuit, the first sample-and-hold circuit being configured to sample the second inductor voltage V L ** perform peak sampling to obtain the third inductor voltage V L *** ; a second sample-and-hold circuit, a first input terminal of the second sample-and-hold circuit being coupled with an output terminal of the differential circuit, the second sample-and-hold circuit being configured to sample the second capacitor voltage V C ** perform peak sampling to obtain the third capacitor voltage V C *** ; a comparator, a first input terminal of the comparator being coupled with an output terminal of the first sample-and-hold circuit, a second input terminal of the comparator being coupled with an output terminal of the second sample-and-hold circuit; the comparator being configured to compare the third inductor voltage V L *** and the third capacitor voltage V C *** in real time according to the third clock signal CLK3, and output a comparison result, the comparison result being configured to indicate whether the third inductor voltage V L *** and the third capacitor voltage V C *** are the same.

3. The alternating current sensor of claim 2, wherein, The fixed resistor and the plurality of variable resistors are connected in series, and each variable resistor has a preset proportional relationship with the resistance value of the fixed resistor. The plurality of adjustable switches correspond to the plurality of variable resistors one by one, and the adjustable switch is connected in parallel across the corresponding variable resistor, and the adjustable switch comprises a control input end for receiving a switch control signal, and is configured to be turned on or off under the control of the switch control signal. The logic circuit comprises a plurality of flip-flops and a plurality of logic gates connected in sequence, and the plurality of flip-flops and the plurality of logic gates correspond to the plurality of adjustable switches of the first adjustable resistor or the plurality of adjustable switches of the second adjustable resistor one by one.

4. The alternating current sensor of claim 3, wherein, The first input end of the logic gate is coupled with the first output end of the corresponding flip-flop, and the output end of the logic gate is coupled with the second input end of the next logic gate and the first input end of the corresponding flip-flop of the next logic gate, wherein the second input end of the first logic gate and the first input end of the corresponding flip-flop are configured to receive the state signal output by the comparator. The second input end of each flip-flop is configured to receive the fourth clock signal CLK4, the third input end of each flip-flop is configured to receive a first enable signal, the second output end of each flip-flop is coupled with the control input end of the corresponding adjustable switch, and the second output end of each flip-flop is configured to output the switch control signal of the corresponding adjustable switch. The first sampling and holding circuit and the second sampling and holding circuit are of the same structure and each comprises a first trigger switch, a first operational amplifier, a second trigger switch and a second operational amplifier.

5. The alternating current sensor of claim 2, wherein, The second end of the first trigger switch is further connected with a first grounding capacitor, the second end of the second trigger switch is further connected with a second grounding capacitor, the third end of the first trigger switch is configured to receive the first clock signal CLK1, and the third end of the second trigger switch is configured to receive the second clock signal CLK2. The first end of the first trigger switch is used for receiving the corresponding second inductor voltage V L ** Or the second capacitor voltage V C ** The second end of the first trigger switch is coupled with the non-inverting input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is coupled with the output terminal of the first operational amplifier, the output terminal of the first operational amplifier is also coupled with the first end of the second trigger switch, the second end of the second trigger switch is coupled with the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is coupled with the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is used for outputting the corresponding third inductor voltage V L *** Or the third capacitor voltage V C *** ; The integral circuit further comprises a first capacitor connected in series with the first adjustable resistor.

6. The alternating current sensor of claim 1, wherein, The differential circuit further comprises a second capacitor connected in series with the second adjustable resistor. The first adjustable resistor is distanced from one end of the first capacitor, and the first capacitor is distanced from one end of the first adjustable resistor, which are collectively configured as a first input end of the integration circuit, and a voltage across the first capacitor is configured as the second inductor voltage V L ** .

7. The alternating current sensor of claim 6, wherein, The calibration circuit further comprises: The second adjustable resistor is distanced from one end of the second capacitor, and the second capacitor is distanced from one end of the second adjustable resistor, which are collectively configured as a first input end of the differential circuit, and a voltage across the second adjustable resistor is configured as the second capacitor voltage V C ** .

8. The alternating current sensor of claim 1, wherein, The calibration circuit further comprises: a first filter circuit for filtering a voltage V L After attenuation, low-pass filtering and differencing, respectively, the first inductance voltage V L * ; a second filter circuit for filtering a voltage V C After attenuation, low-pass filtering and differencing, respectively, the first capacitor voltage V C * .

9. A wireless charging chip, comprising: The calibration circuit further comprises:

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