A method and apparatus for acquiring and analyzing space radio signals

Abstract

This application discloses a method and apparatus for acquiring and analyzing space radio signals. The method includes: a lower-level computer receiving configuration parameters and a start acquisition command sent by a upper-level computer, and acquiring space radio signals according to the configuration parameters. The configuration parameters include a first time resolution, a first frequency resolution, and a first acquisition mode. The first time resolution is one of several preset time resolutions, the first frequency resolution is one of several preset frequency resolutions, and the first acquisition mode is either a time-domain acquisition mode or a frequency-domain acquisition mode. This supports multiple time resolutions and multiple frequency resolutions, with the upper-level computer setting the actual resolution requirements to the lower-level computer, offering greater flexibility compared to traditional single time or frequency resolutions. Furthermore, it supports both time-domain and frequency-domain acquisition modes, allowing for the setting of various working mechanisms and seamless switching between time-domain and frequency-domain acquisition.

Description

Technical Field

[0001] This application relates to the field of astronomical observation technology, and in particular to a method and apparatus for acquiring and analyzing space radio signals. Background Technology

[0002] Radio astronomy observations primarily utilize radio telescopes to collect, measure, and analyze celestial radiation signals to determine astronomical data. With the continuous development of radio signal observation technology, high-precision radio observation systems have become the goal. However, traditional space radio signal acquisition has relatively low resolution, requiring the acquisition of more data to obtain more accurate astronomical data. Furthermore, space radio signal acquisition can be divided into time-domain and frequency-domain acquisition. Current acquisition methods either support time-domain or frequency-domain acquisition, which is inflexible and cannot meet the demands for high precision. Therefore, how to achieve space radio signal acquisition that meets the requirements of high-precision radio observation systems is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a method and apparatus for acquiring and analyzing space radio signals, which can improve the acquisition resolution, thereby reducing the amount of acquired data. It can also switch between time domain acquisition and frequency domain acquisition according to the data accuracy requirements, making it more flexible.

[0004] Firstly, a method for acquiring and analyzing space radio signals is provided. The execution entity of this method is a communication device, such as an FPGA. This method is applied to a space radio signal acquisition and analysis system, which includes a host computer and a slave computer. The method includes: the slave computer receiving configuration parameters and a start acquisition command sent by the host computer, and acquiring space radio signals according to the configuration parameters. The configuration parameters include a first time resolution, a first frequency resolution, and a first acquisition mode. The first time resolution belongs to multiple pre-set time resolutions, the first frequency resolution belongs to multiple pre-set frequency resolutions, and the first acquisition mode belongs to a time-domain acquisition mode and a frequency-domain acquisition mode. For example, the first acquisition mode is a time-domain acquisition mode, or the first acquisition mode is a frequency-domain acquisition mode. The start acquisition command is used to instruct the acquisition of space radio signals.

[0005] In this embodiment, multiple time resolutions and multiple frequency resolutions are supported, allowing for settings to be configured from the host computer to the slave computer based on actual resolution requirements when acquiring space radio signals. Compared to traditional single time or frequency resolutions, this embodiment allows for flexible adjustment of both time and frequency resolutions. Furthermore, traditional single acquisition modes either acquire time-domain or frequency-domain data. This embodiment supports both time-domain and frequency-domain acquisition modes, enabling flexible parameter adjustment and better meeting the application needs of radio observation.

[0006] In a possible implementation, the lower-level machine is equipped with an anti-aliasing filter. The method further includes: the lower-level machine samples multiple sub-bands of the frequency channelization using the anti-aliasing filter, and folds the signals output from the multiple sub-bands into a Nyquist zone based on undersampling spectrum folding; and restores the spectrum to the initial frequency band based on the Nyquist zones where the multiple sub-bands are located. In this scheme, the lower-level machine folds the signals output from the multiple sub-bands into a Nyquist zone based on undersampling spectrum folding, thereby achieving the purpose of acquiring the entire spectrum. Filtering the broadband signal into a narrowband signal before sampling can reduce the sampling rate and achieve higher frequency resolution with a lower number of FFT transform points.

[0007] In a possible implementation, the method further includes: the host computer mapping the first time resolution and the first frequency resolution to the number of integration segments and the number of FFT points, respectively, wherein the number of integration segments and the number of FFT points are stored in the form of a table; and the slave computer flexibly configures the parameters by looking up the table.

[0008] In a possible implementation, the method further includes: the host computer switching the acquisition mode according to a trigger task and sending configuration parameters to the slave computer. The trigger task can be a pre-set list of tasks or an event-triggered task; correspondingly, the slave computer receives the configuration parameters sent by the host computer and switches the acquisition mode without data loss. In this scheme, the host computer can switch the acquisition mode according to a trigger task, which can be a pre-set list of tasks or an event-triggered task, thus better meeting actual acquisition needs.

[0009] In one possible implementation, the lower-level machine is currently in a working state. The lower-level machine switches acquisition modes without losing data. The method further includes: the lower-level machine switches acquisition modes when it determines that the amount of data transmitted is an integer multiple of a preset transmission size, where the preset transmission size is the same as the Direct Memory Access (DMA) size. In this scheme, the lower-level machine does not immediately switch acquisition modes upon receiving a mode switching command. Instead, it switches modes only after ensuring that a data frame has ended and the DMA block corresponding to the current acquisition mode is full. This allows for flexible switching between two acquisition modes while ensuring the continuity of acquired data.

[0010] In possible implementations, the mode switching instruction is either a periodically sent instruction from the host computer, or it is triggered by a specific event, whereby the slave computer reverts from the current acquisition mode to the acquisition mode before the switch when the specific event ceases to occur. That is, the mode switching instruction can be a predefined periodically triggered instruction or a predefined specific event triggered by a specific event. For example, a specific event might include a counter value being the same as the size of the direct memory access (DMA) corresponding to the current acquisition mode.

[0011] In one possible implementation, the lower-level machine is equipped with a first buffer, the capacity of which is higher than a first threshold to ensure that data is not lost during transmission. The first buffer buffers data when the high-speed serial computer expansion bus (PCIe) is busy. The PCIe connection to the upper-level machine facilitates data exchange. When switching acquisition modes, the first buffer transmits data for the next acquisition mode after completing the transmission of data for the current acquisition mode.

[0012] In a possible implementation, the host computer and the slave computer are connected to an external time and frequency system. This external time and frequency system provides network time to the host computer via the Network Time Protocol (NTP), and also provides serial port B-code time and a 10MHz frequency standard signal to the slave computer. In this embodiment, both external clock input and internal clock input modes are supported to ensure the normal operation of the system as much as possible.

[0013] In possible implementations, the method further includes:

[0014] When the time B code provided by the external time and frequency system is invalid, the lower-level machine uses the system time sent by the upper-level machine as the base time for timing. When the 10MHz frequency standard signal provided by the external time and frequency system is invalid, the lower-level machine uses the clock signal generated by the onboard crystal oscillator as the clock source. The system provides a timestamp with an accuracy higher than 0.1 milliseconds. This scheme provides a high-precision adaptive clock source selection algorithm to provide the system with a timestamp with an accuracy higher than 0.1 milliseconds.

[0015] In a possible implementation, the method further includes: the lower-level machine and the upper-level machine synchronizing the system time with the external time-frequency system. Essentially, a proposed time correction algorithm synchronizes the system time with the time-frequency system. This time correction algorithm includes filtering, correction, and calibration functions. The filtering primarily removes glitches from the input signal of the external time-frequency system. The correction addresses the delay caused during filtering and the time difference between UTC and Beijing time, correcting the time to standard Beijing time. The calibration function synchronizes the system time with the external time-frequency system based on a 1pps pulse signal provided by the external time-frequency system.

[0016] Secondly, a space radio signal acquisition and analysis device is provided, which has the function of implementing the behavior described in the first aspect of the method embodiment. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described function. The communication device includes a communication interface and a processor, and optionally, a memory. The memory stores computer programs or instructions, and the processor is coupled to the memory and the communication interface. When the processor executes the computer program or instructions, it causes the communication device to execute the method described in the above method embodiment.

[0017] Thirdly, this application provides a computer-readable storage medium storing a computer program that, when executed, implements the method described in the first aspect. Attached Figure Description

[0018] Figure 1 A block diagram illustrating the principle of space radio signal acquisition and analysis provided in this application embodiment;

[0019] Figure 2 This is a schematic diagram of the data acquisition and analysis system provided in the embodiments of this application;

[0020] Figure 3 A schematic diagram of the undersampling spectrum folding process provided in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the undersampling spectrum folding characteristics provided in an embodiment of this application;

[0022] Figure 5 This is a structural block diagram of the spectrum calculation module provided in an embodiment of this application;

[0023] Figure 6 A flowchart illustrating the operation of the spectrum integration module provided in this application embodiment;

[0024] Figure 7 A state machine diagram of the spectrum calculation module provided in this application embodiment;

[0025] Figure 8 Write state machine diagram of the spectrum integration module provided in the embodiments of this application;

[0026] Figure 9 Read state machine diagram of the spectrum integration module provided in the embodiments of this application

[0027] Figure 10 This is a schematic diagram of the time-frequency domain switching structure provided in an embodiment of this application;

[0028] Figure 11 A schematic diagram of the timing mechanism for switching time-frequency domain modules provided in an embodiment of this application.

[0029] Figure 12 A schematic diagram of the main state for selecting the acquisition mode provided in the embodiments of this application.

[0030] Figure 13 A schematic diagram of the sub-states for selecting the acquisition mode provided in the embodiments of this application.

[0031] Figure 14 A state machine diagram of the data upload control module provided in the embodiments of this application;

[0032] Figure 15 A schematic flowchart illustrating the method for acquiring and analyzing space radio signals provided in this application embodiment;

[0033] Figure 16 A block diagram illustrating the principle of adaptive clock source selection provided in an embodiment of this application;

[0034] Figure 17 A schematic diagram illustrating the adaptive clock source selection process provided in an embodiment of this application;

[0035] Figure 18 This is a schematic diagram of B-code symbols provided in an embodiment of this application;

[0036] Figure 19 This is a schematic diagram of the B-code encoding format provided in the embodiments of this application;

[0037] Figure 20 A schematic diagram of the working state machine of the atomic clock working state discrimination module provided in the embodiments of this application;

[0038] Figure 21 A schematic diagram illustrating the workflow of the real-time time error correction module provided in this application embodiment;

[0039] Figure 22 This is a structural block diagram of a large-capacity cache module provided in an embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings.

[0041] Radio astronomy observation primarily utilizes radio telescopes to collect, measure, and analyze celestial radiation signals to determine astronomical data. With the continuous development of radio signal observation technology, high-precision radio observation systems have become the goal. For example, a high-precision solar radio observation system is a sought-after objective. However, traditional space radio signal acquisition has low resolution, requiring the acquisition of more data to obtain more accurate astronomical data, which is unsuitable for high-precision solar radio observation systems. In the field of radio observation, resolution mainly includes time resolution and frequency resolution. Time resolution ranges from milliseconds to seconds; frequency resolution ranges from several kHz to tens of MHz. Space radio signal acquisition can be divided into two categories: time-domain acquisition and frequency-domain acquisition. Time-domain acquisition, for example, involves acquiring time-domain signals after analog-to-digital conversion using a signal acquisition card. Real-time spectrum analysis is then performed based on the time-domain signals to obtain effective astronomical data. As the requirements for accuracy and observation frequency bands in astronomical observations gradually increase, the difficulty of real-time spectrum analysis of time-domain signals also increases accordingly. In contrast, hardware-accelerated methods can compute frequency domain data in hardware and then analyze it, thereby improving acquisition and analysis efficiency. However, current acquisition of space radio signals is either in the time domain or the frequency domain, which is not flexible enough and cannot meet the requirements for high precision.

[0042] Therefore, the solutions provided in this application embodiment are as follows. This application embodiment can support both time-domain and frequency-domain acquisition, allowing for flexible switching between the two domains according to actual needs. Furthermore, the time resolution and frequency resolution can be flexibly adjusted, satisfying both high-precision measurement requirements and maximizing measurement efficiency.

[0043] The technical solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0044] Please see Figure 1 This is a block diagram illustrating the principle of acquiring and analyzing space radio signals provided in an embodiment of this application. Figure 1 Take a space radio signal with two polarization directions as an example. A space radio signal with one polarization direction can correspond to a broadband radio front-end (which can also be considered an antenna). The broadband radio front-end receives the space radio signal and transmits it to a filter, which then filters the received space radio signal. Figure 1Taking a broadband RF front-end corresponding to one bandwidth filter bank as an example, one bandpass filter bank includes four bandpass filters. The filtered space radio signals are amplified and output by an amplifier. The acquisition and analysis system can be connected to the amplifier to acquire and analyze the space radio signals output by the amplifier. Afterwards, the acquisition and analysis system can output the obtained astronomical data to a storage array for storage and supports an Ethernet interface for remote operation and control via Ethernet. The acquisition and analysis system is connected to an external clock system. It should be understood that... Figure 1 The acquisition and analysis system has at least 8 channels, with one filter for each channel.

[0045] In this embodiment of the application, the undersampling spectrum folding characteristic is employed, such as... Figure 3 As shown, during the sampling of spatial signals, signals within each Nyquist zone overlap. For the first Nyquist zone, signals in the second, third, fourth... Nyquist zones will eventually fold into the first Nyquist zone. When acquiring signals, each Nyquist zone is sampled through separate channels. An anti-aliasing filter is added to the front end of each channel on the AD board to attenuate signals outside a certain Nyquist zone. Then, a lower sampling rate ADC is used to acquire the signal. The signal spectrum will fold into the first Nyquist zone. After spectrum shifting, the signal is moved back to its original frequency band, allowing for distortion-free recovery of the original signal.

[0046] During the signal transfer process, the spectral folding pattern of the signal is as follows: Figure 4 As shown. The signals of the first and second Nyquist zones with respect to f S / 2 mirror symmetry, the signals of the third and fourth Nyquist zones with respect to f S / 2 is mirror symmetric, and simultaneously, the first and second Nyquist zones and the third and fourth Nyquist zones are related to f. s symmetry.

[0047] This application's embodiments primarily focus on how to achieve the acquisition and analysis of space radio signals. First, it introduces... Figure 1 Implementation of the data acquisition and analysis system.

[0048] The data acquisition and analysis system consists of a lower-level computer and a higher-level computer. The higher-level computer can be used to set parameters for the lower-level computer, such as the operating mode, frequency resolution, time resolution, quantization bit width, and mode selection. The higher-level computer can send configuration parameters to the lower-level computer, ensuring flexible and adjustable operating modes and parameters compared to current data acquisition and analysis systems with single operating modules and single resolutions. It can also send acquisition commands to the lower-level computer. For the lower-level computer, if it receives an acquisition command, it acquires and analyzes the spatial setting electrical signals; if it does not receive an acquisition command, it remains in a waiting state. If the lower-level computer receives a command to end acquisition, the system stops acquiring spatial setting electrical signals.

[0049] An external time and frequency system provides a clock for the acquisition and analysis system and local systems. For example, it can provide 1pps second pulses, 10MHz sine wave signals, and time information (which can also be understood as synchronization information). In possible implementations, the external clock system communicates with the acquisition and analysis system through two standard interfaces. For instance, the external clock system provides Network Time Protocol (NTP) network time synchronization services to the host computer via a local area network, thus achieving time synchronization with the host computer. The external clock system can also provide a serial port B-code time synchronization information for time synchronization of the acquisition and analysis system. Depending on the operational requirements of radio astronomy observations, the external clock system may include a GNSS-driven oven-controlled crystal oscillator clock (with an NTP service port), a GNSS-driven oven-controlled crystal oscillator rubidium atomic clock, or a VLBI astronomical observation time unification signal output device at the observation site, which is more accurate.

[0050] Please see Figure 2 This is a schematic diagram of the data acquisition and analysis system. The system includes a host computer and a slave computer. The host computer primarily configures the parameters of the slave computer and performs data acquisition, storage, and display functions. In frequency domain acquisition mode, it simultaneously displays the waterfall plot and energy spectrum diagram corresponding to the spectrum data in real time while storing the spectrum data in a disk array. In time domain acquisition mode, it simultaneously displays the waveform diagram corresponding to the time domain data in real time while storing the time domain data in a disk array. The slave computer primarily performs digital acquisition and analysis functions, converting the analog signals received by the RF front-end into digital signals. In frequency domain acquisition mode, after performing spectrum analysis according to the parameter commands issued by the host computer, the processed data is framed and transmitted to the host computer via the PCIe interface. In time domain acquisition mode, the sampled digital signals are framed and uploaded to the host computer via the PCIe interface. In both modes, the slave computer adds a high-precision timestamp to the data; the timestamp information is included in the frame header information of each frame.

[0051] The lower-level machine can be implemented using an FPGA board and may include a time base management module, trigger decision module, acquisition and control module, analog-to-digital conversion, analog-to-digital (AD) configuration and data processing module, spectrum calculation module, spectrum integration module, time-frequency domain data framing module, large-capacity buffer, data upload control module, PCIe controller, and central control module. After the system powers on, the time base module automatically selects the time base and begins operation based on the presence or absence of an external timecode and a 1pps pulse signal. The central control module parses the parameters sent by the upper-level machine and distributes them to other modules. When the lower-level machine receives an immediate start acquisition command, the system begins operation. When a mixed start acquisition command is received, the system switches modes. If the current task is in frequency domain mode, the acquisition control module timestamps the data, performs spectrum calculation and spectrum integration on the eight data channels respectively, and after the data is framed, it is sent to the large-capacity buffer and uploaded to the upper-level machine via PCIe. If the current task is in time domain mode, the acquisition control module selects the channel, truncates the data bit width, and timestamps the data. After the data is spliced ​​into frames, it is sent to a large-capacity buffer and uploaded to the host computer via PCIe.

[0052] Specifically, the analog-to-digital conversion module hardware is an ADC board, which communicates with the FPGA board via an FMC interface. The ADC module primarily performs the sampling, quantization, and encoding of analog signals into digital signals. This ADC board mainly uses a clock chip and a sampling chip to sample the signal. Both the clock chip and the sampling chip can be configured by the FPGA, outputting clock and AD signals to the FPGA board. The clock chip can automatically select a higher-priority clock source based on priority.

[0053] The AD configuration module can be used to configure the clock chip in the AD board, enabling it to output a fixed-frequency clock. It can also configure the sampling chip in the AD board, causing it to sample according to the clock provided by the clock chip. This module performs differential-to-single-ended conversion on the received AD data and clock data, outputting data with a fixed quantization width and synchronizing the data with the clock.

[0054] The time base management module is used to automatically detect the external time code (B code). If the time code (B code) is present, the time base management module outputs a valid B code flag and decodes the B code. If the time code (B code) is absent, the time base management module outputs an invalid B code flag. When the B code is valid, the time base management module uses the time code (B code) as the time reference and performs timing based on the 1pps pulse provided by the external atomic clock and the system clock. When the B code is invalid, the time base management module uses the system time sent by the host computer as the time reference. The time base management module in this embodiment can achieve a time accuracy of sub-millisecond level.

[0055] The trigger decision module can determine and output start / end acquisition commands based on the start / end acquisition commands and start / end acquisition times sent by the central control module, combined with the real-time timecode output by the clock management module and a 1pps pulse. The trigger decision module can also determine and output system subtask start / end acquisition commands based on the subtask start / end acquisition commands and start / end acquisition times sent by the central control module, combined with the real-time timecode output by the clock management module and a 1pps pulse.

[0056] The acquisition and control module can be used to start or stop acquiring space radio signals according to the system's start / stop acquisition commands. It can also be used for channel and mode selection. Furthermore, the acquisition and control module can generate frame header information based on the acquired space radio signals.

[0057] The central control module can be used to realize information (such as instructions and feedback instructions) interaction between the host computer and the slave computer, and to parse the instructions sent down from the host computer. For example, the central control module can send trigger parameters to the trigger judgment module and time parameters to the time base management module. The central control module can also send time domain channel selection parameters to the acquisition and control module, the number of FFT transform points to the spectrum calculation module, and the integration count parameters to the spectrum integration module.

[0058] The acquisition and analysis system provided in this application embodiment can provide both frequency domain acquisition and time domain acquisition. Alternatively, it can be considered that the acquisition and analysis system provided in this application embodiment offers two working modes: a time domain acquisition mode and a frequency domain acquisition mode. These two working modes can be seamlessly switched. Specifically, various working mechanisms can be configured. Table 1 shows the working mechanisms of the host computer and the slave computer.

[0059] Table 1

[0060]

[0061]

[0062] As shown in Table 1, "Immediate Work" means executing tasks immediately according to the current working parameters, which can be either time-domain or frequency-domain acquisition tasks. "Working According to a Preset Plan" means executing tasks according to a preset working mode. For example, if the preset plan is to perform time-domain acquisition first, followed by frequency-domain acquisition, then the time-domain acquisition task will be executed first, followed by the frequency-domain acquisition task. "Mixed Work" means the system starts working immediately, then interrupts the current main working state according to the pre-set task start / end time list, enters a sub-state to execute the planned task, and returns to the current main working state after the task is completed. "Event-Triggered Work" means that when an event occurs, the current working state is interrupted, and the system returns to the current working state after the event ends.

[0063] The following is combined Figure 2 Table 1 describes frequency domain acquisition and time domain acquisition respectively.

[0064] Please see Figure 5 and Figure 6 This is a schematic diagram of the frequency calculation module and the spectrum integration module. The spectrum calculation module mainly performs Fourier transform (FFT) on the AD data output from the acquisition and control module and calculates the spectral amplitude of the signal. The spectrum integration module is used to adjust the system's time resolution and signal observability by setting the integration time. It should be understood that spectrum integration is to calculate the average value of N spectrum segments (that is, to calculate the average value of the spectrum accumulated in the frequency domain), thereby achieving time resolution adjustment (details explained below). The frequency analysis module sends the spectrum data to the frequency domain data framing module.

[0065] The time-domain data framing module can be used to assemble the time-domain data output by the acquisition and control module into frames according to the storage format and transmit them to a large-capacity buffer. The large-capacity buffer, referred to as the first buffer in this document, is a buffer with a capacity exceeding a first threshold. The large-capacity buffer can be used to temporarily cache time-frequency domain data during time-frequency domain switching, uploading the current mode data only after the previous mode data upload is complete. The data upload control module can select either time-domain or frequency-domain data to upload to the host computer based on the current operating status and control the reading of data from the large-capacity buffer. This embodiment of the application can solve the problem of configuration information spanning from the PICe clock domain to the system master clock domain through multi-level caching.

[0066] This application embodiment allows for flexible adjustment of frequency resolution. For example, the frequency resolution is adjustable in 5 levels, with the highest frequency resolution being less than 6kHz; the time resolution is adjustable in 7 levels, with the highest time resolution being 1ms. Users can select the frequency and time resolution parameters through a host computer interface, which then configures these parameters to the slave computer via the PCIe interface. The slave computer performs spectrum calculation and spectrum integration. The spectrum calculation module performs FFT on the acquired data and calculates the spectral amplitude. The spectrum integration module performs integration processing on the spectrum data based on the time resolution parameters, and then transmits the spectrum data to the host computer via PCIe for display and storage.

[0067] Specifically, to ensure adjustable frequency resolution, the spectrum calculation module uses the online programmable mode of the FFT IP core. The frequency resolution df issued by the host computer and the number of transform points n required by the FFT IP core have the following relationship: Where fs is the system sampling rate, and the maximum number of transform points is set to 32768. Meanwhile, to ensure sufficiently high accuracy, the full-precision mode of the FFT IP core is used. In full-precision mode, the input bit width of the FFT IP core is: w o =w i +log2(n)+1, where w o w is the output bit width of the FFT IP core i This represents the bit width of the sampled signal.

[0068] Spectrum calculation module: State machine such as Figure 7 As shown. Upon system reset, it enters the IDLE state. When valid input FFT configuration data is detected, the state transitions to the configuration state. CFG, the configuration state, sends externally input FFT configuration data to the FFT IP core. Simultaneously, according to the AXI protocol, the FFT IP core is configured to indicate that configuration data preparation is complete. CFGOK, the configuration complete state, waits for a successful configuration feedback signal from the FFT IP core. If configuration completion is detected, FFT IP core configuration stops, and the state transitions to the FFT start state; conversely, if configuration incomplete is detected, it remains in this state, continuing to detect and send configuration data. FFT, the FFT calculation state, continuously checks the validity of input data. If the input data is valid, the 14-bit input data is expanded to the required 32 bits for the FFT IP core and input into the FFT IP core. The valid input bits of the FFT IP core are then reset to start FFT calculation. If the input data is invalid, reset the valid bits of the input data in the FFT IP core to pause the FFT calculation.

[0069] To achieve adjustable time resolution, from a data processing perspective, this involves calculating the average value of N frequency spectrum segments, thereby adjusting the time resolution. At this point, the time resolution dt satisfies: dt = N * n * T s T s Let dt be the period of the system clock. According to the technical specifications, the minimum time resolution is 1ms. Therefore, when the number of transformation points is determined, the time resolution dt and N have a one-to-one correspondence.

[0070] Spectrum Integrator Module: The spectrum integrator module is used to adjust the system's time resolution and signal observability. The system's time resolution is adjusted by setting the integration time. The spectrum integrator module mainly consists of a FIFO IP core; please refer to [link to relevant documentation]. Figure 6 This is a flowchart illustrating the workflow of the spectrum integration module. The implementation of the spectrum integration module is accomplished jointly by the FFT IP core and the state machine. The state machine is written as follows: Figure 8 As shown, the read state machine is as follows Figure 9 As shown. For the write state machine, the state first transitions to the Idle state (Idle_state). In Idle_state, all signals are initialized, and the state transitions to Write_state1. In Write_state1, when the half-frame data valid flag f_half_fft is high and the data is valid, the FIFO write valid bit is high, and the data is written to the FIFO; when the last data flag is high, the state transitions to Write_state2, otherwise it remains in Write_state1. In Write_state2, when the half-frame data valid flag f_half_fft is high, the FIFO write valid bit is high, and the original data plus the data read from the FIFO is written to the FIFO; when the frame count within the DMA block equals the average of N segments and the last data flag is high, the state transitions to Write_state1, otherwise it remains in Write_state2.

[0071] For the read state machine, the state first transitions to the Idle state (Idle_state). In Idle_state, all signals are initialized, and the state transitions to read_state1. In read_state1, the read validity flag is pulled low. When the last data flag is pulled high, the state transitions to read_state2. In read_state2, when the half-frame data validity flag f_half_fft is high and the data is valid, the FIFO read validity bit is pulled high, and the data is read from the FIFO. When the frame count within the DMA block equals the average of N segments and the last data bit is pulled high, the state transitions to read_state3; otherwise, it remains in read_state2. In read_state3, when the FIFO is not empty, the read validity flag is pulled high, and the data is read from the FIFO and shifted for output. When the intra-frame sampling point count equals half the FFT point count, the state transitions to read_state1.

[0072] According to the spectrum analysis module in the embodiments of this application, the integral parameters in the frequency domain acquisition mode can be obtained as shown in Table 2.

[0073] Table 2 Integral parameters in frequency domain mode

[0074]

[0075]

[0076] The embodiments of this application can also achieve flexible switching between time-domain acquisition mode and frequency-domain acquisition mode, while ensuring data continuity. For example, please refer to... Figure 10 This is a block diagram illustrating the switching principle between time-domain and frequency-domain acquisition modes provided in this application embodiment. The main function of the spectrum calculation unit is to convert time-domain signals into frequency-domain signals. When switching from frequency-domain to time-domain acquisition mode, the spectrum calculation unit requires a certain time delay. A large-capacity buffer is used as a time-domain data buffer to ensure that data is not lost. In other words, when the host computer sends time-frequency domain parameters, the slave computer does not switch immediately upon receiving the mode switching command. The mode switch is performed only after ensuring that a frame of data has ended and a DMA block is full.

[0077] Specifically, in this embodiment, the system's operating state can be divided into a main operating state, a sub-operating state, and an event-triggered state. The main operating state is the operating state when the system first starts up, in either time-domain or frequency-domain acquisition mode. The sub-operating state is the operating state when the system switches to the next mode during operation. The event-triggered state is the state when the host computer determines the switch between time-domain and frequency-domain acquisition modes during system operation. The acquisition and control module mainly sends data into the time-domain / frequency-domain channel according to control commands in the corresponding operating state, serving as the main module for achieving seamless time-frequency domain switching. This module mainly consists of a main state machine and a sub-state machine. The main state machine mainly performs state transitions under main tasks, sub-tasks, and event-triggered tasks. The sub-state machine mainly performs time-frequency domain state transitions under the three modes. For example, please refer to... Figure 11 This is a schematic diagram of the timing mechanism for switching the time-frequency domain module provided in an embodiment of this application. The acquisition mode selection main state machine is as follows: Figure 12 As shown, the sub-state machine for selecting the acquisition mode is as follows: Figure 13 As shown.

[0078] The main state machine includes wait_state, main_state, sub_state, event_state, and wait_state. Upon system reset, it enters wait_state. In wait_state, when an event start / end flag is detected, the state transitions to the event-triggered state. When a main task start / end flag is detected, the state transitions to the main task state. In main_state, when counter 1 equals the DMA1 size (cnt1 = DMA_data1), the state trigger flags are reset. For example, setting the event trigger flag high (event_start_work = 1) transitions the state to the event-triggered state; setting the subtask flag high transitions the state to the subtask state; and setting the main task flag low transitions the state to the wait state. Otherwise, the state transitions to the current state. In the `sub_state`, when counter 2 equals the size of DMA2 (cnt1 = DMA_data2): the event trigger flag is high (event_start_work = 1), and the state transitions to the event trigger state; when the subtask flag is low (son_start_work = 0), the state transitions to the main task state. Otherwise, the state returns to the current state. In the `event_state`, when counter 3 equals the size of DMA3 (cnt1 = DMA_data3): the event trigger flag is low (event_start_work = 0), and the state transitions to the main task state. Otherwise, the state returns to the current state.

[0079] The sub-state machine includes `wait_state` (waiting state), `frq_state` (frequency domain state), and `time_state` (time domain state). In `wait_state`, for example, in the main task, event-triggered, and sub-task states, the time-frequency domain selection parameter is checked. When the time-frequency domain selection parameter is high (`time_freq_select = 1`), the state transitions to the time domain state; when the time-frequency domain selection parameter is low (`time_freq_select = 0`), the state transitions to the frequency domain state. In `frq_state`, when the counter equals the DMA count, the counter equals 0; otherwise, the counter increments by one. Simultaneously, according to the channel parameters, 8 channels of AD data are output to the frequency domain port, and the frequency domain data validity flag is set high. In `time_state`, when the counter equals the DMA count, the counter equals 0; otherwise, the counter increments by one. Simultaneously, according to the channel parameters, 8 channels of AD data are output to the frequency domain port, and the time domain data validity flag is set high.

[0080] The data upload control module works in conjunction with the acquisition and control unit to complete the time-frequency domain switching function. This module mainly uses a state machine to perform the time-frequency domain switching, such as... Figure 14 As shown. In Idle_state, all signals are initialized, and the state transitions to Wite_state. In Wite_state, when the frequency domain enable is pulled high, the state transitions to Freq_state; otherwise, it transitions to Time_state. In Time_state, when the DDR FIFO in the bulk buffer is not empty, the FIFO data read enable is pulled high; when the data validity flag is pulled high, time domain data is sent to the output port, and the data validity flag is pulled high; when the frequency domain enable is pulled high, the state transitions to Freq_state; otherwise, it transitions to Time_state.

[0081] A large-capacity cache can be implemented using Double Data Rate (DDR) synchronous dynamic random access memory. This module mainly consists of data input control, FIFO1, DDR read / write control, FIFO2, and data output control, such as... Figure 22As shown. When the system starts acquiring data, the data flows into the DDR controller and first passes through FIFO1. If FIFO1 is not full, a 512-bit wide data is written into the DDR (DDR's write bit width is 512 bits), and the DDR counter is incremented by 1. The DDR write completion signal goes high, indicating that data already exists in the DDR. After the DDR write completion signal goes high, a 512-bit wide data is read into FIFO2. At the same time, the DDR counter is decremented by 1. After the read is complete, the DDR read completion signal goes high. At this time, the DDR controller returns to 1 and starts writing data into the DDR again. The data output from FIFO2 is sent to the data return control module; the return control module is responsible for sending the data to the PCIe controller and uploading it to the host computer. If the host computer does not remove the data in time, the PCIe controller of the lower computer will stop sending data, which will cause FIFO2 to fill up, and the FIFO2 full signal goes high. The DDR controller stops reading data from the DDR, and the DDR read completion signal goes low; subsequent data is stored in the DDR. This continues until the DDR is full. If the DDR is not full, the PCIe data link will be restored, and the PCIe controller can send data; then FIFO2 will continuously read data to the PCIe control module. Once the DDR is full, the full signal of FIFO1 will go high. At this time, the lower-level device will drop data in units of data frame size until the full signal of FIFO1 goes low, meaning the DDR can be written to again. During time-frequency domain switching, for example, switching from the time domain to the frequency domain, the switching flag is set, indicating that there will be no further time-domain data input to FIFO1. If there is data in the DDR and the corresponding two FIFOs, then data will continue to be read until the DDR and both FIFOs are empty. Then, the time-frequency domain switching signal is sent to the data return module. The same logic applies to switching from the frequency domain to the time domain.

[0082] Based on the foregoing Figure 1 and Figure 2 The present application also provides a corresponding method for acquiring and analyzing space radio signals, based on the structure shown. Please refer to [link to relevant documentation]. Figure 15 This is a flowchart illustrating the method for acquiring and analyzing radio signals in this space.

[0083] S1501, The lower-level machine receives the configuration parameters sent by the upper-level machine. The configuration parameters include a first time resolution, a first frequency resolution, and a first acquisition mode. The first time resolution is one of multiple preset time resolutions, the first frequency resolution is one of multiple preset frequency resolutions, and the first acquisition mode is a time domain acquisition mode or a frequency domain acquisition mode.

[0084] In this embodiment, multiple time resolutions and multiple frequency resolutions are supported, allowing the host computer to set the resolution to the slave computer according to actual requirements when acquiring space radio signals. For example, a first time resolution can be selected from multiple time resolutions, and a first frequency resolution can be selected from multiple frequency resolutions, thus flexibly adjusting the time and frequency resolutions to better meet the application needs of radio observation. This embodiment also allows the host computer to configure the acquisition mode, such as a time-domain acquisition mode or a frequency-domain acquisition mode. It should be understood that frequency-domain acquired data has high real-time observability, but due to the limitations of system frequency and time resolution, the amount of information carried by the data is limited; time-domain acquired data can carry a large amount of information, but its real-time observability is lower. Compared to traditional single acquisition modes, this embodiment supports both time-domain and frequency-domain acquisition modes. That is, this embodiment supports acquiring both time-domain and frequency-domain data, thus allowing the acquisition mode to be set according to the application needs of radio observation, ensuring seamless switching without data loss during time-frequency domain switching. It enables observers to switch to time domain mode in real time when they observe burst signals in frequency domain mode to collect raw data at key times, facilitating effective analysis of subsequent data.

[0085] S1502, The lower-level machine receives the start acquisition command sent by the upper-level machine. This start acquisition command is used to indicate the acquisition of space radio signals.

[0086] When it is necessary to acquire space radio signals, a start acquisition command can be sent from the host computer to the slave computer, instructing the slave computer to acquire space radio signals. Similarly, when it is not necessary to acquire space radio signals, a stop acquisition command can be sent from the host computer to the slave computer, instructing the slave computer to stop acquiring space radio signals. In possible implementations, the start acquisition command can carry the start acquisition time, and the stop acquisition command can carry the end acquisition time. Of course, the start acquisition time and the end acquisition time can also be sent to the slave computer separately.

[0087] S1503, the lower-level machine collects space radio signals according to the configuration parameters.

[0088] Once the lower-level machine receives the start acquisition command, it can acquire space radio signals according to the configured parameters. For example, if the configured acquisition mode is time-domain acquisition mode, then time-domain data can be acquired. If the configured acquisition mode is frequency-domain acquisition mode, then frequency-domain data can be acquired.

[0089] Because this application embodiment supports both time-domain and frequency-domain acquisition modes, in possible scenarios, the host computer can switch between these modes. For example, the host computer can send a mode switching command to the slave computer, which instructs the switching of acquisition modes. This mode switching command can be a periodically sent command from the host computer or triggered by a specific event. It should be understood that once the specific event ceases to occur, the slave computer reverts from the current acquisition mode to the acquisition mode before the switch. That is, the mode switching command can be a predefined periodically triggered command or a predefined specific event triggered. For example, a specific event might include a counter value being the same as the size of the Direct Memory Access (DMA) block corresponding to the current acquisition mode. In this application embodiment, the slave computer switches the acquisition mode after determining that a frame of data has ended and the DMA block corresponding to the current acquisition mode is full. In other words, the slave computer does not immediately switch the acquisition mode upon receiving the mode switching command, but waits until a frame of data has ended and the DMA block corresponding to the current acquisition mode is full before performing the mode switch. This allows for flexible switching between the two acquisition modes while ensuring the continuity of the acquired data. It should be noted that the time-domain acquisition mode corresponds to one DMA, and the frequency-domain acquisition mode corresponds to one DMA. For specific switching timing details, please refer to the aforementioned content; they will not be repeated here.

[0090] This application's embodiments support adaptive selection of both external and internal clock input modes to ensure normal system operation as much as possible. For example, the host computer and slave computer are connected to an external time and frequency system. This external time and frequency system provides network time to the host computer via the Network Time Protocol (NTP), and also provides serial port B-code time to the slave computer. For instance, a GNSS-disciplined rubidium atomic clock outputs B-code time as a time reference, synchronized with BeiDou satellite timekeeping. When the time B-code is invalid, the slave computer uses the system time sent by the host computer as its reference time.

[0091] In addition, the embodiments of this application can adaptively select the clock source, that is, adaptively select an external clock of the same source or an internal clock, ensuring that the system uses the rubidium atomic clock time when the GNSS disciplined rubidium atomic clock output clock is valid, and uses the system time when the GNSS disciplined rubidium atomic clock has no output.

[0092] For example, see Figure 16This is a block diagram illustrating the principle of adaptive clock source selection provided in this application embodiment. The adaptive clock source selection mainly includes atomic clock operating status identification and real-time time error correction. The atomic clock operating status identification module can be used to determine whether BeiDou satellite time synchronization is valid. When BeiDou satellite time synchronization is valid, for example, if a B code exists, a valid B code flag is output, and the B code is decoded to generate the system's time reference. If there is no B code signal, an invalid B code flag is output, and the computer's network time is used as the time reference. The real-time time error correction module can be used for time calibration based on 1PPS pulses provided by an external atomic clock. For example, when the B code signal is valid, BeiDou time is used as the time reference, and time calibration and system clock timing are performed based on the 1PPS pulses provided by the external atomic clock. When the B code is invalid, the system time sent by the host computer is used as the time reference. The real-time time error correction module can achieve sub-millisecond time accuracy.

[0093] Specifically, please see Figure 17 This is a schematic diagram of the adaptive clock source selection process provided in this application embodiment. The process includes: the atomic clock operating state discrimination module automatically detects the externally input IRIG-B. When a signal frame header is detected, it considers the atomic clock operating state and the B-code signal to be normal, and outputs a valid B-code signal. Then, the B-code data is automatically decoded. The B-code is divided into two types: B(DC) code and B(AC) code, where DC is a digital signal and AC is an analog modulated sine wave signal. This application embodiment mainly uses B(DC) code, such as... Figure 21 This is a schematic diagram of B-code symbols provided in an embodiment of this application. Corresponding to... Figure 21 Please see Figure 22 This is a schematic diagram of the B-code encoding format.

[0094] The B-code signal is a serial signal. Each frame of the B-code signal consists of two consecutive P-codes in its header. During pulse width modulation (PWM), if two consecutive P-codes are detected, the input signal is determined to be a valid B-code signal, the `irigb_valid` signal goes high, and the module enters the next state. Otherwise, it returns to the idle state. Because the B-code signal (DC code) is pulse width modulation, a counter starts counting when the signal is high and stops counting when the signal is low, and the counter value is matched. Considering that the B-code may be distorted due to interference during transmission, this embodiment incorporates redundancy when matching the counter value. For example, the matching method is as follows: if the high-level width of the counted code is 7-8 ms, it is determined to be a P-code; if the counted code width is 1-3 ms, it is determined to be a 0-code; if the counted code width is 4-6 ms, it is determined to be a 1-code. The B-code signal can then be decoded. Specifically, pulse width modulation can be performed on each code, and the result can be stored in the `tcode` register. Since a frame of B-code data consists of 100 symbols, including 11 P-code symbols and the rest are time data symbols, a counter is used to count each non-P-code time data symbol. When the counter reaches 89, it indicates the end of a frame of B-code data, and the start_gen signal goes high for one clock cycle, indicating that the tcode data is sent to the time generation module in the real-time time error correction module. After that, the atomic clock operating state discrimination module returns to the idle state, waiting for the next frame of B-code signal to arrive.

[0095] For example, see Figure 20 This is a schematic diagram of the working state machine of the atomic clock working state discrimination module provided in the embodiments of this application.

[0096] In the idle state (IDLE state), all registers are reset. When a high level is detected in the irigb signal (irigb = 1), the system enters the P0H state (the state for receiving a high level P0 symbol). In the P0H state, it checks whether a high level P0 symbol has been correctly received. A counter (high_count++) is performed during the high level of the irigb signal; when a low level of the irigb signal arrives (irigb = 0), if the counter value is between 7ms and 8ms, the currently received signal is considered a high level P0 symbol, and the state transitions to the P0L state (the state for receiving a low level P0 symbol). Otherwise, the currently received P0 symbol is considered incorrect, and the state transitions to the IDLE state.

[0097] In the P0L state, it is determined whether a low level of the P0 symbol has been correctly received. A counter (low_count++) is performed while the irigb signal is low. When a high level of the irigb signal arrives, if the counter value is between 1ms and 3ms, the received signal is considered to be a low level of the P0 symbol, and the state transitions to the PRH state (receiving a high level of the Pr symbol). Otherwise, the received P0 symbol is considered incorrect, and the state transitions to the ERROR state (B code reception error state). In the ERROR state, it indicates that the B code has not been correctly received; the B code valid signal irigb_valid will be pulled low, and the state will transition to the IDLE state.

[0098] In the PRH state, it is determined whether a high level of the PR symbol has been received. Counting is performed during the high level of the irigb signal; when the irigb signal goes low, if the counter value is between 7ms and 8ms, the currently received signal is considered to be a high level of the PR symbol, and the state transitions to the PRL state (the state of receiving a low level of the Pr symbol). Otherwise, the currently received PR symbol is considered incorrect, and the state transitions to the ERROR state. In the PRL state, it is determined whether a low level of the Pr symbol has been received. Counting is performed during the low level of the irigb signal; when the irigb signal goes high, if the counter value is between 1ms and 3ms, the currently received low level of the Pr symbol is considered correct. At this time, it is considered that the system has correctly received both the P0 and Pr symbols, and the current B code signal is considered normal. The B code valid signal irigb_valid will be pulled high, and the state transitions to the BH state (the state of receiving a high level of the B code symbol). Otherwise, the currently received Pr symbol is considered incorrect, and the state transitions to the ERROR state.

[0099] In the BH state, the high levels of the irigb signal are counted. When a low level of the irigb signal arrives, the state transitions to the BL state (the state of receiving a low level of a B code symbol). In the BL state, the low levels of the irigb signal are counted. When a high level of the irigb signal arrives (irigb_valid = 1), it indicates that one B code symbol has been received, and the state transitions to the DECODE state (decoding state).

[0100] In the DECODE state, decoding is performed based on the duration of the high and low levels of the B code symbols. If the high-level width of the counted symbol is 7-8 ms, it is determined to be a P code; if the counted symbol width is 1-3 ms, it is determined to be a 0 code; if the counted symbol width is 4-6 ms, it is determined to be a 1 code. The tcode register is used to store the decoded data; rcv_ptr is a pointer to the B code data symbols, indicating which symbol is currently being decoded. If a 0 or 1 symbol is determined, the corresponding bit in the B code time code register tcode is assigned a value of 0 or 1, and rcv_ptr is incremented by 1. If a P code is received, rcv_ptr remains unchanged, and the value of tcode is not changed. If rcv_ptr equals 88 (the number of data symbols in the B code), then when the high level arrives, it will jump to the TIMEOUT state (output time code state); otherwise, it will jump to the BH state to receive the next B code symbol.

[0101] In the TIMEOUT state, the Beijing time is calculated from the B-code data. The calculated Beijing time will be sent as an external time reference to the sub-millisecond time information generation and real-time error correction module. Afterwards, if the irigb signal is detected to be low, the state transitions to the IDLE state; otherwise, it transitions to the P0H state for the next reception.

[0102] The decoded Beijing time will be sent as an external time reference to correct the time error in real time when the next 1PPS pulse arrives. For details, please refer to [link to relevant documentation]. Figure 21 This is a schematic diagram illustrating the workflow of the real-time time error correction module provided in this application embodiment. The process includes: the real-time time error correction module detecting a valid time reference signal. If the module detects that an external time reference is valid before an internal time reference, it uses the external time as the time reference; otherwise, it uses the internal time. After selecting a time reference, timing begins. During timing, if the real-time time error correction module detects a rising edge of the 1PPS signal, time calibration is performed. Detection of the 1PPS rising edge and the trigger signal rising edge is achieved by detecting the pulse level. It should be understood that, based on the phase relationship between 1PPS, the trigger signal, and the 10kHz timing clock, this will result in a one-clock delay, requiring compensation for the counter when the 1PPS rising edge arrives. For example, if no 1PPS rising edge is detected, sub-millisecond counting is performed based on the current time base. When the sub-millisecond counter reaches 9999, the second counter increments by 1. If a 1PPS rising edge is detected, time calibration is performed. The specific operation is as follows: if the value of the sub-millisecond counter is greater than 5000, it is considered that the system clock is slower than the ideal clock, so the sub-millisecond counter is cleared and the second increments by 1; otherwise, it is considered that the system clock is faster than the ideal clock, so the sub-millisecond counter is cleared and the second increments by 1.

[0103] It should be understood that the aforementioned embodiments of the space radio signal acquisition and analysis device can all be used in subsequent embodiments, and repeated content will not be described again.

[0104] This application also provides a computer-readable storage medium including instructions that, when run on a computer, cause the computer to perform the methods described in the above method examples. For details, please refer to the detailed description in the method examples, which will not be repeated here.

[0105] In the embodiments of this application, the term "multiple" refers to two or more. The term "and / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. In addition, the character " / ", unless otherwise specified, generally indicates that the related objects before and after it are in an "or" relationship.

[0106] "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0107] Furthermore, unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority, or importance of multiple objects. For example, the first Nyquist zone and the second Nyquist zone can be the same Nyquist zone or different Nyquist zones, and such names do not indicate a difference in priority or importance between the two deployment environments.

[0108] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0109] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0110] The steps of the methods or algorithms described in the embodiments of this application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC.

[0111] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0112] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0113] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0114] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0116] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method of collecting and analyzing a spatial radio signal, characterized by, The application is applied to a collection and analysis system of space radio signals, the collection and analysis system comprises an upper computer and a lower computer, and the method comprises the following steps: The lower computer receives configuration parameters sent by the upper computer, the configuration parameters comprising a first time resolution, a first frequency resolution, and a first collection mode, wherein the first time resolution belongs to a plurality of preset time resolutions, the first frequency resolution belongs to a plurality of preset frequency resolutions, and the first collection mode belongs to a time domain collection mode and a frequency domain collection mode; The lower computer receives a start collection instruction sent by the upper computer, and the start collection instruction is used to instruct to collect space radio signals; The lower computer collects the space radio signals according to the configuration parameters; The lower computer is provided with an anti-aliasing filter in an analog input front end, and the method further comprises the following steps: The lower computer respectively samples a plurality of sub-bands of frequency channelization through the anti-aliasing filter; The lower computer respectively folds signals output by the plurality of sub-bands to one Nyquist zone based on an under-sampling spectrum folding mode; The upper computer restores the spectrum to an initial frequency band according to the Nyquist zone where the plurality of sub-bands are located; The method further comprises the following steps: The upper computer respectively maps the first time resolution and the first frequency resolution into integral segments and FFT points, and the integral segments and the FFT points are stored in the form of a table; The lower computer realizes flexible configuration of parameters in a table lookup mode.

2. A method of collecting and analyzing a spatial radio signal as claimed in claim 1, characterized in that, The method further comprises the following steps: The upper computer switches the collection mode according to a trigger task, and sends configuration parameters to the lower computer, wherein the trigger task is a user-pre-set plan list task or an event trigger task; The lower computer receives the configuration parameters sent by the upper computer and switches the collection mode without losing data.

3. A method of collecting and analyzing a spatial radio signal as claimed in claim 2, characterized in that, The lower computer is currently in a working state, and the lower computer switches the collection mode without losing data, comprising the following steps: The lower computer switches the collection mode when it is determined that the current completed transmission data amount is an integer multiple of a preset transmission size, and the preset transmission size is the same as a direct memory access (DMA) size.

4. A method of collecting and analyzing a spatial radio signal as claimed in claim 2, characterized in that, The lower computer is provided with a first cache area, the capacity of the first cache area is higher than a first threshold value, the first cache area is used to cache data when a high-speed serial computer expansion bus (PCIe) transmission data is busy, and the method further comprises the following steps: The first cache area transmits next collection mode data after the current collection mode data transmission is completed when the collection mode is switched.

5. A method of collecting and analyzing a spatial radio signal as claimed in claim 1, characterized in that, The upper computer and the lower computer are connected to an external time-frequency system, the external time-frequency system provides network time for the upper computer based on a network time protocol (NTP), the external time-frequency system provides a serial B code time for the lower computer, and provides a 10MHz frequency standard signal as a clock source for signal collection.

6. A method of acquisition and analysis of a spatial radio signal as claimed in claim 5, characterized in that, The method further comprises the following steps: When the time B code provided by the external time and frequency system is invalid, the lower computer counts time based on the system time sent by the upper computer as the reference time; when the 10MHz frequency reference signal provided by the external time and frequency system is invalid, the lower computer takes the clock signal generated by the on-board crystal oscillator as the clock source, wherein the system is provided with a time stamp with a precision higher than 0.1 millisecond.

7. A method of acquisition and analysis of a spatial radio signal as claimed in claim 6, characterized in that, The method further comprises: The lower computer and the upper computer synchronize the system time with the external time and frequency system, and the synchronization comprises filtering, correction and calibration functions.

8. An apparatus for the acquisition analysis of spatial radio signals, characterized in that The device comprises a processor, a memory, a field programmable logic gate array (FPGA), and an FPGA mezzanine card (FMC); the processor is connected with the memory; the memory is used for storing a computer program; the processor is used for executing the computer program stored in the memory; the FPGA is connected with the processor through a high-speed serial computer expansion bus (PCIe); and the FMC is connected with the FPGA, so that the device realizes the method for collecting and analyzing a space radio signal according to any one of claims 1-7.

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