electronic devices

Abstract

The present invention provides an electronic device. The electronic device includes a voltage source circuit, a current source circuit, and an electronic component. The voltage source circuit, the current source circuit, and the electronic component are electrically connected to a node. The electronic device disclosed herein can implement a bidirectional bias circuit including the voltage source circuit and the current source circuit.

Description

Technical Field

[0001] The present disclosure relates to a device, and in particular, to an electronic device. Background Art

[0002] Generally speaking, a varactor antenna with a varactor diode consists of active matrix pixels biased by a voltage source circuit. The voltage source circuit is implemented using a source-follower amplifier that maintains a bias voltage and a source or sink current to compensate for the varactor diode's leakage current. Therefore, bidirectional biasing requires a complementary metal-oxide-semiconductor (CMOS) process to compensate for the reverse and forward currents of the varactor diode, which has both source and sink currents. Summary of the Invention

[0003] The electronic device disclosed herein includes a voltage source circuit, a current source circuit, and an electronic component. The voltage source circuit, the current source circuit, and the electronic component are electrically connected to a node.

[0004] Based on the above, according to the electronic device of the present disclosure, the electronic device can implement a bidirectional bias circuit including a voltage source circuit and a current source circuit.

[0005] In order to make the foregoing content more easily understood, several embodiments are described in detail below with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the embodiments, serve to explain the principles of the present disclosure.

[0007] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 2A According to the present disclosure Figure 1 A timing diagram of relevant voltages and signals of an embodiment of the present invention;

[0009] Figure 2B According to the present disclosure Figure 1 Another timing diagram of relevant voltages and signals of an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 4According to the present disclosure Figure 3 A timing diagram of relevant voltages and signals of an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 6 According to the present disclosure Figure 5 A timing diagram of the relevant voltages and signals of an embodiment.

[0014] Explanation of Figure Numbers

[0015] 100, 300, 500: electronic devices;

[0016] 110, 310, 510: voltage source circuit;

[0017] 120, 320, 520: current source circuit;

[0018] 130, 330, 530: electronic components;

[0019] BP: bias period;

[0020] BS: bias signal;

[0021] C1: capacitor;

[0022] Cst1, Cst2, CstA, CstB, CstC, CstD: storage capacitors;

[0023] DL, DL1, DL2, DL3: data lines;

[0024] dv: delta voltage;

[0025] I1: source current;

[0026] I2: sink current;

[0027] If: forward current;

[0028] Ir: reverse current;

[0029] N0, N1, N2, N3, N4, N5: nodes;

[0030] RS: reset signal;

[0031] RP: reset period;

[0032] SP: scanning period;

[0033] SP1: first scanning cycle;

[0034] SP2: second scanning cycle;

[0035] SS, SS1, SS2: scanning signal;

[0036] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13: time;

[0037] Tb, Tb1, Tb2, Tb3, TbA, TbB, TbC, TbD: bias transistors;

[0038] Tc1, Tc2: compensation transistors;

[0039] Td1, Td2: driving transistors;

[0040] Tr1, Tr2, TrA, TrB, TrC, TrD: reset transistors;

[0041] Ts1, Ts2, TsA, TsB, TsC: scanning transistors;

[0042] Vdata1, Vdata2, Vdata3: data voltage;

[0043] VDD: first operating voltage;

[0044] Vf: forward voltage;

[0045] Va, Vref1, Vref2: reference voltage;

[0046] Vrst1: first reset voltage;

[0047] Vrst2: second reset voltage;

[0048] VSS: second operating voltage;

[0049] Vth1: threshold voltage. DETAILED DESCRIPTION

[0050] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like components.

[0051] Throughout the present disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same component by different names. This document does not intend to distinguish between components that have the same function but are named differently. In the following description and claims, words such as "including" and "comprising" are open-ended terms and should be interpreted as meaning "including, but not limited to..."

[0052] The term "coupled (or electrically connected)" used throughout the entire specification (including the attached claims) of this application may refer to any direct or indirect connection method. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or certain connection methods. The terms "first", "second" and similar terms mentioned throughout the entire specification (including the attached claims) of this application are only used to name separate elements or to distinguish between different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limit of the number of elements and should not be used to limit the arrangement order of elements. In addition, where possible, the elements / components / steps with the same figure numbers in the drawings and embodiments represent the same or similar parts. The related descriptions of the elements / components / steps can be referenced to each other using the same figure numbers or using the same terms in different embodiments.

[0053] The electronic device of the present disclosure may include, for example, an antenna pixel circuit, and the electronic component may correspond to the antenna unit of one pixel of the antenna pixel. The electronic component of the present disclosure may be a voltage-controlled device, and the voltage-controlled device may include, for example, a varactor diode, a resistor, an inductor, or a capacitor. It should be noted that the electronic device of the present disclosure can be manufactured using display panel processes, and the related transistors and electronic components are manufactured on a glass substrate.

[0054] It should be noted that in the following embodiments, the technical features of several different embodiments may be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of each embodiment do not violate the spirit of the present disclosure or conflict with each other, they may be mixed and used together at will.

[0055] Figure 1 Schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1 , the electronic device 100 includes a voltage source circuit 110, a current source circuit 120, and an electronic component 130. The voltage source circuit 110, the current source circuit 120, and the electronic component 130 are electrically connected to a node N0. The voltage source circuit 110 is further electrically connected to a data line DL1. The current source circuit 120 is further electrically connected to a data line DL2. The electronic component 130 is electrically connected between the node N0 and a ground voltage (0V). In an embodiment of the present disclosure, the voltage source circuit 110 and the current source circuit 120 form a bidirectional bias circuit, and the voltage source circuit 110 and the current source circuit 120 are configured to implement forward and reverse bias for the electronic component 130. In an embodiment of the present disclosure, the voltage source circuit 110, the current source circuit 120, and the electronic component 130 may be a pixel unit of an array in a panel, and other pixel units of the array may also have the same circuit as the electronic device 100.

[0056] In an embodiment of the present disclosure, the voltage source circuit 110 includes a drive transistor Td1, a scan transistor Ts1, a compensation transistor Tc1, a bias transistor Tb1, a reset transistor Tr1, and a storage capacitor Cst1. A first terminal of the scan transistor Ts1 is electrically connected to a data line DL1. A second terminal of the scan transistor Ts1 is electrically connected to a node N1. A control terminal of the scan transistor Ts1 receives a scan signal SS. A first terminal of the bias transistor Tb1 is electrically connected to a first operating voltage VDD. A control terminal of the bias transistor Tb1 receives a bias signal BS. A first terminal of the drive transistor Td1 is electrically connected to a second terminal of the bias transistor Tb1. A second terminal of the drive transistor Td1 is electrically connected to a second terminal of the scan transistor Ts1 via a node N1, and the second terminal of the drive transistor Td1 is further electrically connected to the electronic component 130 via a node N0. Node N1 is electrically connected to a node N0. A control terminal of the drive transistor Td1 is electrically connected to a node N2. A first terminal of the compensation transistor Tc1 is electrically connected to a control terminal of the drive transistor Td1 via a node N2. A second terminal of the compensation transistor Tc1 is electrically connected to a first terminal of the drive transistor Td1. A control terminal of the compensation transistor Tc1 receives a scan signal SS. A first terminal of the reset transistor Tr1 is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor Tr1 is electrically connected to the first terminal of the compensation transistor Tc1 and the control terminal of the drive transistor Td1 via a node N2. The control terminal of the reset transistor Tr1 receives a reset signal RS. A first terminal of the storage capacitor Cst1 is electrically connected to the control terminal of the drive transistor Td1 via a node N2. A second terminal of the storage capacitor Cst1 is electrically connected to a reference voltage Vref1.

[0057] In an embodiment of the present disclosure, the driving transistor Td1, the scanning transistor Ts1, the compensation transistor Tc1, the bias transistor Tb1, and the reset transistor Tr1 are N-type transistors, such as N-type metal oxide semiconductors (NMOS). In other embodiments of the present disclosure, the driving transistor Td1 or other transistors may be P-type transistors, such as P-type metal oxide semiconductors (PMOS).

[0058] In an embodiment of the present disclosure, the current source circuit 120 includes a drive transistor Td2, a scan transistor Ts2, a compensation transistor Tc2, a bias transistor Tb2, a bias transistor Tb3, a reset transistor Tr2, and a storage capacitor Cst2. A first terminal of the scan transistor Ts2 is electrically connected to the data line DL2. A second terminal of the scan transistor Ts2 is electrically connected to a node N3. A control terminal of the scan transistor Ts2 receives a scan signal SS. A first terminal of the bias transistor Tb2 is electrically connected to the electronic component 130 via a node N0. A control terminal of the bias transistor Tb2 receives a bias signal BS. A first terminal of the drive transistor Td2 is electrically connected to a second terminal of the bias transistor Tb2. A second terminal of the drive transistor Td2 is electrically connected to a second terminal of the scan transistor Ts2 via a node N3. A control terminal of the drive transistor Td2 is electrically connected to a node N4. A first terminal of the compensation transistor Tc2 is electrically connected to a control terminal of the drive transistor Td2 via a node N4. A second terminal of the compensation transistor Tc2 is electrically connected to a first terminal of the drive transistor Td2. A control terminal of the compensation transistor Tc2 receives a scan signal SS. A first terminal of the reset transistor Tr2 is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor Tr2 is electrically connected to a first terminal of the compensation transistor Tc2 and a control terminal of the drive transistor Td2 via a node N4. The control terminal of the reset transistor Tr2 receives a reset signal RS. A first terminal of the storage capacitor Cst2 is electrically connected to a control terminal of the drive transistor Td2 via a node N4. A second terminal of the storage capacitor Cst2 is electrically connected to a reference voltage Vref2. A first terminal of the bias transistor Tb3 is electrically connected to a second terminal of the drive transistor Td2 and a second terminal of the scan transistor Ts2. A second terminal of the bias transistor Tb3 is electrically connected to a second operating voltage VSS. The control terminal of the bias transistor Tb3 is electrically connected to a bias signal BS. The first operating voltage VDD may be higher than the second operating voltage VSS, and the second operating voltage VSS may be lower than a ground voltage (0V). In an embodiment of the present disclosure, the electronic component 130 may receive a third operating voltage via a node N0, and the third operating voltage is between the first operating voltage VDD and the second operating voltage VSS.

[0059] In the embodiment of the present disclosure, the driving transistor Td2, the scanning transistor Ts2, the compensation transistor Tc2, the bias transistor Tb2, the bias transistor Tb3 and the reset transistor Tr2 are N-type transistors. In other embodiments of the present disclosure, the driving transistor Td2 or other transistors may be P-type transistors.

[0060] In an embodiment of the present disclosure, the voltage source circuit 110 and the current source circuit 120 receive the same scan signal SS.

[0061] Figure 2A According to the present disclosure Figure 1 The relevant voltage and signal timing diagram of the embodiment. Figure 1 and Figure 2A , the electronic device 100 can operate during the bias period BP, the reset period RP, and the scan period SP. In an embodiment of the present disclosure, during the scan period SP from time t5 to time t7, the data line DL1 can provide a data signal having a data voltage Vdata1 to the voltage source circuit 110, and the data line DL2 can provide a data signal having a data voltage Vdata2 to the current source circuit 120. In an embodiment of the present disclosure, an external control device can control the voltage source circuit 110 and the current source circuit 120 by adjusting the data voltage Vdata1 and the data voltage Vdata2 to operate the electronic component 130.

[0062] During the reset period RP from time t2 to time t4, the reset signal RS may be at a high voltage level, and the bias signal BS and the scan signal SS may be at a low voltage level. Therefore, the reset transistor Tr1 is turned on, and the node N2 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N2 rises to the first operating voltage VDD, and the drive transistor Td1 is fully turned on from time t3 to time t4. The reset transistor Tr2 is turned on, and the node N4 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N4 rises to the first operating voltage VDD, and the drive transistor Td2 is fully turned on from time t3 to time t4. The other transistors of the voltage source circuit 110 and the current source circuit 120 are disconnected.

[0063] During the scan period SP from time t5 to time t7, the scan signal SS may be at a high voltage level, and the bias signal BS and the reset signal RS may be at a low voltage level. Therefore, the scan transistor Ts1 and the compensation transistor Tc1 are turned on, and the node N2 is discharged with the data voltage Vdata1 through the compensation transistor Tc1, the driving transistor Td1, and the scan transistor Ts1, respectively. Then, the data voltage Vdata1 with threshold voltage compensation (the threshold voltage of the driving transistor Td1) is stored in the node N2 by the diode connection of the driving transistor Td1. In this regard, during the period from time t5 to time t6, the voltage of the node N1 rises to the data voltage Vdata1, and the voltage of the node N2 may fall from the first operating voltage VDD to a voltage equal to the data voltage Vdata1 plus the threshold voltage Vth1 of the driving transistor Td1. Scan transistor Ts2 and compensation transistor Tc2 are turned on, and node N4 is discharged with data voltage Vdata2 through compensation transistor Tc2, drive transistor Td2, and scan transistor Ts2, respectively. Then, data voltage Vdata2 with threshold voltage compensation (threshold voltage of drive transistor Td2) is stored in node N4 via the diode connection of drive transistor Td2. In this regard, during the period from time t5 to time t6, the voltage of node N3 rises to data voltage Vdata2, and the voltage of node N4 may fall from the first operating voltage VDD to a voltage equal to data voltage Vdata2 plus threshold voltage Vth2 of drive transistor Td2. The other transistors of voltage source circuit 110 and current source circuit 120 are turned off.

[0064] During the bias period BP from time t8 to time t10 (the period from time t0 to time t1 is the same as the period from time t9 to time t10), the bias signal BS may be at a high voltage level, and the scan signal SS and the reset signal RS may be at a low voltage level. Therefore, the bias transistors Tb1, Tb2, and Tb3 are turned on. The voltage at node N2 may be maintained at a voltage equal to the data voltage Vdata1 plus the threshold voltage Vth1 of the driving transistor Td1. Therefore, the voltage at node N1 may be a voltage equal to the data voltage Vdata1 minus the incremental voltage dV caused by the generation of the source current I1. The voltage at node N4 may be maintained at a voltage equal to the data voltage Vdata2 plus the threshold voltage Vth2 of the driving transistor Td2. Since the bias transistor Tb3 is turned on, the voltage at node N3 may drop to the second operating voltage VSS.

[0065] During the bias period BP from time t8 to time t10, if the electronic device 100 operates in reverse bias mode, a reverse current Ir (greater than 0) may flow from node N0 to the ground voltage (0V) through the electronic component 130. The data voltage Vdata1 may be lower than the first operating voltage VDD, and the data voltage Vdata1 may be higher than or equal to the ground voltage (0V). The voltage source circuit 110 may operate as a source follower amplifier to generate a source current I1 according to the data voltage Vdata1 provided by DL1 so as to automatically maintain the bias voltage at node N0. The bias voltage is applied to the electronic component 130. The source current I1 flows from the voltage source circuit 110 to the node N0. The bias voltage may be higher than or equal to the ground voltage (0V). If the reverse current Ir is too small to be compensated by the source current I1, the current source circuit 120 may generate a sink current I2 according to the data voltage Vdata2. The sink current I2 flows from the node N0 to the current source circuit 120. The source current I1 is greater than the sink current I2. If the reverse current Ir is sufficiently large, the sink current I2 can be zero when the drive transistor Td2 is disconnected by the data voltage Vdata2. In the embodiment of the present disclosure, the bias voltage is stable when the source current I1 is equal to the sink current I2 plus the reverse current Ir. In other words, the reverse current Ir can be equal to the source current I1 minus the sink current I2.

[0066] During the bias period BP from time t8 to time t10, if the electronic device 100 operates in a forward bias mode, a forward current If (less than 0) may flow from the ground voltage (0V) to the node N0 through the electronic component 130. The data voltage Vdata1 may be lower than the ground voltage (0V), and the data voltage Vdata1 may be higher than the second operating voltage VSS. The voltage source circuit 110 may operate as a source follower amplifier to generate a source current I1 according to the data voltage Vdata1 provided by DL1 so as to automatically maintain the bias voltage at the node N0. A bias voltage is applied to the electronic component 130. The source current I1 flows from the voltage source circuit 110 to the node N0. The bias voltage may be lower than the ground voltage (0V). The current source circuit 120 may generate a sink current I2 according to the data voltage Vdata2. The sink current I2 flows from the node N0 to the current source circuit 120. The sink current I2 is greater than the source current I1. The sink current I2 is greater than or equal to the forward current If. In an embodiment of the present disclosure, when the source current I1 is equal to the sink current I2 minus the forward current If, the bias voltage is stable.

[0067] Figure 2B According to the present disclosure Figure 1 Another timing diagram of the relevant voltages and signals of an embodiment of the present invention. Figure 1 and Figure 2B, the electronic device 100 can operate during the bias period BP, the reset period RP, and the scan period SP. In an embodiment of the present disclosure, during the scan period SP from time t5 to time t7, the data line DL1 can provide a data signal having a data voltage Vdata1 to the voltage source circuit 110, and the data line DL2 can provide a data signal having a data voltage Vdata2 to the current source circuit 120. In an embodiment of the present disclosure, an external control device can control the voltage source circuit 110 and the current source circuit 120 by adjusting the data voltage Vdata1 and the data voltage Vdata2 to operate the electronic component 130. In an embodiment of the present disclosure, the data voltage Vdata1 can be equal to the second operating voltage VSS.

[0068] During the reset period RP from time t2 to time t4, the reset signal RS may be at a high voltage level, and the bias signal BS and the scan signal SS may be at a low voltage level. Therefore, the reset transistor Tr1 is turned on, and the node N2 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N2 rises to the first operating voltage VDD, and the drive transistor Td1 is fully turned on from time t3 to time t4. The reset transistor Tr2 is turned on, and the node N4 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N4 rises to the first operating voltage VDD, and the drive transistor Td2 is fully turned on from time t3 to time t4. The other transistors of the voltage source circuit 110 and the current source circuit 120 are disconnected.

[0069] During the scan period SP from time t5 to time t7, the scan signal SS may be at a high voltage level, and the bias signal BS and the reset signal RS may be at a low voltage level. Therefore, the scan transistor Ts1 and the compensation transistor Tc1 are turned on, and the node N2 is discharged with the data voltage Vdata1 through the compensation transistor Tc1, the drive transistor Td1, and the scan transistor Ts1, respectively. Then, the data voltage Vdata1 with threshold voltage compensation (the threshold voltage of the drive transistor Td1) is stored in the node N2 through the diode connection of the drive transistor Td1. In this regard, during the period from time t5 to time t6, the voltage of the node N1 may be equal to the second operating voltage VSS because the data voltage Vdata1 may be equal to the second operating voltage VSS. The voltage of the node N2 may drop from the first operating voltage VDD to a voltage equal to the second operating voltage VSS plus the threshold voltage Vth1 of the drive transistor Td1. Scan transistor Ts2 and compensation transistor Tc2 are turned on, and node N4 is discharged with data voltage Vdata2 through compensation transistor Tc2, drive transistor Td2, and scan transistor Ts2, respectively. Then, data voltage Vdata2 with threshold voltage compensation (threshold voltage of drive transistor Td2) is stored in node N4 via the diode connection of drive transistor Td2. In this regard, during the period from time t5 to time t6, the voltage of node N3 rises to data voltage Vdata2, and the voltage of node N4 may fall from the first operating voltage VDD to a voltage equal to data voltage Vdata2 plus threshold voltage Vth2 of drive transistor Td2. The other transistors of voltage source circuit 110 and current source circuit 120 are turned off.

[0070] During the bias period BP from time t8 to time t10 (the period from time t0 to time t1 is the same as the period from time t9 to time t10), the bias signal BS may be at a high voltage level, and the scan signal SS and the reset signal RS may be at a low voltage level. Therefore, the bias transistors Tb1, Tb2, and Tb3 are turned on. The voltage at node N2 may be maintained at a voltage equal to the second operating voltage VSS plus the threshold voltage Vth1 of the driving transistor Td1. Therefore, the driving transistor Td1 is turned off, and the voltage at node N1 may be the forward voltage Vf provided by the electronic component 130. The voltage at node N4 may be maintained at a voltage equal to the data voltage Vdata2 plus the threshold voltage Vth2 of the driving transistor Td2. Since the bias transistor Tb3 is turned on, the voltage at node N3 may drop to the second operating voltage VSS.

[0071] In an embodiment of the present disclosure, during the bias period BP from time t8 to time t10, the electronic device 100 is operated in a forward current test mode. The driving transistor Td1 is turned off, so the source current I1 is zero, and the current source circuit 120 can generate a sink current I2 applied to the electronic component 130 according to the data voltage Vdata2. The sink current I2 flows from the node N0 to the current source circuit 120. The forward current If can flow from the ground voltage (0V) to the node N0 through the electronic component 130. In other words, the sink current I2 flows from the electronic component 130 to the node N0. Therefore, the electronic component 130 applied with the forward current If can perform a forward current test. The forward current If is intended to serve as an excitation for testing the electronic component 130, and an external instrument can detect a detectable change in the electronic component 130 caused by the forward current If (such as emitted light, thermal changes, physical deformation, or other changes) to determine whether the electronic component 130 is operating normally or not operating normally.

[0072] It should be noted that when the electronic device 100 is operated in the reverse bias mode, the forward bias mode, or the forward current test mode, the data voltage Vdata1 and the data voltage Vdata2 should be different. The external control device can control the voltage source circuit 110 and the current source circuit 120 by adjusting the data voltage Vdata1 and the data voltage Vdata2 to operate the electronic component 130 in the reverse bias mode, the forward bias mode, or the forward current test mode.

[0073] Figure 3 Schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 3 , electronic device 300 includes a voltage source circuit 310, a current source circuit 320, and an electronic component 330. Voltage source circuit 310, current source circuit 320, and electronic component 330 are electrically connected to node N0. Voltage source circuit 310 is further electrically connected to data line DL. Current source circuit 320 is further electrically connected to data line DL. Electronic component 330 is electrically connected between node N0 and ground voltage (0V). In an embodiment of the present disclosure, voltage source circuit 310 and current source circuit 320 form a bidirectional bias circuit, and voltage source circuit 310 and current source circuit 320 are configured to provide forward and reverse bias for electronic component 330.

[0074] In an embodiment of the present disclosure, the voltage source circuit 310 includes a drive transistor Td1, a scan transistor Ts1, a compensation transistor Tc1, a bias transistor Tb1, a reset transistor Tr1, and a storage capacitor Cst1. A first terminal of the scan transistor Ts1 is electrically connected to a data line DL. A second terminal of the scan transistor Ts1 is electrically connected to a node N1. A control terminal of the scan transistor Ts1 receives a scan signal SS1. A first terminal of the bias transistor Tb1 is electrically connected to a first operating voltage VDD. A control terminal of the bias transistor Tb1 receives a bias signal BS. A first terminal of the drive transistor Td1 is electrically connected to a second terminal of the bias transistor Tb1. A second terminal of the drive transistor Td1 is electrically connected to a second terminal of the scan transistor Ts1 via a node N1, and the second terminal of the drive transistor Td1 is further electrically connected to the electronic component 330 via a node N0. Node N1 is electrically connected to a node N0. A control terminal of the drive transistor Td1 is electrically connected to a node N2. A first terminal of the compensation transistor Tc1 is electrically connected to a control terminal of the drive transistor Td1 via a node N2. A second terminal of the compensation transistor Tc1 is electrically connected to a first terminal of the drive transistor Td1. A control terminal of the compensation transistor Tc1 receives a scan signal SS1. A first terminal of the reset transistor Tr1 is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor Tr1 is electrically connected to the first terminal of the compensation transistor Tc1 and the control terminal of the drive transistor Td1 via a node N2. The control terminal of the reset transistor Tr1 receives a reset signal RS. A first terminal of the storage capacitor Cst1 is electrically connected to the control terminal of the drive transistor Td1 via a node N2. A second terminal of the storage capacitor Cst1 is electrically connected to a reference voltage Vref1.

[0075] In an embodiment of the present disclosure, the driving transistor Td1, the scanning transistor Ts1, the compensation transistor Tc1, the bias transistor Tb1, and the reset transistor Tr1 are N-type transistors, such as N-type metal oxide semiconductors (NMOS). In other embodiments of the present disclosure, the driving transistor Td1 or other transistors may be P-type transistors, such as P-type metal oxide semiconductors (PMOS).

[0076] In an embodiment of the present disclosure, the current source circuit 320 includes a drive transistor Td2, a scan transistor Ts2, a compensation transistor Tc2, a bias transistor Tb2, a bias transistor Tb3, a reset transistor Tr2, and a storage capacitor Cst2. A first terminal of the scan transistor Ts2 is electrically connected to the data line DL. A second terminal of the scan transistor Ts2 is electrically connected to a node N3. A control terminal of the scan transistor Ts2 receives a scan signal SS2. A first terminal of the bias transistor Tb2 is electrically connected to the electronic component 330 via a node N0. A control terminal of the bias transistor Tb2 receives a bias signal BS. A first terminal of the drive transistor Td2 is electrically connected to a second terminal of the bias transistor Tb2. A second terminal of the drive transistor Td2 is electrically connected to a second terminal of the scan transistor Ts2 via a node N3. A control terminal of the drive transistor Td2 is electrically connected to a node N4. A first terminal of the compensation transistor Tc2 is electrically connected to a control terminal of the drive transistor Td2 via a node N4. A second terminal of the compensation transistor Tc2 is electrically connected to a first terminal of the drive transistor Td2. A control terminal of the compensation transistor Tc2 receives a scan signal SS2. A first terminal of the reset transistor Tr2 is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor Tr2 is electrically connected to a first terminal of the compensation transistor Tc2 and a control terminal of the drive transistor Td2 via a node N4. The control terminal of the reset transistor Tr2 receives a reset signal RS. A first terminal of the storage capacitor Cst2 is electrically connected to a control terminal of the drive transistor Td2 via a node N4. A second terminal of the storage capacitor Cst2 is electrically connected to a reference voltage Vref2. A first terminal of the bias transistor Tb3 is electrically connected to a second terminal of the drive transistor Td2 and a second terminal of the scan transistor Ts2. A second terminal of the bias transistor Tb3 is electrically connected to a second operating voltage VSS. The control terminal of the bias transistor Tb3 is electrically connected to a bias signal BS. The first operating voltage VDD may be higher than the second operating voltage VSS, and the second operating voltage VSS may be lower than a ground voltage (0V). In an embodiment of the present disclosure, the electronic component 330 may receive a third operating voltage via a node N0, and the third operating voltage is between the first operating voltage VDD and the second operating voltage VSS.

[0077] In the embodiment of the present disclosure, the driving transistor Td2, the scanning transistor Ts2, the compensation transistor Tc2, the bias transistor Tb2, the bias transistor Tb3 and the reset transistor Tr2 are N-type transistors. In other embodiments of the present disclosure, the driving transistor Td2 or other transistors may be P-type transistors.

[0078] In an embodiment of the present disclosure, the voltage source circuit 310 and the current source circuit 320 receive different scan signals.

[0079] Figure 4 According to the present disclosure Figure 3 The relevant voltage and signal timing diagram of the embodiment. Figure 3 and Figure 4 , the electronic device 300 can operate during the bias period BP, the reset period RP, the scan period SP1, and the scan period SP2. In an embodiment of the present disclosure, during the scan period SP1 from time t5 to time t7, the data line DL can provide a data signal having a data voltage Vdata1 to the voltage source circuit 310. During the scan period SP2 from time t8 to time t10, the data line DL can provide a data signal having a data voltage Vdata2 to the current source circuit 320. In an embodiment of the present disclosure, an external control device can control the voltage source circuit 310 and the current source circuit 320 by adjusting the data voltage Vdata1 and the data voltage Vdata2 to operate the electronic component 330.

[0080] During the reset period RP from time t2 to time t4, the reset signal RS may be at a high voltage level, and the bias signal BS, the scan signal SS1, and the scan signal SS2 may be at a low voltage level. Therefore, the reset transistor Tr1 is turned on, and the node N2 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N2 rises to the first operating voltage VDD, and the drive transistor Td1 is fully turned on from time t3 to time t4. The reset transistor Tr2 is turned on, and the node N4 is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage of the node N4 rises to the first operating voltage VDD, and the drive transistor Td2 is fully turned on from time t3 to time t4. The other transistors of the voltage source circuit 310 and the current source circuit 320 are disconnected.

[0081] During scan period SP1 from time t5 to time t7, scan signal SS1 may be at a high voltage level, and bias signal BS, reset signal RS, and scan signal SS2 may be at a low voltage level. Consequently, scan transistor Ts1 and compensation transistor Tc1 are turned on, and node N2 is discharged with data voltage Vdata1 through compensation transistor Tc1, drive transistor Td1, and scan transistor Ts1, respectively. Subsequently, data voltage Vdata1 with threshold voltage compensation (the threshold voltage of drive transistor Td1) is stored in node N2 via the diode connection of drive transistor Td1. Drive transistor Td2 is turned on, and the other transistors of current source circuit 320 are turned off, while the other transistors of voltage source circuit 310 are turned off. In this regard, during the period from time t5 to time t6, the voltage of node N1 rises to data voltage Vdata1, and the voltage of node N2 may fall from the first operating voltage VDD to a voltage equal to data voltage Vdata1 plus threshold voltage Vth1 of drive transistor Td1.

[0082] During scan period SP2 from time t8 to time t10, scan signal SS2 may be at a high voltage level, and bias signal BS, reset signal RS, and scan signal SS1 may be at a low voltage level. Consequently, scan transistor Ts2 and compensation transistor Tc2 are turned on, and node N4 is discharged with data voltage Vdata2 through compensation transistor Tc2, drive transistor Td2, and scan transistor Ts2, respectively. Subsequently, data voltage Vdata2 with threshold voltage compensation (the threshold voltage of drive transistor Td2) is stored in node N4 via the diode connection of drive transistor Td2. All transistors of voltage source circuit 310 are turned off, and another transistor of current source circuit 320 is turned off. In this regard, during the period from time t8 to time t9, the voltage of node N3 rises to data voltage Vdata2, and the voltage of node N4 may drop from the first operating voltage VDD to a voltage equal to data voltage Vdata2 plus threshold voltage Vth2 of drive transistor Td2.

[0083] During the bias period BP from time t11 to time t13 (the period from time t0 to time t1 is the same as the period from time t12 to time t13), the bias signal BS may be at a high voltage level, and the scan signals SS1, SS2, and reset signal RS may be at a low voltage level. Therefore, bias transistors Tb1, Tb2, and Tb3 are turned on. The voltage at node N2 may be maintained at a voltage equal to the data voltage Vdata1 plus the threshold voltage Vth1 of the driving transistor Td1. Therefore, the voltage at node N1 may be a voltage equal to the data voltage Vdata1 minus the delta voltage dV. The voltage at node N4 may be maintained at a voltage equal to the data voltage Vdata2 plus the threshold voltage Vth2 of the driving transistor Td2. Since bias transistor Tb3 is turned on, the voltage at node N3 may drop to the second operating voltage VSS.

[0084] During the bias period BP from time t11 to time t13, if the electronic device 300 operates in reverse bias mode, the reverse current Ir may flow from the node N0 to the ground voltage (0V) through the electronic component 330. The data voltage Vdata1 may be lower than the first operating voltage VDD, and the data voltage Vdata1 may be higher than or equal to the ground voltage (0V). The voltage source circuit 310 may operate as a source follower amplifier to generate a source current I1 according to the data voltage Vdata1 provided by the data line DL so as to automatically maintain the bias voltage at the node N0. The bias voltage is applied to the electronic component 330. The source current I1 flows from the voltage source circuit 310 to the node N0. The bias voltage may be higher than the ground voltage (0V). If the reverse current Ir is too small to be compensated by the source current I1, the current source circuit 320 may generate a sink current I2 according to the data voltage Vdata2. The sink current I2 flows from the node N0 to the current source circuit 320. The source current I1 is greater than the sink current I2. If the reverse current Ir is sufficiently large, the sink current I2 can be zero when the drive transistor Td2 is disconnected by the data voltage Vdata2. In the embodiment of the present disclosure, the bias voltage is stable when the source current I1 is equal to the sink current I2 plus the reverse current Ir. In other words, the reverse current Ir can be equal to the source current I1 minus the sink current I2.

[0085] During the bias period BP from time t11 to time t13, if the electronic device 300 operates in a forward bias mode, a forward current If may flow from the ground voltage (0V) to the node N0 through the electronic component 330. The data voltage Vdata1 may be lower than the ground voltage (0V), and the data voltage Vdata1 may be higher than the second operating voltage VSS. The voltage source circuit 310 may operate as a source follower amplifier to generate a source current I1 according to the data voltage Vdata1 provided by the data line DL so as to automatically maintain the bias voltage at the node N0. A bias voltage is applied to the electronic component 330. The source current I1 flows from the voltage source circuit 310 to the node N0. The bias voltage may be lower than the ground voltage (0V). The current source circuit 320 may generate a sink current I2 according to the data voltage Vdata2. The sink current I2 flows from the node N0 to the current source circuit 320. The sink current I2 is greater than the source current I1. The sink current I2 is greater than or equal to the forward current If. In an embodiment of the present disclosure, when the source current I1 is equal to the sink current I2 minus the forward current If, the bias voltage is stable.

[0086] Figure 5 Schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 5, the electronic device 500 includes a voltage source circuit 510, a current source circuit 520, an electronic component 530, a bias transistor Tb, and a capacitor C1. The voltage source circuit 510 is electrically connected to a node N0 via the bias transistor Tb. The current source circuit 520, the electronic component 530, and the capacitor C1 are electrically connected to the node N0. A first end of the capacitor C1 is electrically connected to a reference voltage Va. A second end of the capacitor C1 is electrically connected to the node N0. The voltage source circuit 510 is further electrically connected to a data line DL1 and a data line DL2. The current source circuit 520 is further electrically connected to a data line DL3. The electronic component 530 is electrically connected between the node N0 and a ground voltage (0V). In an embodiment of the present disclosure, the voltage source circuit 510 and the current source circuit 520 form a bidirectional bias circuit, and the voltage source circuit 510 and the current source circuit 520 are configured to implement forward and reverse bias for the electronic component 530. In the embodiment of the present disclosure, the voltage source circuit 510 , the current source circuit 520 , and the electronic component 530 may be pixel units of an array in a panel, and other pixel units of the array may also have the same circuit as the electronic device 500 .

[0087] In an embodiment of the present disclosure, the voltage source circuit 510 includes a drive transistor Td1, a scan transistor TsA, a scan transistor TsB, a compensation transistor Tc1, a bias transistor TbA, a bias transistor TbB, a reset transistor TrA, a reset transistor TrB, a storage capacitor CstA, and a storage capacitor CstB. A first terminal of the scan transistor TsA is electrically connected to a data line DL1. A second terminal of the scan transistor TsA is electrically connected to a node N1. A control terminal of the scan transistor TsA receives a scan signal SS. A first terminal of the scan transistor TsB is electrically connected to a data line DL2. A second terminal of the scan transistor TsB is electrically connected to a node N3. A control terminal of the scan transistor TsB receives a scan signal SS. A first terminal of the bias transistor TbA is electrically connected to a reference voltage Vref1. A control terminal of the bias transistor TbA receives a bias signal BS. A second terminal of the bias transistor TbA is electrically connected to a node N3. A first terminal of the bias transistor TbB is electrically connected to a first operating voltage VDD. A control terminal of the bias transistor TbB receives the bias signal BS. A first terminal of the drive transistor Td1 is electrically connected to a second terminal of the bias transistor TbB. A second terminal of the drive transistor Td1 is electrically connected to a second terminal of the scan transistor TsA via a node N1, and the second terminal of the drive transistor Td1 is further electrically connected to a first terminal of the bias transistor Tb. A control terminal of the drive transistor Td1 is electrically connected to a node N2. A first terminal of the compensation transistor Tc1 is electrically connected to the control terminal of the drive transistor Td1 via a node N2. A second terminal of the compensation transistor Tc1 is electrically connected to the first terminal of the drive transistor Td1. The control terminal of the compensation transistor Tc1 receives a scan signal SS. A first terminal of the reset transistor TrA is electrically connected to a first reset voltage Vrst1. A second terminal of the reset transistor TrA is electrically connected to a node N3. A control terminal of the reset transistor TrA receives a reset signal RS. A first terminal of the reset transistor TrB is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor TrB is electrically connected to the first terminal of the compensation transistor Tc1 and the control terminal of the drive transistor Td1 via a node N2. A control terminal of the reset transistor TrB receives a reset signal RS. A first terminal of the storage capacitor CstA is electrically connected to the control terminal of the driving transistor Td1 through the node N2. A second terminal of the storage capacitor CstA is electrically connected to the node N3. A first terminal of the storage capacitor CstB is electrically connected to the node N3. A second terminal of the storage capacitor CstB is electrically connected to the node N1.

[0088] In an embodiment of the present disclosure, the drive transistor Td1, the scan transistor TsA, the scan transistor TsB, the compensation transistor Tc1, the bias transistor TbA, the bias transistor TbB, the reset transistor TrA, and the reset transistor TrB are N-type transistors, such as NMOS. In other embodiments of the present disclosure, the drive transistor Td1 or other transistors may be P-type transistors, such as PMOS.

[0089] In an embodiment of the present disclosure, the current source circuit 520 includes a drive transistor Td2, a scan transistor TsC, a compensation transistor Tc2, a bias transistor TbC, a bias transistor TbD, a reset transistor TrC, a reset transistor TrD, a storage capacitor CstC, and a storage capacitor CstD. A first terminal of the scan transistor TsC is electrically connected to the data line DL3. A second terminal of the scan transistor TsC is electrically connected to a node N4. A control terminal of the scan transistor TsC receives a scan signal SS. A first terminal of the bias transistor TbC is electrically connected to a reference voltage Vref2. A control terminal of the bias transistor TbC receives a bias signal BS. A second terminal of the bias transistor TbC is electrically connected to a node N4. A first terminal of the bias transistor TbD is electrically connected to a node N0. A control terminal of the bias transistor TbD receives the bias signal BS. A first terminal of the drive transistor Td2 is electrically connected to a second terminal of the bias transistor TbD. A second terminal of the drive transistor Td2 is electrically connected to a second operating voltage VSS. A control terminal of the drive transistor Td2 is electrically connected to a node N5. A first terminal of the compensation transistor Tc2 is electrically connected to the control terminal of the drive transistor Td2 via a node N5. A second terminal of the compensation transistor Tc2 is electrically connected to the first terminal of the drive transistor Td2. The control terminal of the compensation transistor Tc2 receives a scan signal SS. A first terminal of the reset transistor TrC is electrically connected to a second reset voltage Vrst2. A second terminal of the reset transistor TrC is electrically connected to a node N4. A control terminal of the reset transistor TrC receives a reset signal RS. A first terminal of the reset transistor TrD is electrically connected to a first operating voltage VDD. A second terminal of the reset transistor TrD is electrically connected to the first terminal of the compensation transistor Tc2 and the control terminal of the drive transistor Td2 via a node N5. The control terminal of the reset transistor TrD receives the reset signal RS. A first terminal of the storage capacitor CstC is electrically connected to the control terminal of the drive transistor Td2 via a node N5. A second terminal of the storage capacitor CstC is electrically connected to a node N4. A first terminal of the storage capacitor CstD is electrically connected to a node N5. A second terminal of the storage capacitor CstD is electrically connected to a second operating voltage VSS. In an embodiment of the present disclosure, the electronic component 530 may receive a third operating voltage through the node N0 , and the third operating voltage is between the first operating voltage VDD and the second operating voltage VSS.

[0090] In an embodiment of the present disclosure, the driving transistor Td2, the scanning transistor TsC, the compensation transistor Tc2, the bias transistor TbC, the bias transistor TbD, the reset transistor TrC, and the reset transistor TrD are N-type transistors, such as NMOS. In other embodiments of the present disclosure, the driving transistor Td2 or other transistors may be P-type transistors, such as PMOS.

[0091] In an embodiment of the present disclosure, the voltage source circuit 510 and the current source circuit 520 receive the same scan signal SS.

[0092] Figure 6 According to the present disclosure Figure 5 The relevant voltage and signal timing diagram of the embodiment. Figure 5 and Figure 6 , the electronic device 500 can operate during the bias period BP, the reset period RP, and the scan period SP. In an embodiment of the present disclosure, during the scan period SP from time t5 to time t7, the data line DL1 can provide a data signal having a data voltage Vdata1 to the voltage source circuit 510, and the data line DL2 can provide a data signal having a data voltage Vdata2 to the voltage source circuit 510. The data line DL3 can provide a data signal having a data voltage Vdata3 to the current source circuit 520. In an embodiment of the present disclosure, an external control device can control the voltage source circuit 510 and the current source circuit 520 by adjusting the data voltage Vdata1, the data voltage Vdata2, and the data voltage Vdata3 to operate the electronic component 530. It should be noted that in an embodiment, the data voltage Vdata1, the data voltage Vdata2, and the data voltage Vdata3 are positive voltages.

[0093] During the reset period RP from time t2 to time t4, the reset signal RS may be at a high voltage level, and the bias signal BS and the scan signal SS may be at a low voltage level. Therefore, the reset transistors TrA and TrB are turned on. Node N2 is charged with the first operating voltage VDD. The storage capacitor CstA is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage at node N2 rises to the first operating voltage VDD, and from time t3 to time t4, the drive transistor Td1 is fully turned on. The voltage at node N3 drops to the first reset voltage Vrst1. The reset transistors TrC and TrD are turned on, and node N5 is charged with the first operating voltage VDD. The storage capacitor CstC is charged with the first operating voltage VDD. During the period from time t2 to time t3, the voltage at node N5 rises to the first operating voltage VDD, and from time t3 to time t4, the drive transistor Td2 is fully turned on. The voltage at node N4 drops to the second reset voltage Vrst2. The other transistors of the voltage source circuit 510 and the current source circuit 520 are off.

[0094] During the scan period SP from time t5 to time t7, the scan signal SS may be at a high voltage level, and the bias signal BS and the reset signal RS may be at a low voltage level. Therefore, the scan transistors TsA, TsB, and the compensation transistor Tc1 are turned on, and the node N2 is discharged with the data voltage Vdata1 through the compensation transistor Tc1, the drive transistor Td1, and the scan transistor TsA, respectively. Then, the data voltage Vdata1 with threshold voltage compensation (the threshold voltage of the drive transistor Td1) is stored in the node N2 by the diode connection of the drive transistor Td1. In this regard, during the period from time t5 to time t6, the voltage of the node N1 becomes the data voltage Vdata1, and the voltage of the node N2 may drop from the first operating voltage VDD to a voltage equal to the data voltage Vdata1 plus the threshold voltage Vth1 of the drive transistor Td1. The voltage of the node N3 becomes the data voltage Vdata2. Scan transistors TsC, TsD, and compensation transistor Tc2 are turned on, and node N4 becomes data voltage Vdata3. Then, the second operating voltage VSS with threshold voltage compensation (threshold voltage of drive transistor Td2) is stored in node N5 by the diode connection of drive transistor Td2. In this regard, during the period from time t5 to time t6, the voltage of node N5 may drop from the first operating voltage VDD to a voltage equal to the second operating voltage VSS plus the threshold voltage Vth2 of drive transistor Td2. The other transistors of voltage source circuit 510 and current source circuit 520 are turned off.

[0095] During the bias period BP from time t8 to time t10 (the period from time t0 to time t1 is the same as the period from time t9 to time t10), the bias signal BS may be at a high voltage level, and the scan signal SS and the reset signal RS may be at a low voltage level. Therefore, bias transistors Tb, TbA, TbB, TbC, and TbD are turned on. The voltage of node N2 may be changed by a voltage equal to the positive or negative absolute value of the first reference voltage Vref1 minus the data voltage Vdata2 plus the threshold voltage Vth1 of the driving transistor Td1. Therefore, the voltage of node N1 may be changed by a voltage equal to the positive or negative absolute value of the first reference voltage Vres1 minus the data voltage Vdata2 and minus the delta voltage dV from the data voltage Vdata1. The voltage of node N3 may be changed to a voltage equal to the first reference voltage Vref1. The voltage of node N4 may be changed to a voltage equal to the second reference voltage Vref2. The voltage at node N5 can be changed from the second operating voltage VSS plus the threshold voltage Vth2 of the driving transistor Td2 to a voltage equal to the positive or negative absolute value of the second reference voltage Vref2 minus the data voltage Vdata3. Thus, node N0 can have a bias voltage, and the bias voltage can be equal to the data voltage Vdata1 plus the first reference voltage Vref1, minus the data voltage Vdata2, and minus the delta voltage dV. Thus, the voltage source circuit 510 and the current source circuit 520 can receive multiple positive data voltages to generate a negative voltage bias for the electronic component 530.

[0096] In addition, as mentioned above Figures 1 to 4 In the embodiment, the electronic device 500 can also operate in a reverse bias mode, a forward bias mode, and a forward current test mode, so the details are not repeated here.

[0097] In summary, the electronic device disclosed herein can implement a bidirectional bias circuit comprising a voltage source circuit and a current source circuit, each of which has a threshold voltage compensation effect. Therefore, the electronic device disclosed herein can effectively operate electronic components in either a reverse bias mode or a forward bias mode.

[0098] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure cover modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

1. An electronic device, characterized in that: include: A voltage source circuit includes a first scanning transistor and a first driving transistor; a current source circuit comprising a second scanning transistor and a second driving transistor; as well as electronic components, wherein the voltage source circuit, the current source circuit, and the electronic component are electrically connected to a node, The first scanning transistor is coupled to the first driving transistor and the node, the first driving transistor is further coupled to a first operating voltage, and the first scanning transistor receives a first data voltage. The second scanning transistor is coupled to the second driving transistor, the second driving transistor is coupled to the node and a second operating voltage, and the second scanning transistor receives a second data voltage. wherein the voltage source circuit determines a first current flowing through the first driving transistor according to the first data voltage, and the current source circuit determines a second current flowing through the second driving transistor according to the second data voltage, The first current flows from the first driving transistor to the node, and the second current flows from the node to the second driving transistor.

2. The electronic device according to claim 1, wherein: A third current is equal to the first current minus the second current, and the third current flows from the node to the electronic component.

3. The electronic device according to claim 2, wherein: When the third current is greater than 0, the third current is a reverse current.

4. The electronic device according to claim 2, wherein: When the third current is less than 0, the third current is a forward current.

5. The electronic device according to claim 4, wherein: The first current is equal to 0 and is used for a forward current test of the electronic component.

6. The electronic device according to claim 1, wherein: Further including: a first data line; as well as The second data line, wherein the voltage source circuit is electrically connected to the first data line, and the current source circuit is electrically connected to the second data line, The voltage source circuit and the current source circuit receive the same scan signal.

7. The electronic device according to claim 6, wherein: The first scan transistor is electrically connected to the first data line, and the second scan transistor is electrically connected to the second data line, wherein the first scan transistor and the second scan transistor receive the same scan signal.

8. The electronic device according to claim 1, wherein: Further including: Data cable, The voltage source circuit and the current source circuit are electrically connected to the data line, and the voltage source circuit and the current source circuit receive different scan signals.

9. The electronic device according to claim 8, wherein: The first scan transistor and the second scan transistor are electrically connected to the data line, and the first scan transistor and the second scan transistor receive the different scan signals.

10. The electronic device according to claim 1, wherein: The voltage source circuit further includes a first compensation transistor, a first reset transistor, and a first bias transistor, and the first compensation transistor and the first scan transistor receive the same scan signal.

11. The electronic device according to claim 1, wherein: The current source circuit further includes a second compensation transistor, a second reset transistor, a second bias transistor, and a third bias transistor, and the second compensation transistor and the second scan transistor receive the same scan signal.

12. The electronic device according to claim 1, wherein: The voltage source circuit further includes a first storage capacitor, and the current source circuit further includes a second storage capacitor.

13. The electronic device according to claim 1, wherein: The voltage source circuit further includes a third transistor.

14. The electronic device according to claim 13, wherein: Further including: The third data line, The voltage source circuit is electrically connected to the third data line, and the third transistor and the first scan transistor receive the same scan signal.

15. The electronic device according to claim 13, wherein: Further including: A bias transistor is electrically connected between the voltage source circuit and the node.

16. The electronic device according to claim 13, wherein: The voltage source circuit includes a third capacitor, a third reset transistor, and a fourth bias transistor, and the current source circuit includes a fourth capacitor, a fourth reset transistor, and a fifth bias transistor.

17. The electronic device according to claim 1, wherein: The electronic component receives a third operating voltage, and the third operating voltage is between the first operating voltage and the second operating voltage.

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