LDO composite zero point tracking compensation circuit

Abstract

The application discloses a kind of LDO composite zero point tracking compensation circuits, including error amplifier (AMP1), buffer (BUF), compensation MOS tube (Mc), compensation capacitor (Cc), first resistance (R1), second resistance (R2), first MOS tube (M11), second MOS tube (M12), third MOS tube (M13), fourth MOS tube (M14), fifth MOS tube (M15), sixth MOS tube (M16), seventh MOS tube (M17) and eighth MOS tube (M18).The application can improve the technical problem that the movement rate of single voltage-controlled resistance generated zero point and output pole does not match, make the movement rate of zero point also proportional to load current, ensure that the movement rate of zero point and the movement rate of output pole are same, so as to realize the global effective compensation of LDO completely.

Description

Technical Field

[0001] This invention belongs to the field of LDO compensation technology, specifically relating to an LDO composite zero-point tracking compensation circuit. Background Technology

[0002] As the front end of a low-voltage electronic system, the LDO (Low Voltage Detector) provides a stable power supply to subsequent electronic devices. Its stability directly determines the performance and lifespan of these devices. The LDO uses negative feedback to step down the voltage of the preceding power supply and maintain a stable output. It mainly consists of a voltage reference, an error amplifier, a power transistor, and a feedback network. During operation, the error amplifier amplifies the difference between the voltage fed back from the feedback network and the reference voltage. This difference then directly or indirectly controls the conduction level of the power transistor, stabilizing the output voltage at a predetermined value through the feedback loop.

[0003] Figure 1 This is a basic schematic diagram of an LDO. For LDOs with a wide load range, the output poles change significantly with the load, increasing the risk of pole overlap. Therefore, additional compensation methods are needed to help the system achieve stability. A common approach is zero-point tracking compensation, using a MOSFET as a voltage-controlled resistor to generate a dynamic zero to offset the influence of the output poles. However, the rate of change of the zero and output poles with the load is not the same for a single voltage-controlled resistor. Under light loads, the zero-point movement speed is greater than the output pole movement speed, easily causing loop instability. Therefore, it is impossible to achieve ideal compensation across the entire load range. The zero-pole distribution of a traditional LDO system is as follows: Figure 2 As shown. See also Figure 2 The values ​​of each parameter are as follows:

[0004]

[0005] Where p1 is the output pole of the first stage of the error amplifier, R o1 C is the output impedance of the error amplifier. o1 This is the capacitor connected to the error amplifier. p2 is the output pole of the LDO, r out For the LDO output node impedance, C out z1 is the output capacitor. z1 is the parasitic ESR zero of the output capacitor, which is usually located outside the bandwidth.

[0006] Except under light load conditions, the dominant pole of the system is the output pole of the error amplifier, and the secondary pole is the output pole. Since the output node impedance is inversely proportional to the load current, the output pole will shift with the load. When the load continuously decreases, the LDO output pole will coincide with the error amplifier output pole, causing a rapid deterioration in the phase margin. One feasible method is to use zero-tracking to generate a zero that also shifts with the load. This can mitigate the phase drop caused by the LDO output pole under different load conditions. However, it will not completely cancel out the influence of the output pole, because under light load conditions, in addition to the dominant and secondary poles, other nodes generate poles that are also within the bandwidth. Therefore, the generated zero must not only mitigate the phase drop caused by the output pole but also ensure that the system gain drops as early as possible. Overall, the optimal setting for the compensated zero is to move with the output pole while still lagging behind it.

[0007] Traditional compensation methods use voltage-controlled resistors to generate a dynamic zero point, such as... Figure 3 As shown. The generated zero point z c satisfy: Assuming the power transistor is in the saturation region, then That is, the output pole p2 ∝ I out The power transistor control voltage V p satisfy:

[0008]

[0009] For R c It is located in the linear resistance region, and its value is:

[0010]

[0011] That is, the dynamic zero point z c satisfy: It can be seen that the output poles and compensation zeros do not change with the load, making it difficult to achieve ideal phase compensation across the entire load range. (Zero z) c When the load current is large, it can ensure that it follows the output pole to the low-frequency pole and lags behind the output pole. However, because the zero-point descent speed is faster, the zero-point will gradually catch up with the pole under light load, causing the loop gain to decrease later, which is less conducive to loop stability. The relative positions of the traditional compensated zero and pole are as follows: Figure 4 As shown.

[0012] Patent CN202111161887.9 discloses a small-area, fast transient response, fully integrated on-chip LDO circuit. The output power transistor is driven by a large-swing, high-gain amplifier, reducing the size of the output power transistor and the chip area, increasing the loop gain of the LDO, and shortening the output voltage recovery time. Furthermore, a load current partitioning frequency compensation circuit is used for frequency compensation, ensuring the LDO remains stable under all load conditions without sacrificing loop gain bandwidth, and also enhancing high-frequency power supply noise suppression. The compensation circuit does not consume quiescent current and has a small area, reducing the LDO's quiescent power consumption and chip area. However, this invention cannot fundamentally change the compensation rate and cannot completely solve the global compensation problem of the LDO. Summary of the Invention

[0013] Technical problem to be solved: The purpose of this invention is to overcome the shortcomings of the existing technology and propose an LDO composite zero-point tracking compensation circuit to improve the technical problem of mismatch between the zero-point and output pole movement rate generated by the current single voltage-controlled resistor.

[0014] Technical solution:

[0015] An LDO composite zero-point tracking compensation circuit includes an error amplifier (AMP1), a buffer (BUF), a compensation MOSFET (Mc), a compensation capacitor (Cc), a first resistor (R1), a second resistor (R2), a first MOSFET (M11), a second MOSFET (M12), a third MOSFET (M13), a fourth MOSFET (M14), a fifth MOSFET (M15), a sixth MOSFET (M16), a seventh MOSFET (M17), and an eighth MOSFET (M18).

[0016] The drain of the compensation MOSFET (Mc) is connected to the compensation capacitor (Cc), the source is connected to the FB terminal of the error amplifier (AMP1) and the input terminal of the buffer (BUF), and the gate is connected to the drain of the sixth MOSFET (M16). The output terminal of the buffer (BUF) is connected to the first resistor (R1), the second resistor (R2), the source of the third MOSFET (M13), and the source of the fourth MOSFET (M14), respectively. The end of the first resistor (R1) not connected to the buffer (BUF) is connected to the gate of the first MOSFET (M11) and the fourth MOSFET (M14), and the end of the second resistor (R2) not connected to the buffer (BUF) is connected to the drain of the sixth MOSFET (M16) and the seventh MOSFET (M17), respectively.

[0017] The input terminal of the error amplifier (AMP1) is connected to the reference voltage and the feedback voltage, respectively. The FB terminal is connected to the input terminal of the buffer (BUF) and the source of the compensation MOS transistor (Mc). The OUT terminal is connected to the end of the compensation capacitor (Cc) away from the compensation MOS transistor (Mc).

[0018] The gate of the third MOSFET (M13) is connected to the drain of the fourth MOSFET (M14) and the drain of the fifth MOSFET (M15), respectively; the drain of the third MOSFET (M13) is connected to the gate of the first MOSFET (M11), the gate and drain of the second MOSFET (M12), and the gate of the sixth MOSFET (M16), respectively; the gate of the seventh MOSFET (M17) and the gate and drain of the eighth MOSFET (M18) are interconnected.

[0019] The sources of the first MOSFET (M11), the second MOSFET (M12), the fifth MOSFET (M15), the sixth MOSFET (M16), the seventh MOSFET (M17), and the eighth MOSFET (M18) are connected to GND;

[0020] The impedance R of the compensation MOSFET (Mc) c It is inversely proportional to the load current, and the zero point is directly proportional to the load current. The zero point shift rate is the same as the output pole shift rate.

[0021] Furthermore, the impedance R of the compensation MOSFET (Mc) c for:

[0022]

[0023] In the formula, μ p V is the carrier mobility; Cox is the gate oxide capacitance per unit area; Mc is the aspect ratio of the compensated MOSFET; V FB The voltage at the feedback node of the error amplifier; |V thp | represents the threshold voltage of the PMOS transistor; k represents the transfer ratio of current mirrors M17 and M18; Iout' represents the output current of the sampled power transistor; and R represents the resistance values ​​of R1 and R2.

[0024] Furthermore, the error amplifier (AMP1) adopts a folded cascode structure with PMOS input, which extends the reference and feedback voltages to low common-mode voltage conditions.

[0025] Furthermore, the first MOSFET (M11), the second MOSFET (M12), the fifth MOSFET (M15), the sixth MOSFET (M16), the seventh MOSFET (M17), and the eighth MOSFET (M18) are N-channel MOSFETs; the compensation MOSFET (Mc), the third MOSFET (M13), and the fourth MOSFET (M14) are P-channel MOSFETs.

[0026] Beneficial effects:

[0027] The LDO composite zero-point tracking compensation circuit of the present invention fundamentally improves the technical problem of mismatch between zero-point movement rate and pole in the prior art, so that the zero-point movement rate is also proportional to the load current, ensuring that the zero-point movement rate is the same as the output pole movement rate, thereby completely realizing the effective compensation of the entire domain of LDO. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the basic structure of an LDO;

[0029] Figure 2 This is a schematic diagram of the zero-pole distribution of an LDO.

[0030] Figure 3 This is a schematic diagram of a traditional zero-point tracking compensation circuit.

[0031] Figure 4 This is a schematic diagram of the relative positions of zeros and poles in traditional compensation.

[0032] Figure 5 This is a schematic diagram of the LDO composite zero-point tracking compensation circuit structure according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of the improved zero-pole distribution. Detailed Implementation

[0034] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0035] Figure 5 This is a schematic diagram of the LDO composite zero-point tracking compensation circuit structure according to an embodiment of the present invention. See also... Figure 5 The LDO composite zero-point tracking compensation circuit includes an error amplifier AMP1, a buffer BUF, a compensation MOSFET Mc, a compensation capacitor Cc, a first resistor R1, a second resistor R2, a first MOSFET M11, a second MOSFET M12, a third MOSFET M13, a fourth MOSFET M14, a fifth MOSFET M15, a sixth MOSFET M16, a seventh MOSFET M17, and an eighth MOSFET M18.

[0036] The drain of the compensation MOSFET Mc is connected to the compensation capacitor Cc, the source is connected to the FB terminal of the error amplifier AMP1 and the input terminal of the buffer BUF, and the gate is connected to the drain of the sixth MOSFET M16. The output terminal of the buffer BUF is connected to the first resistor R1, the second resistor R2, the source of the third MOSFET M13 and the source of the fourth MOSFET M14, respectively. The end of the first resistor R1 that is not connected to the buffer BUF is connected to the drain of the first MOSFET M11 and the gate of the fourth MOSFET (M14), and the end of the second resistor R2 that is not connected to the buffer BUF is connected to the drain of the sixth MOSFET M16 and the seventh MOSFET M17, respectively.

[0037] The input terminal of the error amplifier AMP1 is connected to the reference voltage and the feedback voltage, respectively. The FB terminal is connected to the input terminal of the buffer BUF and the source of the compensation MOS transistor Mc. The OUT terminal is connected to the end of the compensation capacitor Cc away from the compensation MOS transistor Mc. The gate of the third MOS transistor M13 is connected to the drain of the fourth MOS transistor M14 and the drain of the fifth MOS transistor M15, respectively. The drain of the third MOS transistor M13 is connected to the gate of the first MOS transistor M11, the gate and drain of the second MOS transistor M12, and the gate of the sixth MOS transistor M16, respectively. The gate and drain of the seventh MOS transistor M17 and the eighth MOS transistor M18 are interconnected.

[0038] The sources of the first MOSFET M11, the second MOSFET M12, the fifth MOSFET M15, the sixth MOSFET M16, the seventh MOSFET M17, and the eighth MOSFET M18 are connected to GND.

[0039] The impedance R of the compensation MOSFET Mc c It is inversely proportional to the load current, and the zero point is directly proportional to the load current. The zero point shift rate is the same as the output pole shift rate. Figure 5 Vb in the equation is the bias voltage of the tail current source M15, which biases M15 into a subthreshold state.

[0040] The second MOSFET M12, the first MOSFET M11, and the sixth MOSFET M16 are the same size and carry the same current. The current in the left half of the second resistor R2 makes the output node voltage of the resistor equal to V. FB -|V thp The current in the right half of the second resistor R2 varies with the load current, and Iout' is proportional to the output current. The superimposed current flows through the second resistor R2, resulting in a final output voltage of V. FB -|V thp |-k×Iout'×R. The resistance values ​​of R1 and R2 are both R.

[0041] If this voltage is connected to the compensation MOSFET Mc, then the impedance of Mc in the linear region is:

[0042]

[0043] Where μ p C represents carrier mobility. ox The capacitance of the gate oxide layer per unit area; To compensate for the width-to-length ratio of the MOSFET; V FB The voltage at the feedback node of the error amplifier; |V thp | represents the absolute value of the PMOS transistor threshold; k represents the transfer ratio of current mirrors M17 and M18; Iout' represents the output current of the sampled power transistor; and R represents the resistance values ​​of R1 and R2.

[0044] That is, the impedance of Mc is inversely proportional to the load current, and the zero point is directly proportional to the load current, ensuring that it moves at the same speed as the output pole. Figure 6 This is a schematic diagram of the improved zero-pole distribution.

[0045] Compared with traditional zero-point tracking compensation schemes, the LDO composite zero-point tracking compensation circuit proposed in this embodiment can improve the problem of voltage-controlled zero moving too fast under light load conditions, making the zero-point moving speed the same as the output pole moving speed, so that the zero-point maintains a distance from the output pole while following the output pole, ensuring loop stability across the entire load range.

[0046] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. An LDO composite zero-point tracking compensation circuit, characterized in that, The LDO composite zero-point tracking compensation circuit includes an error amplifier (AMP1), a buffer (BUF), a compensation MOSFET (Mc), a compensation capacitor (Cc), a first resistor (R1), a second resistor (R2), a first MOSFET (M11), a second MOSFET (M12), a third MOSFET (M13), a fourth MOSFET (M14), a fifth MOSFET (M15), a sixth MOSFET (M16), a seventh MOSFET (M17), and an eighth MOSFET (M18). The drain of the compensation MOSFET (Mc) is connected to the compensation capacitor (Cc), the source is connected to the FB terminal of the error amplifier (AMP1) and the input terminal of the buffer (BUF), and the gate is connected to the drain of the sixth MOSFET (M16). The output terminal of the buffer (BUF) is connected to the first resistor (R1), the second resistor (R2), the source of the third MOSFET (M13), and the source of the fourth MOSFET (M14), respectively. The end of the first resistor (R1) not connected to the buffer (BUF) is connected to the gate of the first MOSFET (M11) and the fourth MOSFET (M14), and the end of the second resistor (R2) not connected to the buffer (BUF) is connected to the drain of the sixth MOSFET (M16) and the seventh MOSFET (M17), respectively. The input terminal of the error amplifier (AMP1) is connected to the reference voltage and the feedback voltage, respectively. The FB terminal is connected to the input terminal of the buffer (BUF) and the source of the compensation MOS transistor (Mc). The OUT terminal is connected to the end of the compensation capacitor (Cc) away from the compensation MOS transistor (Mc). The gate of the third MOSFET (M13) is connected to the drain of the fourth MOSFET (M14) and the drain of the fifth MOSFET (M15), respectively; the drain of the third MOSFET (M13) is connected to the gate of the first MOSFET (M11), the gate and drain of the second MOSFET (M12), and the gate of the sixth MOSFET (M16), respectively; the gate of the seventh MOSFET (M17) and the gate and drain of the eighth MOSFET (M18) are interconnected. The sources of the first MOSFET (M11), the second MOSFET (M12), the fifth MOSFET (M15), the sixth MOSFET (M16), the seventh MOSFET (M17), and the eighth MOSFET (M18) are connected to GND; The impedance R of the compensation MOSFET (Mc) c It is inversely proportional to the load current, and the zero point is directly proportional to the load current. The zero point shift rate is the same as the output pole shift rate.

2. The LDO composite zero-point tracking compensation circuit according to claim 1, characterized in that, The impedance R of the compensation MOSFET (Mc) c for: In the formula, μ p V is the carrier mobility; Cox is the gate oxide capacitance per unit area; Mc is the aspect ratio of the compensated MOSFET; V FB The voltage at the feedback node of the error amplifier; |V thp | represents the threshold voltage of the PMOS transistor; k represents the transfer ratio of current mirrors M17 and M18; Iout' represents the output current of the sampled power transistor; and R represents the resistance values ​​of R1 and R2.

3. The LDO composite zero-point tracking compensation circuit according to claim 1, characterized in that, The error amplifier (AMP1) employs a folded cascode structure with PMOS input, allowing the reference and feedback voltages to extend to low common-mode voltage conditions.

4. The LDO composite zero-point tracking compensation circuit according to claim 1, characterized in that, The first MOSFET (M11), the second MOSFET (M12), the fifth MOSFET (M15), the sixth MOSFET (M16), the seventh MOSFET (M17), and the eighth MOSFET (M18) are N-channel MOSFETs; the compensation MOSFET (Mc), the third MOSFET (M13), and the fourth MOSFET (M14) are P-channel MOSFETs.

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