Method, device and solid state disk for reducing read latency

Abstract

The application relates to the technical field of solid state disks, and provides a method and device for reducing read delay and a solid state disk, which are applied to the solid state disk, the solid state disk comprises a flash memory array and a cache unit, the cache unit manages cache data through a cache structure, and mainly receives a pre-reading command sent by a host, wherein the pre-reading command comprises data information corresponding to a conditional branch of a host application program; the pre-reading command is received to avoid adding an additional algorithm in the solid state disk to predict data required to be read by the host, thereby saving the cost of hardware. The flash memory array is searched according to the pre-reading command to pre-read first data corresponding to the data information, the pre-read first data is written into the cache structure, the host reads the target data from the cache unit according to the cache structure, thereby avoiding reading data in the flash memory array, and the time for reading data is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disks, and particularly relates to a method and device for reducing read latency and a solid state disk. BACKGROUND

[0002] A solid state disk (SSD) is a hard disk made of an array of solid-state electronic storage chips, and the solid state disk includes a control unit and a storage unit (FLASH storage chip or DRAM storage chip). Main physical devices of the solid state disk include a main controller, a flash array (NAND Flash) and a cache. In the process of working of the solid state disk, read command latency is one of the key performances of the solid state disk, and the read command latency includes two scenarios of cache hit and cache miss. Cache hit refers to that data is directly transmitted from the cache to the host, and the read latency of 4KB data is about 8us; cache miss refers to that the main controller first reads data from the NAND, and then transmits the data to the host, and the read latency of 4KB data is about 60us to 90us. Therefore, in actual operation, the main controller needs to predict the address to be read, so as to read data from the NAND to the cache in advance, and for the random read scenario, the main controller cannot predict the address to be read, so the delay of the random read will be larger.

[0003] In the prior art, a neural network algorithm or the like is generally used in the SSD to predict the address to be read by the host, and to perform pre-reading in advance. However, the prediction algorithm can only be applied to a sequence with strong correlation, and for a random sequence or a scenario in which multiple sequences are mixed together, the prediction effect is generally not good. Moreover, in the case of poor prediction effect, the main controller reads useless data to the cache, which has a negative effect on the performance, and the prediction algorithm occupies the software and hardware resources of the main controller, increasing the cost. SUMMARY

[0004] The embodiment of the present application mainly provides a method and device for reducing read latency and a solid state disk, and aims to solve the technical problems of low accuracy and high cost in the prior art when the solid state disk performs pre-reading.

[0005] To solve the above technical problems, one technical solution adopted by the embodiments of the present application is to provide a method for reducing read latency, applied to a solid state disk, the solid state disk comprising a flash memory array and a cache unit, the cache unit managing cache data through a cache structure, the method comprising: receiving a pre-read command sent by a host; wherein the pre-read command comprises data information corresponding to a conditional branch of a host application program; searching the flash memory array according to the pre-read command to pre-read first data corresponding to the data information, wherein the first data comprises target data; and writing the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure.

[0006] Optionally, the searching the flash memory array according to the pre-read command to pre-read target data corresponding to the data information comprises: based on the pre-read command, obtaining an address in the data information, and a length and a priority corresponding to the address; searching the flash memory array according to the address and the length corresponding to the address to obtain data consistent with the length and the address; setting the data consistent with the length and the address as the first data, and assigning the priority corresponding to the address to the first data.

[0007] Optionally, the cache structure comprises a priority, a time stamp, a valid bit, an address and a length, and the writing the pre-read first data into the cache structure comprises: obtaining the first data, and a priority, a length and an address corresponding to the first data; writing the first data and the priority, the length and the address corresponding to the first data into the cache structure respectively, and setting a valid bit of the first data to a first threshold value; obtaining a time when the first data is written into the cache structure, and recording the time as a time stamp of the first data.

[0008] Optionally, the cache structure further comprises a hit count, and after the host reads the target data from the cache unit according to the cache structure, the method further comprises: obtaining the read cache data, and a hit count corresponding to the cache data; increasing the hit count corresponding to the cache data based on a preset threshold value, and updating the hit count of the cache data based on the increased hit count.

[0009] Optionally, when the space of the cache unit is full, the method further comprises: searching the cache structure to obtain cache data with a first threshold of valid bits; obtaining a system time of the host; obtaining a time stamp of the cache data with the first threshold of valid bits, and calculating a time difference value between the system time and the time stamp; calculating a weight of the data according to a priority of the cache data with the first threshold of valid bits, the time difference value and a hit frequency; obtaining data with the minimum weight based on the weight; and deleting the data with the minimum weight to release the storage space of the cache unit.

[0010] Optionally, the method further comprises: receiving a cache invalidation command sent by the host; obtaining an address and a length corresponding to the cache invalidation command, and searching the cache structure based on the address and the length to obtain second data consistent with the address and the length; and modifying valid bits of the second data to a second threshold to release the storage space of the cache unit.

[0011] To solve the above technical problems, another technical solution adopted by the embodiment of the present application is to provide a device for reducing read latency, applied to a solid state disk, wherein the solid state disk comprises a flash memory array and a cache unit, the cache unit manages cache data through a cache structure, and the device comprises: a receiving module configured to receive a pre-read command sent by a host, wherein the pre-read command comprises data information corresponding to a conditional branch of a host application program; a cache management module configured to search the flash memory array according to the pre-read command to pre-read first data corresponding to the data information, wherein the first data comprises target data; and a reading module configured to write the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure.

[0012] Optionally, the cache management module is specifically configured to: obtain an address in the data information, and a length and a priority corresponding to the address based on the pre-read command; search the flash memory array according to the address and the length corresponding to the address to obtain data consistent with the length and the address; set the data consistent with the length and the address as first data, and assign the priority corresponding to the address to the first data.

[0013] Optionally, the cache structure comprises priority, time stamp, valid bit, address and length, and the reading module is specifically configured to: acquire the first data and the priority, length and address corresponding to the first data; write the first data and the priority, length and address corresponding to the first data into the cache structure respectively, and set the valid bit of the first data as a first threshold; acquire the time when the first data is written into the cache structure, and record the time as the time stamp of the first data.

[0014] To solve the above technical problems, another technical solution adopted by the embodiments of the present application is to provide a solid state disk, comprising: a flash memory array; a cache unit; and a main controller; wherein the main controller comprises: at least one processor; wherein the cache unit manages cache data through a cache structure; the at least one processor is in communication connection with the cache unit; the cache unit receives instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for reducing read latency as described above.

[0015] Different from the related art, the embodiments of the present application provide a method and device for reducing read latency and a solid state disk, which are applied to a solid state disk, the solid state disk comprising a flash memory array and a cache unit, the cache unit managing cache data through a cache structure, mainly by receiving a pre-reading command sent by a host, wherein the pre-reading command comprises data information corresponding to a conditional branch of a host application program; by receiving the pre-reading command, an additional algorithm is avoided to be added in the solid state disk to predict data required to be read by the host, thereby saving the cost of hardware. After receiving the pre-reading command, the flash memory array is searched according to the pre-reading command to pre-read first data corresponding to the data information, wherein the first data comprises target data, and then the pre-read first data is written into the cache structure, so that the host reads the target data from the cache unit according to the cache structure, thereby avoiding reading data in the flash memory array, and saving the time of reading data. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are schematic and not intended to be limiting of the embodiments, and in which like reference numerals designate similar items in the figures and wherein: the drawings are not to scale.

[0017] Figure 1 is a structural block diagram of a solid state disk provided by the embodiments of the present application;

[0018] Figure 2is a flow chart of a method for reducing read latency provided by an embodiment of the present application;

[0019] Figure 3 is a structural block diagram of a cache structure provided by an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of data reading provided by an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of data reading provided by another embodiment of the present application;

[0022] Figure 6 is a structural block diagram of a device for reducing read latency provided by an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0024] It should be noted that, if there is no conflict, each feature in the embodiments of the present application can be combined with each other, and all within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flow chart, in some cases, the steps shown or described can be executed in a different order from the module division in the device schematic diagram or the order in the flow chart.

[0025] Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items.

[0026] Please refer to Figure 1 , Figure 1 is a structural block diagram of a solid state disk provided by an embodiment of the present application, as shown in Figure 1 The solid state disk 100 (Solid State Drives, SSD) includes a flash array 110 (NAND Flash), a main controller 120 and a cache unit 130. The solid state disk 100 is connected to the host 200 in a wired or wireless manner to realize data interaction.

[0027] The flash memory array 110, as the storage medium of the solid state disk 100, is also called flash memory, Flash, Flash memory or Flash particle, belongs to a memory device, is a non-volatile memory, and can store data for a long time without power supply. The storage characteristics are equivalent to hard disks, so that the flash memory array 110 can become the basis of the storage medium of various portable digital devices.

[0028] The main controller 120, as a control operation module, is used for managing the internal system of the SSD. The main controller 120 includes a processor 121.

[0029] The processor 121 is connected with the cache unit 130. The processor 121 and the cache unit 130 can be connected through a bus or other manners. The processor 121 is used for running software programs, instructions and modules stored in the cache unit 130, so as to realize any method embodiment of the application.

[0030] The cache unit 130 is mainly used for caching read / write instructions sent by the host 200 and read data or write data obtained from the flash memory array 110 according to the read / write instructions sent by the host 200. The cache unit 130 can include a storage program area, which can store an operating system and at least one application program required by a function. In addition, the cache unit 130 can include a high-speed random access memory. In some embodiments, the cache unit 130 can optionally include a memory remotely arranged relative to the processor 121. The cache unit 130 manages cache data through a cache structure, so as to transmit target data from the cache data in the cache unit 130 to the host 200 according to the cache structure.

[0031] Specifically, in the working process of the solid state disk 100, the host 200 sends a pre-read command to the main controller 120, so that the main controller 120 performs a read operation on the flash memory array 110 based on the pre-read command. At this time, the main controller 120 also writes the data read from the flash memory array 110 into the cache unit 130, so that the host 200 can directly hit the cache when reading data, thereby saving the time of reading data.

[0032] Please refer to Figure 2 , Figure 2 is a flowchart of a method for reducing read delay provided by an embodiment of the application, applied to a solid state disk, as shown in Figure 2 The method comprises the following steps.

[0033] S01, receiving a pre-read command sent by a host, wherein the pre-read command includes data information corresponding to a conditional branch of a host application program.

[0034] When the host executes the application program, the host sends a pre-read command to the master controller, so that the master controller reads data from the flash memory array according to the pre-read command and writes the read data into the cache unit, so that when the host reads data, it can be directly read from the cache unit, thereby reducing the time of the host reading data. Wherein, the host application program includes a plurality of conditional branches, and the host executes the application program by executing the plurality of conditional branches.

[0035] The plurality of conditional branches respectively include an address and a length corresponding to the address. Before sending the pre-read command, the host predicts the probability of executing the plurality of conditional branches based on the plurality of conditional branches, and sets the priority of the address in the conditional branch based on the probability of the conditional branch. And based on the address, its corresponding priority and length, the pre-read command is sent to make the master controller read data from the flash memory array based on the pre-read command, wherein the data information includes an address and a length corresponding to the address. It should be noted that when the host sends the pre-read command, it will obtain all the conditional branches of the host application program, and send the pre-read command based on the address and length in the all conditional branches, so that the master controller reads the data corresponding to the address and length from the flash memory array to the cache unit, so that when the host executes any conditional branch, it will hit the cache unit.

[0036] Further, the priority of the conditional branch can be obtained according to a preset model. Specifically, the entire conditional branch of the host application program is input into the preset model, the probability of each conditional branch is obtained based on the preset model, and the priority of each conditional branch is set according to the probability of each conditional branch. Wherein, the preset model is a branch prediction unit, when the host executes the application program, by running the application program multiple times, the number of times of executing each conditional branch is counted to obtain the probability of executing each conditional branch. Based on this, in the actual application process, the probability of each conditional branch can be confirmed, and the priority of the conditional branch is also higher when the probability of the conditional branch is greater. For example, after training the branch prediction unit by running multiple times, it is confirmed that conditional branch three will be run in most cases after starting to run the application program. At this time, in the actual running, the probability of conditional branch three can be confirmed by the branch prediction unit, and based on this, the priority of conditional branch three is also the highest when setting the priority.

[0037] S02, according to the pre-read command, find the flash memory array to pre-read the first data corresponding to the data information, wherein the first data includes target data.

[0038] When the host controller receives the pre-read command, the host controller acquires the data information in the pre-read command, i.e. the address contained in the pre-read command, and the length and priority corresponding to the address, and then searches the flash array based on the address and the length corresponding to the address, so as to acquire the data consistent with the length and the address. When the data consistent with the length and the address is acquired, the data consistent with the length and the address is set as first data, and the priority corresponding to the address is assigned to the first data. The first data includes target data, which refers to the cache data currently read by the host from the cache unit.

[0039] S03, write the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure.

[0040] Please refer to Figure 3 , Figure 3 is a structure block diagram of a cache structure provided by an embodiment of the present application, as shown in Figure 3 The cache structure includes valid bit (V), priority (P), time stamp (T), hit number (H), address (ADDR), length (LEN) and data (DATA). When the host controller acquires the first data based on the pre-read command, the host controller also acquires the priority, length and address corresponding to the first data, and writes the first data and the priority, length and address corresponding to the first data into the cache structure. When the host controller writes the first data and the length, address and priority of the first data into the cache structure, the host controller also reads the system time when the first data is written, and writes the time into the cache structure as the time stamp of the first data. Moreover, when the first data and the corresponding information are written into the cache structure, the valid bit of the first data is the first threshold value. The first threshold value is a constant, which is used to determine that the data is effectively written.

[0041] When the first data and corresponding priority, length and address are written into the cache structure, if the host needs to read target data, the address and length of the target data are acquired, and a read command based on the address and length of the target data is sent to the host controller. The host controller searches the cache structure based on the read command to acquire cache data with the same length and address as the target data in the cache unit. When data with the same address and length as the target data is acquired, the host controller sends the data to the host to enable the host to read the cache data. At this time, the data is target data. When the data is read, the host controller increases the hit count of the data based on a preset threshold. The preset threshold is a constant, and the hit count is increased by the preset threshold, for example, the preset threshold is 1. The hit count refers to the number of times the cache data is read in the cache structure. When the cache data is read, the hit count of the cache data is updated once. For example, the cache structure includes data A, B, C, D, E and F. The original hit counts of the data A, B, C, D, E and F are all 2. If the data A is read, the hit count of the data A is increased by the preset threshold 1. At this time, the hit count of the data A is updated to 3.

[0042] In some embodiments, if the space of the cache unit is full, the host controller also deletes data in the cache unit to release the cache space of the cache unit. Specifically, when the cache unit is full, the host controller searches the cache structure to acquire data with a valid bit of a first threshold. When data with a valid bit of a first threshold is acquired, the host controller also acquires the priority, timestamp and hit count of the data, and acquires the current time. Then, based on the current time, the host controller acquires the difference between the current time and the timestamp, wherein the difference can confirm the retention time of the data in the cache structure. After determining the priority, time difference and hit count of the data, the host controller also acquires the weight coefficients corresponding to the priority, time difference and hit count, and calculates the weight of the data according to the weight coefficients and the priority, time difference and hit count. The calculation formula is W=(P*Wp)+(T d *W t )+(H*W h ), wherein W p , W t and W h are the priority (P), time difference (T dand a hit number (H). After calculating the weight, the host controller acquires the data with the minimum weight in the cache structure and deletes the data with the minimum weight, thereby releasing the storage space of the cache unit. After the host controller reads the data from the flash memory array and writes the data into the cache unit, the data is stored in the flash memory array and the cache unit respectively, so as to ensure that the data is also stored in the flash memory array when the data is evicted from the cache unit, thereby improving the accuracy of the solid state disk.

[0043] In some embodiments, the host controller also receives a cache invalidation command sent by the host, acquires an address and a length corresponding to the cache invalidation command, and then finds the cache structure based on the address and the length to acquire second data consistent with the address and the length. After acquiring the second data, the host controller modifies the valid bit of the second data to a second threshold, thereby releasing the storage space of the cache unit. It should be noted that the second threshold is a constant, and the second threshold and the first threshold are used to distinguish the current state of the data. When the valid bit of the data in the cache structure is modified to the second threshold, it is considered that the cache space occupied by the data corresponding to the second threshold is 0.

[0044] In some embodiments, when the host application searches for corresponding data in a linked list, each node of the linked list saves the address of the data in the solid state disk and a pointer to the next node. Specifically, when the host application searches the linked list based on target data, the address of the target data is acquired, and the address of the first node in the linked list is acquired. The data consistent with the node address in the solid state disk is found, and the data is compared with the target data. If they are consistent, it is considered that the search is successful. If they are not consistent, the next node is used to search the solid state disk. Before the host reads the solid state disk based on the first node, a pre-read command is sent to the solid state disk based on the next node of the first node. For example, as shown in FIG. 5, the host sends a pre-read command of node B before initiating a data read command of node A, sends a cache pre-read command of node C before a data read command of node B, and so on. In this way, when the application reads node A and compares the data of A, the data of B is already read into the cache of the solid state disk in parallel. When the host reads B, there is a small delay, thereby saving the data read time. Figure 4

[0045] ​In some embodiments, when the host application searches for target data in a binary tree, each node in the binary tree stores the address of data in the solid state disk and a pointer to the left and right child nodes, and in the binary tree, the data of the left child node is smaller than that of the parent node, and the data of the right child node is larger than that of the parent node. When the host application searches the binary tree based on the target data, the host application selects the parent node at the top of the binary tree, and according to the address of the data in the parent node, searches the solid state disk, reads out the data with the same address as the data in the parent node from the solid state disk, and then compares the read-out data with the target data. If the read-out data is consistent with the target data, it is considered that the search is successful, and if it is not consistent, it is determined whether the target data is smaller than the read-out data. If it is smaller, move to the left child node to continue searching, and if it is larger, move to the right child node to search.

[0046] The child nodes corresponding to the parent node are fixed, and before the host application reads the parent node, a pre-reading command is sent to the solid state disk to read the two child nodes of the parent node from the flash memory array to the cache unit to save subsequent reading time. And when reading the child nodes based on the parent node, the initial priority of the two child nodes is the same, and after comparing the target data with the read-out data, if moving to the left child node, the data priority of the left child node is increased and the data priority of the right child node is decreased; if moving to the right node, the data priority of the right child node is increased and the data priority of the left node is decreased. For example, as shown in Figure 5 , assuming that the target data is D, first, read data B and C before reading the data of node A, wherein the data priority of the left child node B is 5 and the data priority of the right child node C is 5. Next, move to node B, and the target data is smaller than B, pre-read data D and E, increase the data priority of the left child node D to 6, and decrease the data priority of the right child node E to 4.

[0047] The embodiment of the present application provides a method for reducing read delay, which is applied to a solid state disk, the solid state disk comprises a flash memory array and a cache unit, the cache unit manages cache data through a cache structure, and mainly receives a pre-read command sent by a host, wherein the pre-read command comprises data information corresponding to a conditional branch of a host application program; the pre-read command sent by the host is received, so that additional algorithms for predicting data required to be read by the host are avoided in the solid state disk, and thus the cost of hardware is saved. After the pre-read command is received, the flash memory array is searched according to the pre-read command, so as to pre-read first data corresponding to the data information, wherein the first data comprises target data, and then the pre-read first data is written into the cache structure, so that the host reads the target data from the cache unit according to the cache structure, thereby avoiding reading data in the flash memory array, and thus the time for reading data is saved.

[0048] Please refer to Figure 6 , Figure 6 is a structure block diagram of a device for reducing read delay provided by the embodiment of the present application, as shown in Figure 6 The device 300 for reducing read delay comprises a receiving module 31, a cache management module 32 and a reading module 33.

[0049] The receiving module 31 is used for receiving a pre-read command sent by a host, wherein the pre-read command comprises data information corresponding to a conditional branch of a host application program.

[0050] The cache management module 32 is used for searching the flash memory array according to the pre-read command, so as to pre-read first data corresponding to the data information, wherein the first data comprises target data.

[0051] The reading module 33 is used for writing the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure.

[0052] The cache management module 32 is specifically used for:

[0053] Based on the pre-read command, an address in the data information is acquired, and a length corresponding to the address and a priority are acquired;

[0054] According to the address and the length corresponding to the address, the flash memory array is searched, so as to acquire data consistent with the length and the address;

[0055] The data consistent with the length and the address is set as the first data, and the priority corresponding to the address is assigned to the first data.

[0056] The cache structure includes priority, time stamp, valid bit, address and length, and the reading module 33 is specifically configured to:

[0057] acquire the first data, and the priority, length and address corresponding to the first data;

[0058] write the first data and the priority, length, address corresponding to the first data into the cache structure respectively, and set the valid bit of the first data as a first threshold value;

[0059] acquire the time when the first data is written into the cache structure, and record the time as the time stamp of the first data.

[0060] It should be noted that the above-mentioned device for reducing read delay can execute the method for reducing read delay provided by the embodiments of the present application, and has the corresponding function modules and beneficial effects of executing the method. Technical details not described in detail in the device for reducing read delay embodiments can be referred to the method for reducing read delay provided by the embodiments of the present application.

[0061] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software plus a general hardware platform, and of course, it can also be realized by hardware. Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.

[0062] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; under the idea of the present application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of different aspects of the present application as described above. In order to be brief, they are not provided in details; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for reducing read latency, applied to a solid state disk, characterized in that, The solid state disk includes a flash memory array and a cache unit, and the cache unit manages cache data through a cache structure. The method includes: receiving a pre-read command sent by a host, wherein the pre-read command includes data information corresponding to a conditional branch of a host application; according to the pre-read command, searching the flash memory array to pre-read first data corresponding to the data information, wherein the first data includes target data; writing the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure; wherein the cache structure includes priority, timestamp, valid bit, address, length and hit count, and the writing of the pre-read first data into the cache structure includes: obtaining the first data and the priority, length and address corresponding to the first data; writing the first data and the priority, length and address corresponding to the first data into the cache structure, respectively, and setting the valid bit of the first data to a first threshold value; obtaining the time when the first data is written into the cache structure, and recording the time as the timestamp of the first data; when the space of the cache unit is full, the method further includes: searching the cache structure to obtain cache data with a valid bit of a first threshold value in the cache structure; obtaining the system time of the host; obtaining the timestamp of the cache data with the valid bit of the first threshold value, and calculating the time difference between the system time and the timestamp; according to the priority, time difference and hit count of the cache data with the valid bit of the first threshold value, calculating the weight of the data; based on the weight, obtaining the data with the smallest weight; deleting the data with the smallest weight to release the storage space of the cache unit.

2. The method of claim 1, wherein, According to the pre-read command, searching the flash memory array to pre-read target data corresponding to the data information includes: based on the pre-read command, obtaining the address in the data information, and the length and priority corresponding to the address; according to the address and the length corresponding to the address, searching the flash memory array to obtain data consistent with the length and address; setting the data consistent with the length and address as first data, and assigning the priority corresponding to the address to the first data.

3. The method of claim 2, wherein, When the host reads the target data from the cache unit according to the cache structure, the method further includes: obtaining the cache data that is read, and the hit count corresponding to the cache data; based on a preset threshold value, increasing the hit count corresponding to the cache data, and updating the hit count of the cache data based on the increased hit count.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: receiving a cache invalidation command sent by the host; obtaining the address and length corresponding to the cache invalidation command, and searching the cache structure based on the address and length to obtain second data consistent with the address and length of the invalid data; modifying the valid bit of the second data to a second threshold value to release the storage space of the cache unit.

5. A device for reducing read latency, applied to a solid state disk, characterized in that, The solid state disk includes a flash memory array and a cache unit, the cache unit manages cache data through a cache structure, and the device includes: A receiving module configured to receive a pre-read command sent by a host, wherein the pre-read command includes data information corresponding to a conditional branch of a host application; A cache management module configured to, according to the pre-read command, search the flash memory array to pre-read first data corresponding to the data information, wherein the first data includes target data; A reading module configured to write the pre-read first data into the cache structure, so that the host reads the target data from the cache unit according to the cache structure; The cache structure includes priority, timestamp, valid bit, address, length, and hit count, and the reading module is specifically configured to: Obtain the first data and the priority, length, and address corresponding to the first data; Write the first data and the priority, length, and address corresponding to the first data into the cache structure, respectively, and set the valid bit of the first data to a first threshold value; Obtain the time when the first data is written into the cache structure, and record the time as the timestamp of the first data; When the space of the cache unit is full, the cache management module is specifically configured to: Search the cache structure to obtain cache data with a valid bit of a first threshold value in the cache structure; Obtain the system time of the host; Obtain the timestamp of the cache data with the valid bit of the first threshold value, and calculate the time difference between the system time and the timestamp; According to the priority, time difference, and hit count of the cache data with the valid bit of the first threshold value, calculate the weight of the data; Based on the weight, obtain the data with the smallest weight; Delete the data with the smallest weight to release the storage space of the cache unit.

6. The apparatus of claim 5, wherein, The cache management module is specifically configured to: Based on the pre-read command, obtain the address in the data information, and the length and priority corresponding to the address; According to the address and the length corresponding to the address, search the flash memory array to obtain data consistent with the length and address; Set the data consistent with the length and address as first data, and assign the priority corresponding to the address to the first data.

7. A solid state drive, comprising: It includes: a flash memory array; a cache unit; and a host controller; The cache unit manages cache data through a cache structure; The host controller includes: at least one processor; wherein the at least one processor is in communication connection with the cache unit; The cache unit receives instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of reducing read latency according to any one of claims 1-4.

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