Method for evaluating non-aligned address memory access performance and storage medium thereof

Abstract

The application discloses a kind of non-alignment address memory access performance evaluation method and its storage medium, step S1, determine the non-alignment address memory access specific scene of target processor;Step S2, based on the non-alignment address memory access specific scene of target processor, determine the data type supported by target processor;Step S3, according to the size of memory page, determine the space data amount applied by target processor;Step S4, according to the cache line size of target processor, determine the stride distance of target processor and the misalignment offset of target processor.The evaluation of the non-alignment address memory access capacity of target mainstream processor is used as the evaluation value, and the non-alignment address memory access capacity of target processor is evaluated.

Description

A method for evaluating the performance of unaligned address memory access and its storage medium Technical Field

[0001] This invention relates to a method for evaluating the performance of unaligned address memory access and its storage medium, belonging to the field of unaligned address memory access technology. Background Technology

[0002] As technology advances and application software becomes increasingly complex, basic memory access remains crucial and indispensable. Memory access is further divided into aligned address access and unaligned address access. Currently, there is no clear reference standard for judging the performance of unaligned address memory access. Hardware designers will judge whether the unaligned address memory access capability meets the expected standard from the instruction design, while users generally obtain an imprecise judgment from the performance of typical applications.

[0003] Existing evaluation methods for unaligned address memory access capabilities are relatively simplistic and suffer from inaccurate results. The proportion of unaligned address memory access operations in typical application scenarios varies considerably. Hardware engineers often only consider performance from the algorithm design level of the memory access instructions themselves, with less consideration for the actual performance advantages that users can obtain. Therefore, there is a lack of clear criteria for judging the processor's ability to handle unaligned address memory access. If the performance of unaligned address memory access cannot be accurately and comprehensively tested and judged in a timely manner, users will experience performance deficiencies when using the processor in large and complex application scenarios. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a method for evaluating the performance of unaligned address memory access and its storage medium, and to analyze the performance of processor platform unaligned address memory access and the judgment of its ability to handle unaligned address memory access.

[0005] To achieve the above objectives, the present invention provides a method for evaluating the performance of unaligned address memory access, comprising:

[0006] Step S1: Determine the specific scenario of unaligned address memory access in the target processor;

[0007] Step S2: Based on the specific scenario of unaligned address memory access in the target processor, determine the data types supported by the target processor;

[0008] Step S3: Determine the amount of space data requested by the target processor based on the memory page size;

[0009] Step S4: Determine the stride distance and misalignment offset of the target processor based on the cache line size of the target processor.

[0010] First, based on the memory page size, determine the amount of space data requested by the target processor, which is achieved through the following steps:

[0011] Obtain the memory page size supported by the target processor;

[0012] In intra-page step memory access scenarios, cross-page step memory access scenarios, and contiguous memory access scenarios, a space of K times the size of the target processor's supported memory page is requested for memory access operations. The space of K times the size of the target processor's supported memory page covers the overhead of intra-page memory access, cache line memory access, cross-cache line memory access, and cross-page memory access.

[0013] First, based on the target processor's cache line size, determine the target processor's stride distance and misalignment offset through the following steps:

[0014] Get the cache line size of the target processor;

[0015] Based on the cache line size of the target processor, determine the stride distance and misalignment offset of the target processor.

[0016] First, based on the target processor's cache line size, determine the target processor's stride distance and misalignment offset through the following steps:

[0017] Based on the cache line size of the target processor's intra-page step memory access scenario, determine the step distance and misalignment offset of the target processor.

[0018] The stride distance of the target processor = the known cache line size of the target processor ÷ the length N of the long integer data processed by the target processor;

[0019] The misalignment offset of the target processor is:

[0020] The unaligned address has n bits at the end of the first cache line, and the unaligned address has Nn bits in the second cache line, where n is a natural number.

[0021] Firstly, in step S5, the memory access capabilities of the target processor with aligned and unaligned addresses are compared and analyzed to obtain a preliminary capability estimate, which is achieved through the following steps:

[0022] A comparative analysis of the aligned and unaligned address memory access capabilities of the target processor was conducted to obtain speedup scores:

[0023] Speedup score of the target processor = Unaligned address memory access time of the target processor ÷ Aligned address memory access time of the target processor;

[0024] Based on the target processor's speedup score, an estimate of the unaligned address memory access capability is obtained:

[0025] If the speedup score of the target processor is 1, it is determined that the unaligned address memory access capability of the target processor has reached the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value M.

[0026] If the speedup score of the target processor is less than 1, then the unaligned address memory access capability of the target processor is determined to be better than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is a set value L.

[0027] If the speedup score of the target processor is greater than 1, it is determined that the unaligned address memory access capability of the target processor is lower than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value H.

[0028] Prior to step S6, the target processor will be compared with other mainstream processors to obtain the evaluation results of its unaligned address memory access capability. This will be achieved through the following steps:

[0029] Identify specific scenarios for unaligned address memory access in mainstream processors;

[0030] Based on specific scenarios of unaligned address memory access in mainstream processors, determine the data types supported by mainstream processors;

[0031] Determine the amount of space data requested by mainstream processors based on the memory page size;

[0032] Based on the cache line size of mainstream processors, determine the stride distance and misalignment offset of mainstream processors.

[0033] A comparative analysis of the aligned and unaligned address memory access capabilities of mainstream processors was conducted to obtain speedup scores for mainstream processors:

[0034] Speedup score of mainstream processors = unaligned address memory access time of mainstream processors ÷ aligned address memory access time of mainstream processors;

[0035] Based on the speedup scores of mainstream processors, an estimated score is obtained for the unaligned address memory access capability of mainstream processors:

[0036] If the speedup score of the mainstream processor is 1, it is determined that the unaligned address memory access capability of the mainstream processor has reached the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value M.

[0037] If the speedup score of the mainstream processor is less than 1, then the unaligned address memory access capability of the mainstream processor is determined to be better than the aligned address memory access capability. The estimated score of the unaligned address memory access capability is a set value L.

[0038] If the speedup score of the mainstream processor is greater than 1, it is determined that the unaligned address memory access capability of the mainstream processor is lower than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value H.

[0039] The estimated score of the non-aligned address memory access capability of the benchmark mainstream processor is used as the benchmark score. If the estimated score of the non-aligned address memory access capability of the target processor is higher than the benchmark score, it is determined that the non-aligned address memory access capability of the target processor is superior to that of the mainstream processor.

[0040] If the estimated score and benchmark score of the target processor's unaligned address memory access capability are equal, then the target processor's unaligned address memory access capability is determined to be comparable to that of mainstream processors.

[0041] If the target processor's score for unaligned address memory access capability is lower than the benchmark score, then the target processor's unaligned address memory access capability is determined to be weaker than that of mainstream processors.

[0042] Prior to this, the target processor's unaligned address memory access scenarios include read-only, write-only, and read-write.

[0043] Prior to this, the target processor supports data types including integer, single-precision, double-precision, and vector classes.

[0044] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0045] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0046] The beneficial effects achieved by this invention are as follows:

[0047] 1) This invention establishes basic scenarios through typical applications, and adjusts and determines multiple types of scenarios based on the differences in hardware design between the target processor and the benchmark processor; this invention takes into account the establishment and comprehensive coverage of scenario modules based on four key factors: data types supported by the processor, memory page table replacement, cache line size, and offset size.

[0048] 2) The verification data after the completion of the scenario module is a crucial step. This invention obtains the capability assessment by comparing the aligned address memory access performance and the unaligned address memory access performance of the target processor in various scenarios.

[0049] 3) After the initial data is established, an evaluation value of the capability is finally obtained by comparing it with the non-aligned address capability of the benchmark processor itself. The evaluation value can also be used to infer the level of this capability in the industry.

[0050] 4) This invention ensures the correctness of memory access function while conducting in-depth evaluation of the memory access capability of non-boundary addresses, allowing performance bottlenecks to be exposed as early as possible. Attached Figure Description

[0051] Figure 1 is a flowchart of the present invention;

[0052] Figure 2 is a schematic diagram of a cache inline aligned address strafing memory access scenario;

[0053] Figure 3 is a diagram of a non-aligned address strafing memory access scenario within a cache line.

[0054] Figure 4 is a schematic diagram of a cross-cache row step-by-step memory access scenario. Detailed Implementation

[0055] The following embodiments are only used to illustrate the technical solutions of the present invention more clearly, and should not be used to limit the scope of protection of the present invention.

[0056] Figure 1 is a flowchart of the present invention, which includes the following steps:

[0057] S1: Determine the specific scenarios for non-aligned address memory access, including read-only, write-only, and read-write scenarios.

[0058] Based on the typical application scenarios frequently used by upper-level users, representative characteristic use cases of non-aligned address memory access can be extracted and simply divided into three typical memory access scenarios: read-only, write-only, and read-write.

[0059] S2: Determine the data types supported by the target processor;

[0060] The target processor supports data types including integer (short integer, long integer), single precision, double precision, and vector.

[0061] After confirming the scenario in S1, the corresponding program is written. The first step is to investigate the data types supported by the target processor. Generally, processors support integer (short integer, long integer), single-precision, double-precision, and vector data types. Therefore, considering the need to cover all data types of the target processor, the program needs to define memory access behaviors at various data granularities.

[0062] S3: Determine the memory page size to determine the amount of space data to be allocated.

[0063] After S2 determines the data types supported by the target processor, it first investigates the memory page size supported by the target processor. In order to reduce the overhead caused by memory page table swapping, the amount of space data requested is generally limited to the memory page size, thereby restricting the user's memory access range to only one page. For example, if the memory page size of the target processor is 4KB, then space within 4KB can be requested for memory access operations.

[0064] However, when users are using comprehensive scenarios, the amount of memory access is usually greater than the size of the memory page. Therefore, it is necessary to consider the case of cross-page access. Generally, the amount of space data requested is agreed to be an integer multiple of the size of the memory page, thereby constraining non-aligned addresses from forcibly crossing two pages.

[0065] Finally, a comprehensive scenario for continuous memory access is constructed based on the most common memory access patterns in real-world applications. In this continuous memory access scenario, which includes intra-page step memory access, cross-page step memory access, and continuous memory access, a memory space of K times the size of the target processor's supported memory pages is requested for memory access operations. The memory space of K times the size of the target processor's supported memory pages covers the overhead of intra-page memory access, cache line memory access, cross-cache line memory access, and cross-page memory access.

[0066] S4: Determine the stride distance and misalignment offset based on the cache line size in the in-page stride memory access scenario.

[0067] The memory access method is an intra-page strafing memory access scenario. Intra-page strafing memory access scenarios include intra-cache line strafing memory access scenarios and cross-cache line strafing scenarios. Based on the intra-page strafing memory access scenario determined by S3, it is first necessary to check the target processor's cache line size. Based on the cache line size, the strafing distance and misalignment offset are determined, which is achieved through the following steps:

[0068] Step distance = known target processor cache line size ÷ length N of long integer data processed by the target processor;

[0069] The unaligned offset is: n bits at the end of the first cache line and Nn bits at the end of the second cache line.

[0070] Intra-page strafing memory access scenarios are defined as memory accessing a range within a single page. When strafing memory accesses non-aligned addresses, the address may be within a cache line (intra-cache-line strafing memory access scenario) or it may span two cache lines (cross-cache-line strafing scenario). Therefore, we need to distinguish between these two scenarios here.

[0071] In cross-cache line strafing memory access scenarios, the strafing offset also needs to be considered. For example, if a processor's cache line size is 64 bytes, then processing an 8-byte long integer, the strafing distance could be 8 bytes of the data. Therefore, we can consider a 1-byte unaligned address at the end of the first cache line, with the remaining 7 bytes in the second cache line, and so on, resulting in 7 possible unaligned offsets. Intra-cache line strafing is simpler; the strafing distance is also 8 bytes of the long integer, but the 8 bytes of the data's address are all in the cache, eliminating the cross-cache line scenario. Combining the complete scenario constructed by steps S1-S4 allows for a more comprehensive analysis and assessment of the performance rationality of the hardware design for unaligned address memory access.

[0072] S5: Compare and analyze the memory access performance data of aligned and unaligned addresses of the target processor and record the preliminary capability score.

[0073] A comprehensive and reliable verification scenario was constructed in S1-S4, targeting non-aligned address memory access and incorporating typical applications, data granularity, page table replacement, cache line size, and offset size from upper-layer users. After the test cases for each scenario were prepared, the capabilities of aligned and non-aligned address memory access were tested on the target processor.

[0074] Compare and analyze the memory access capabilities of aligned and unaligned addresses under the same scenario, and record the speedup scores (i.e., unaligned memory access performance data / aligned memory access performance data).

[0075] The score for unaligned address capabilities can be estimated by accelerating the score value:

[0076] Step S5 involves comparing and analyzing the aligned and unaligned address memory access capabilities of the target processor to obtain a preliminary capability estimate, which is achieved through the following steps:

[0077] A comparative analysis of the aligned and unaligned address memory access capabilities of the target processor was conducted to obtain speedup scores:

[0078] Speedup score of the target processor = Unaligned address memory access time of the target processor ÷ Aligned address memory access time of the target processor;

[0079] Based on the target processor's speedup score, an estimate of the unaligned address memory access capability is obtained:

[0080] If the speedup score of the target processor is 1, it is determined that the unaligned address memory access capability of the target processor has reached the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value M.

[0081] If the speedup score of the target processor is less than 1, then the unaligned address memory access capability of the target processor is determined to be better than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is a set value L.

[0082] If the speedup score of the target processor is greater than 1, it is determined that the unaligned address memory access capability of the target processor is lower than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value H.

[0083] Prior to step S6, the target processor will be compared with other mainstream processors to obtain the evaluation results of its unaligned address memory access capability. This will be achieved through the following steps:

[0084] Identify specific scenarios for unaligned address memory access in mainstream processors;

[0085] Based on specific scenarios of unaligned address memory access in mainstream processors, determine the data types supported by mainstream processors;

[0086] Determine the amount of space data requested by mainstream processors based on the memory page size;

[0087] Based on the cache line size of mainstream processors, determine the stride distance and misalignment offset of mainstream processors.

[0088] A comparative analysis of the aligned and unaligned address memory access capabilities of mainstream processors was conducted to obtain speedup scores for mainstream processors:

[0089] Speedup score of mainstream processors = unaligned address memory access time of mainstream processors ÷ aligned address memory access time of mainstream processors;

[0090] Based on the speedup scores of mainstream processors, an estimated score is obtained for the unaligned address memory access capability of mainstream processors:

[0091] If the speedup score of the mainstream processor is 1, it is determined that the unaligned address memory access capability of the mainstream processor has reached the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value M.

[0092] If the speedup score of the mainstream processor is less than 1, then the unaligned address memory access capability of the mainstream processor is determined to be better than the aligned address memory access capability. The estimated score of the unaligned address memory access capability is a set value L.

[0093] If the speedup score of the mainstream processor is greater than 1, it is determined that the unaligned address memory access capability of the mainstream processor is lower than the aligned address memory access capability. It is determined that there is still a certain gap between the unaligned address memory access capability and the aligned address memory access capability of the target processor. The estimated score of the unaligned address memory access capability is set to a value H.

[0094] The estimated score of the non-aligned address memory access capability of the benchmark mainstream processor is used as the benchmark score. If the estimated score of the non-aligned address memory access capability of the target processor is higher than the benchmark score, it is determined that the non-aligned address memory access capability of the target processor is superior to that of the mainstream processor.

[0095] If the estimated score and benchmark score of the target processor's unaligned address memory access capability are equal, then the target processor's unaligned address memory access capability is determined to be comparable to that of mainstream processors.

[0096] If the estimated score for the target processor's unaligned address memory access capability is lower than the benchmark score, then the target processor's unaligned address memory access capability is determined to be weaker than that of mainstream processors. To evaluate a processor's unaligned address memory access capability, the unaligned address memory access capability of mainstream processors, which is widely recognized by industry users, can be used as an evaluation standard. After selecting a benchmark mainstream processor and performing performance verification and comparative analysis according to the same steps in S1-S5, an estimated score for the unaligned address capability is obtained.

[0097] The benchmark mainstream processors are processed through steps S1-S5 to obtain a set of estimated scores for the unaligned address capabilities of the benchmark mainstream processors.

[0098] The estimated score of the non-aligned address access capability of the benchmark mainstream processor is used as the benchmark score. Each scenario of the target processor is matched with it. If the estimated score of the non-aligned address access capability of the target processor is higher than the benchmark score, it is determined that the non-aligned address access capability of the target processor is better than that of the mainstream processor.

[0099] If the estimated score and benchmark score of the target processor's unaligned address memory access capability are equal, then the target processor's unaligned address memory access capability is determined to be comparable to that of mainstream processors.

[0100] If the estimated score for the target processor's unaligned address memory access capability is lower than the benchmark score, then the target processor's unaligned address memory access capability is determined to be weaker than that of mainstream processors. By comparing the estimated capability scores of the benchmark processors with the initial estimated score of the target processor, stronger evidence is provided for judging the target processor's unaligned address memory access capability. This offers hardware developers a faster and more effective method to identify and resolve problems in the early stages of development, shortening the development cycle and further ensuring that users obtain the best processor performance in terms of unaligned address memory access.

[0101] The key point of this invention lies in the establishment of the module for unaligned address memory access scenarios.

[0102] 1) From the user's perspective, define basic scenarios through typical applications;

[0103] 2) Adjustments and determination of multiple scenarios based on the differences in hardware design between the target processor and the benchmark processor. The establishment and comprehensive coverage of scenario modules are considered from four key factors: processor-supported data types, memory page table replacement, cache line size, and offset size.

[0104] 3) The verification data after the completion of the scenario module is a crucial step. A preliminary capability assessment is obtained by comparing the aligned address memory access performance and the unaligned address memory access performance of the target processor in various scenarios.

[0105] 4) After the initial data is established, an evaluation value of the capability is finally obtained by comparing it with the non-aligned address capability of the benchmark processor itself. The evaluation value can also be used to infer the level of this capability in the industry.

[0106] This invention largely ensured the correctness of memory access functions in the early stages of processor design and development, while also conducting in-depth evaluation of the ability to access memory at non-boundary addresses, allowing performance bottlenecks to be exposed as early as possible.

[0107] By adopting the above-mentioned unaligned address memory access performance evaluation mechanism, software developers can quickly and effectively determine the unaligned address memory access capability based on some basic hardware information of the target processor platform at each level. This enables hardware developers to have a clear judgment standard for this aspect of the chip development stage, quickly locate performance bottlenecks, further shorten the development cycle, maximize the performance needs of users when using complex software systems, enhance the user experience, and improve the competitiveness of the target processor platform at each level in the market.

[0108] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0109] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0110] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0111] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for evaluating the performance of unaligned address memory access, characterized in that, include: Step S1: Determine the specific scenario of unaligned address memory access for the target processor; the specific scenario of unaligned address memory access includes read-only, write-only, and read-write scenarios; Step S2: Determine the data types supported by the target processor based on the specific scenario of unaligned address memory access. Step S3: Determine the amount of space data requested by the target processor based on the memory page size. Step S4: Determine the stride distance and unaligned offset of the target processor based on the cache line size. Step S5: Compare and analyze the aligned and unaligned address memory access capabilities of the target processor to obtain a preliminary capability score. This is achieved through the following steps: Compare and analyze the aligned and unaligned address memory access capabilities of the target processor to obtain a speedup score: Speedup score of the target processor = Unaligned address memory access time of the target processor ÷ Aligned address memory access time of the target processor. Based on the speedup score of the target processor, an estimate of the unaligned address memory access capability is obtained: if the speedup score of the target processor is 1, it is determined that the unaligned address memory access capability of the target processor has reached the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value M; if the speedup score of the target processor is less than 1, it is determined that the unaligned address memory access capability of the target processor is superior to the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value L; if the speedup score of the target processor is greater than 1, it is determined that the unaligned address memory access capability of the target processor is inferior to the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set to a value H.

2. The method for evaluating the performance of unaligned address memory access according to claim 1, characterized in that, Based on the memory page size, the amount of space data requested by the target processor is determined through the following steps: obtain the memory page size supported by the target processor; in intra-page step memory access scenarios, cross-page step memory access scenarios, and contiguous memory access scenarios, request a space data amount of K times the memory page size supported by the target processor for memory access operations. The space data amount of K times the memory page size supported by the target processor covers the memory access overhead within the page, the memory access overhead within the cache line, the memory access overhead across the cache line, and the memory access overhead across the page.

3. The method for evaluating the performance of unaligned address memory access according to claim 2, characterized in that, The target processor's stride distance and misalignment offset are determined based on the target processor's cache line size through the following steps: obtain the target processor's cache line size; determine the target processor's stride distance and misalignment offset based on the target processor's cache line size.

4. The method for evaluating the performance of unaligned address memory access according to claim 3, characterized in that, Based on the target processor's cache line size, the stride distance and misalignment offset of the target processor are determined through the following steps: Based on the cache line size of the target processor in the intra-page stride memory access scenario, determine the stride distance and misalignment offset of the target processor; the stride distance of the target processor = the known cache line size of the target processor ÷ the length N of the long integer data processed by the target processor; the misalignment offset of the target processor is: n bits at the end of the first cache line for the unaligned address, and Nn bits at the end of the second cache line for the unaligned address, where n is a natural number.

5. The method for evaluating the performance of unaligned address memory access according to claim 1, characterized in that, The process also includes step S6, which compares the target processor with other mainstream processors to obtain an evaluation result of its unaligned address memory access capability. This is achieved through the following steps: determining specific scenarios for unaligned address memory access in mainstream processors; these scenarios include read-only, write-only, and read-write scenarios; determining the data types supported by mainstream processors based on these scenarios; determining the amount of space data requested by mainstream processors based on memory page size; determining the stride distance and unaligned offset of mainstream processors based on cache line size; comparing and analyzing the aligned and unaligned address memory access capabilities of mainstream processors to obtain a speedup score: speedup score = unaligned address memory access time ÷ aligned address memory access time; and estimating the unaligned address memory access capability based on the speedup score: if the speedup score is 1, then the unaligned address memory access capability of the mainstream processor has reached a certain level. Aligned address memory access capability and unaligned address memory access capability are estimated by a set value M. If the speedup score of the mainstream processor is less than 1, the unaligned address memory access capability of the mainstream processor is determined to be better than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set by a set value L. If the speedup score of the mainstream processor is greater than 1, the unaligned address memory access capability of the mainstream processor is determined to be worse than the aligned address memory access capability, and the estimated score of the unaligned address memory access capability is set by a set value H. The estimated score of the unaligned address memory access capability of the benchmark mainstream processor is used as the benchmark score. If the estimated score of the target processor's unaligned address memory access capability is higher than the benchmark score, the unaligned address memory access capability of the target processor is determined to be better than the unaligned address memory access capability of the mainstream processor. If the estimated score of the target processor's unaligned address memory access capability is equal to the benchmark score, the unaligned address memory access capability of the target processor is determined to be comparable to the unaligned address memory access capability of the mainstream processor. If the estimated score of the target processor's unaligned address memory access capability is lower than the benchmark score, the unaligned address memory access capability of the target processor is determined to be weaker than the unaligned address memory access capability of the mainstream processor.

6. The method for evaluating the performance of unaligned address memory access according to claim 1, characterized in that, The target processor supports data types including integer, single-precision, double-precision, and vector types.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 6.

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