Display panel

Abstract

A display panel includes a substrate, a marking structure, a plurality of active elements, and a plurality of light-emitting elements. The marking structure is disposed in a marking area of ​​the display panel. The marking structure includes a perforated layer having a plurality of through holes. The active elements are disposed in an active element area of ​​the display panel. Both the marking area and the active element area are located in the display area of ​​the display panel. The light-emitting elements are disposed in the display area of ​​the display panel. A first portion of the light-emitting element overlaps the marking structure in the normal direction of the substrate surface.

Description

Technical Field

[0001] The present invention relates to a display panel, and more particularly to a display panel including a marking structure. Background Technology

[0002] With the rapid development of display technology, the market demand for large format displays (LFDs) is increasing. Currently, splicing technology is one of the main ways to realize large format displays.

[0003] Multi-panel display technology combines multiple smaller display panels to create a larger display. In multi-panel display devices, marking structures are typically placed within the display panels to identify them. Generally, these marking structures are located in the bezel area of ​​the display panels. Summary of the Invention

[0004] The present invention provides a display panel that can improve the problem that the area of ​​the display area is limited by the marking structure.

[0005] At least one embodiment of the present invention provides a display panel. The display panel includes a substrate, a marking structure, a plurality of active elements, and a plurality of light-emitting elements. The marking structure is disposed in a marking area of ​​the display panel. The marking structure includes a perforated layer having a plurality of through holes. The active elements are disposed in an active element area of ​​the display panel. Both the marking area and the active element area are located in the display area of ​​the display panel. The light-emitting elements are disposed in the display area of ​​the display panel. A first portion of the light-emitting element overlaps the marking structure in the normal direction of the surface of the substrate.

[0006] Based on the above, by overlapping the light-emitting elements with the marking structure, the area of ​​the display area can be avoided by the marking structure, and a display panel with narrow bezels or even no bezels can be obtained. Attached Figure Description

[0007] Figure 1 This is a top view of a display panel according to an embodiment of the present invention.

[0008] Figures 2A to 9A This is a partial top view of a method for manufacturing a display panel according to an embodiment of the present invention.

[0009] Figures 2B to 9B This is a partial cross-sectional schematic diagram of a method for manufacturing a display panel according to an embodiment of the present invention.

[0010] Figure 10 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0011] Figure 11This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0012] Figure 12 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0013] Figure 13 This is a top view of a display panel according to an embodiment of the present invention.

[0014] Figure 14 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0015] Figure 15 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures:

[0017] 10, 20, 30, 40, 50, 60: Display panel

[0018] 100: Substrate

[0019] 110: First dielectric layer

[0020] 120: Second dielectric layer

[0021] 130: Third dielectric layer

[0022] 140: Fourth dielectric layer

[0023] 150: Fifth dielectric layer

[0024] 160: Sixth dielectric layer

[0025] AA: Active Component Area

[0026] AM: Alignment Marker

[0027] AMR: Alignment Marker Region

[0028] BG: Bottom Gate

[0029] CE: Common Electrode

[0030] CL: Masking layer

[0031] CLa: Leveling section

[0032] CLb: ridge

[0033] CR: Code Section

[0034] CS: Circuit Structure

[0035] D: Drain electrode

[0036] DA: Display Area

[0037] G: Gate

[0038] HL: Perforated layer

[0039] LD1, LD2: Light-emitting elements

[0040] MA: Marked area

[0041] MK: Marker structure

[0042] ND: Normal direction

[0043] P1: First Pattern Layer

[0044] P2: Second Pattern Layer

[0045] P3: Third Pattern Layer

[0046] P4: Fourth Pattern Layer

[0047] P5: Fifth Pattern Layer

[0048] P6: Sixth Pattern Layer

[0049] PD: Electrode

[0050] PD1: First pad

[0051] PD2: Second pad

[0052] S: Source

[0053] SL1, SL2, SL3, SL4: Signal lines

[0054] SM: Multiple semiconductor structures

[0055] TH: Through hole

[0056] TFT: Active element

[0057] t1, t2, t3: Thickness Detailed Implementation

[0058] Figure 1 This is a top view of a display panel according to an embodiment of the present invention. Figure 1 The substrate 100 of the display panel 10 and the light-emitting element LD1 are shown, while other structures are omitted.

[0059] Please refer to Figure 1 The display panel 10 includes a substrate 100, a marking structure (not shown), a plurality of active elements (not shown), and a plurality of light-emitting elements LD1.

[0060] A marker structure is provided in the marker area MA of the display panel 100. In some embodiments, the marker structure includes, for example, a data matrix code.

[0061] Active elements are disposed in the active element region AA of the display panel 10. In some embodiments, active elements are arrayed in the active element region AA of the display panel 10. The active elements are thin-film transistors of any form, such as top-gate thin-film transistors, bottom-gate thin-film transistors, dual-gate thin-film transistors, or other types of thin-film transistors. In some embodiments, the active elements in the active element region AA include a variety of different types of thin-film transistors.

[0062] Light-emitting elements LD1 are disposed in the display area DA of the display panel. In some embodiments, the light-emitting elements LD1 are arrayed in the display area DA of the display panel. The light-emitting elements LD1 are any form of self-emissive element, such as micro light-emitting diodes, organic light-emitting diodes, or other types of light-emitting elements. In some embodiments, the active elements in the active element area AA are electrically connected to the light-emitting elements LD1 through a circuit structure. In this embodiment, since some light-emitting elements LD1 are not located in the active element area AA, a portion of the circuit structure extends from the active element area AA to outside the active element area AA, and electrically connects the active elements in the active element area AA to the light-emitting elements LD1 outside the active element area AA.

[0063] In this embodiment, both the marker area MA and the active element area AA are located within the display area DA of the display panel. In this embodiment, the marker area MA is separated from the active element area AA. The first portion of the light-emitting element LD1 overlaps with the marker area MA; the second portion of the light-emitting element LD1 overlaps with the active element area AA; and the third portion of the light-emitting element LD1 is located within the display area DA, outside of the marker area MA and the active element area AA. In this embodiment, since the marker area MA overlaps with the display area DA, it is not necessary to place the marker area MA within the bezel area, or even to place a bezel area in the display panel 10. Therefore, the display panel 10 has the advantage of a narrow bezel or even no bezel. In some embodiments, the display panel 10 is suitable for splicing display devices. For example, multiple display panels 10 can be spliced ​​together to form a large-size display device. Since the display panel 10 can have the advantage of being bezel-less, the problem of splicing seams affecting the display image can be improved.

[0064] Although in this embodiment, the marker area MA is located at the lower right corner of the display area DA, and the active element area AA is located near the upper left corner of the display area DA, the present invention is not limited thereto. The marker area MA and the active element area AA can be located at any position in the display area DA as needed.

[0065] Figures 2A to 9A This is a partial top view of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 2B to 9B This is a partial cross-sectional schematic diagram of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 2B to 10 Corresponding to Figures 2A to 9A The median a-a' and the line b-b'. Additionally, for ease of explanation, Figures 2A to 9A as well as Figures 2B to 9B The structure is not shown to scale. For example, in Figures 2A to 9A In the active element region AA, the amplification ratio is greater than that of the marker region MA.

[0066] Please refer to this first. Figure 2A and Figure 2B A first pattern layer P1 is formed on the substrate 100. In this embodiment, the first pattern layer P1 includes a through-hole layer HL located in the marking area MA. The through-hole layer HL has a code area CR and a alignment mark area AMR surrounding the code area CR. The through-hole layer HL includes an alignment mark AM located in the alignment mark area AMR. The alignment mark AM can include any geometry. For example, in this embodiment, the through-hole layer HL includes a cross-shaped alignment mark AM located in the upper right corner, a rectangular alignment mark AM located in the upper left corner, and a triangular alignment mark AM located in the lower left corner.

[0067] In this embodiment, the method for forming the first pattern layer P1 includes: depositing a light-shielding material layer on the substrate 100; and then patterning the aforementioned light-shielding material layer by a photolithography etching process to obtain the first pattern layer P1. In some embodiments, the aforementioned light-shielding material layer includes a conductive material (e.g., metal, metal oxide, metal nitride, silicon, or other suitable material), black resin, or other opaque material. In some embodiments, the first pattern layer P1 also includes a light-shielding pattern (not shown) or a conductive pattern (not shown) located in the active element region AA. The present invention does not limit the first pattern layer P1 to be located only in the marker region MA.

[0068] Please refer to Figure 3A and Figure 3BAn information processing technique is performed on the code area CR of the via layer HL to form multiple vias TH in the code area CR. In some embodiments, the information processing technique includes dry etching (e.g., laser etching) or wet etching. In some embodiments, the information processing technique may also include photolithography. In some embodiments, the vias TH constitute a data matrix encoding. In this embodiment, the position of the via layer HL can be confirmed by the alignment mark AM of the via layer HL to reduce the probability of information processing misalignment. Figure 3A and Figure 3B In this work, the number, position, and size of the vias TH are for illustrative purposes only and are not intended to limit the invention. In other words, the number, position, and size of the vias TH can be adjusted according to actual needs. The shape of the vias TH projected vertically onto the substrate 100 can be circular, but the invention is not limited thereto. In some embodiments, the shape of the vias TH projected vertically onto the substrate 100 can be text, symbols, or other graphics.

[0069] Please refer to Figure 4A and Figure 4B A first dielectric layer 110 is formed on the substrate 100 and the first pattern layer P1. In some embodiments, the material of the first dielectric layer 110 includes oxides, nitrides, oxynitrides, organic materials or other suitable materials or stacks of the above materials. In this embodiment, the first dielectric layer 110 fills the vias TH and alignment marks AM of the through-hole layer HL.

[0070] Next, a second patterned layer P2 is formed on the first dielectric layer 110. In this embodiment, the second patterned layer P2 includes a plurality of semiconductor structures SM located in the active element region AA. For ease of explanation, Figure 4A and Figure 4B Only one semiconductor structure SM is shown. The active element region AA may include semiconductor structures SM of various shapes. For example, semiconductor structures SM may include strip-shaped, L-shaped, hook-shaped, or other geometries.

[0071] In this embodiment, the method for forming the second patterned layer P2 includes: depositing a semiconductor material layer on the first dielectric layer 110; and then patterning the semiconductor material layer by a photolithography etching process to obtain the second patterned layer P2. In some embodiments, the material of the second patterned layer P2 includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, organic semiconductor materials, oxide semiconductor materials, or other suitable materials or combinations thereof.

[0072] Please refer to Figure 5A and Figure 5BA second dielectric layer 120 is formed on the first dielectric layer 110 and the second patterned layer P2. In some embodiments, the material of the second dielectric layer 120 includes oxides, nitrides, oxynitrides, organic materials or other suitable materials or stacks of the above materials.

[0073] Next, a third pattern layer P3 is formed on the second dielectric layer 120. In this embodiment, the third pattern layer P3 includes a plurality of signal lines SL1, a plurality of gates G, and a masking layer CL.

[0074] In this embodiment, the method for forming the third patterned layer P3 includes: depositing a conductive material layer on the second dielectric layer 120; and then patterning the conductive material layer by a photolithography etching process to obtain the third patterned layer P3. In some embodiments, the material of the third patterned layer P3 includes a metal, a metal oxide, a metal nitride, or other suitable materials.

[0075] Multiple signal lines SL1 and multiple gates G are located in the active element region AA. For ease of explanation, Figure 5A Only one signal line SL1 and one gate G are shown. The gate G is connected to the corresponding signal line SL1, and the gate G overlaps the corresponding semiconductor structure SM in the normal direction ND of the surface of the substrate 100.

[0076] A masking layer CL is located in the marking area MA. The masking layer CL overlaps the via TH and the alignment mark AM on the normal direction ND of the surface of the substrate 100. In this embodiment, the marking structure MK includes a masking layer CL and a through-hole layer HL, wherein the masking layer CL and the through-hole layer HL are separated by a first dielectric layer 110 and a second dielectric layer 120. In other words, in this embodiment, the masking layer CL overlaps with and is separated from the through-hole layer HL. By setting the masking layer CL, other structures subsequently formed above the masking layer CL (such as circuit structures and light-emitting elements) can be prevented from affecting the reading of the code area CR of the through-hole layer HL. Specifically, when reading the code area CR of the through-hole layer HL from the back side of the display panel (the lower surface of the substrate 100), other structures above the masking layer CL are masked by the masking layer CL, thereby preventing other structures above the masking layer CL from affecting the reading.

[0077] Please refer to Figure 6A and Figure 6BA third dielectric layer 130 is formed on the second dielectric layer 120 and the third patterning layer P3. In some embodiments, the material of the third dielectric layer 130 includes oxides, nitrides, oxynitrides, organic materials, or other suitable materials or stacks of the above materials. In some embodiments, a photolithographic etching process is performed on the second dielectric layer 120 and the third dielectric layer 130 to form openings in the second dielectric layer 120 and the third dielectric layer 130. The aforementioned openings, for example, expose a semiconductor structure SM.

[0078] Next, a fourth pattern layer P4 is formed on the third dielectric layer 130. In this embodiment, the fourth pattern layer P4 includes a plurality of signal lines SL2, a plurality of sources S, a plurality of drains D, and a plurality of signal lines SL3.

[0079] In this embodiment, the method for forming the fourth patterned layer P4 includes: depositing a conductive material layer on the third dielectric layer 130; and then patterning the aforementioned conductive material layer by a photolithography etching process to obtain the fourth patterned layer P4. In some embodiments, the material of the fourth patterned layer P4 includes a metal, a metal oxide, a metal nitride, or other suitable materials.

[0080] Multiple signal lines SL2, multiple source terminals S, and multiple drain terminals D are located in the active component region AA. For ease of explanation, Figure 6A Only one signal line SL2, one source S, and one drain D are shown. The source S and drain D fill the openings in the second dielectric layer 120 and the third dielectric layer 130, and are connected to the corresponding semiconductor structure SM. The source S is connected to the corresponding signal line SL2. In this embodiment, the gate G, the semiconductor structure SM, the source S, and the drain D constitute an active element TFT. An array of multiple active element TFTs is disposed in the active element region AA. In this embodiment, the active element TFT is a top-gate thin-film transistor, but the present invention does not limit the active element region AA to only having top-gate thin-film transistors. In some embodiments, the active element region AA also includes other types of thin-film transistors.

[0081] Signal line SL3 is located in the marking area MA and extends from the marking area MA to outside the marking area MA. A portion of signal line SL3 overlaps with the marking structure MK in the normal direction ND of the surface of substrate 100.

[0082] Please refer to Figure 7A and Figure 7BA fourth dielectric layer 140 is formed on the third dielectric layer 130 and the fourth pattern layer P4. In some embodiments, the fourth dielectric layer 140 is made of oxide, nitride, oxynitride, organic material, or other suitable material or a stack of such materials. In some embodiments, a photolithographic etching process is performed on the fourth dielectric layer 140 to form an opening in the fourth dielectric layer 140. The opening, for example, exposes the drain electrode D.

[0083] Next, a fifth pattern layer P5 is formed on the fourth dielectric layer 140. In this embodiment, the fifth pattern layer P5 includes a plurality of signal lines SL4.

[0084] In this embodiment, the method for forming the fifth pattern layer P5 includes: depositing a conductive material layer on the fourth dielectric layer 140; and then patterning the aforementioned conductive material layer by a photolithography etching process to obtain the fifth pattern layer P5. In some embodiments, the material of the fifth pattern layer P5 includes a metal, a metal oxide, a metal nitride, or other suitable materials.

[0085] Signal lines SL4 are disposed in the active element region AA, and each signal line SL4 is electrically connected to the drain D of a corresponding active element TFT. For example, the signal line SL4 fills an opening in the fourth dielectric layer 140 to connect to the corresponding drain D. In this embodiment, at least a portion of the signal lines SL4 extend from the active element region AA into the display area outside the active element region AA. For example, a portion of the signal lines SL4 extend from the active element region AA into the marker region MA. A portion of the signal lines SL4 overlaps the marker structure MK in the normal direction ND of the surface of the substrate 100. Furthermore, another portion of the signal lines SL4 does not extend outside the active element region AA.

[0086] In this embodiment, the circuit structure CS includes signal lines SL1, SL2, SL3, and SL4. The circuit structure CS partially overlaps the marking structure MK in the normal direction ND of the surface of the substrate 100. For example, signal lines SL3 and SL4 in the circuit structure CS partially overlap the marking structure MK in the normal direction ND.

[0087] Please refer to Figure 8A and Figure 8B A fifth dielectric layer 150 is formed on the fourth dielectric layer 140 and the fifth pattern layer P5. In some embodiments, the fifth dielectric layer 150 is made of oxide, nitride, oxynitride, organic material, or other suitable material or a stack of such materials. In some embodiments, a photolithographic etching process is performed on the fifth dielectric layer 150 to form an opening in the fifth dielectric layer 150. The opening, for example, exposes the signal line SL4.

[0088] Next, a sixth pattern layer P6 is formed on the fifth dielectric layer 150. In this embodiment, the sixth pattern layer P6 includes a common electrode CE, a plurality of first pads PD1, and a plurality of second pads PD2.

[0089] In this embodiment, the method for forming the sixth pattern layer P6 includes: depositing a conductive material layer on the fifth dielectric layer 150; and then patterning the aforementioned conductive material layer by a photolithography etching process to obtain the sixth pattern layer P6. In some embodiments, the material of the sixth pattern layer P6 includes a metal, a metal oxide, a metal nitride, or other suitable materials.

[0090] A common electrode CE, multiple first pads PD1, and multiple second pads PD2 are located in the display area, with the common electrode CE extending from the active element area AA to the marker area MA. In this embodiment, the first portion of the common electrode CE, the first portion of the first pads PD1, and the first portion of the second pads PD2 are located in the active element area AA, the second portion of the common electrode CE, the second portion of the first pads PD1, and the second portion of the second pads PD2 are located in the marker area MA, and the third portion of the common electrode CE, the third portion of the first pads PD1, and the third portion of the second pads PD2 are located in other display areas outside the active element area AA and the marker area MA.

[0091] In this embodiment, the common electrode CE has multiple openings, each corresponding to a pixel. A first pad PD1 and a second pad PD2 are located within the openings of the common electrode CE, with the second pad PD2 connected to the common electrode CE and the first pad PD1 connected to the corresponding signal line SL4. For example, the first pad PD1 fills an opening in the fifth dielectric layer 150 to connect to the corresponding signal line SL4.

[0092] Please refer to Figure 9A and Figure 9B A sixth dielectric layer 160 is formed on the fifth dielectric layer 150 and the sixth pattern layer P6. In some embodiments, the fifth dielectric layer 150 is made of oxide, nitride, oxynitride, organic material, or other suitable material or a stack of such materials. In some embodiments, the sixth dielectric layer 160 includes a solder resist. In some embodiments, a photolithographic etching process is performed on the sixth dielectric layer 160 to form openings in the sixth dielectric layer 160. These openings, for example, expose the first pad PD1 and the second pad PD2.

[0093] Next, multiple light-emitting elements LD1 are bonded to the sixth pattern layer P6. For example, each light-emitting element LD1 is connected to its corresponding first pad PD1 and corresponding second pad PD2 via solder, anisotropic conductive film (ACF), or other bonding materials. (See circuit structure CS for reference.) Figure 7A The common electrode CE is electrically connected to the light-emitting element LD1 via the first pad PD1; and the common electrode CE is electrically connected to the light-emitting element LD1 via the second pad PD2. In some embodiments, the light-emitting element LD1 includes miniature light-emitting diodes of different colors.

[0094] Light-emitting elements LD1 are distributed throughout the display area. In this embodiment, the first portion of the light-emitting elements LD1 is located in the marking area MA and overlaps with the marking structure MK in the normal direction ND of the surface of the substrate 100; the second portion of the light-emitting elements LD1 is located in the active element area AA; and the third portion of the light-emitting elements LD1 is located in other display areas besides the active element area AA and the marking area MA. In this embodiment, the circuit structure CS (please refer to...) Figure 7A The light-emitting element LD1 is electrically connected through the first pad PD1 and the second pad PD2 of the sixth pattern layer P6. Through the configuration of the circuit structure CS, the active element TFT in the active element region AA can be electrically connected not only to the light-emitting element LD1 in the second part of the active element region AA, but also to the light-emitting element LD1 in the first part and the light-emitting element LD1 in the third part outside the active element region AA.

[0095] Based on the above, since the first part of the light-emitting element LD1 overlaps with the marking structure MK, the display area of ​​the display panel 10 can cover the range of the marking area MA, thereby increasing the area of ​​the display area.

[0096] Figure 10 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. It must be noted that... Figure 10 The embodiments follow Figures 2B to 9B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0097] Figure 10 The display panel 20 and Figure 9B The main difference between the display panel 10 and the display panel 20 is that the light-emitting element LD1 in the display panel 10 is a miniature light-emitting diode, while the light-emitting element LD2 in the display panel 20 is an organic light-emitting diode.

[0098] Please refer to Figure 10The fifth pattern layer P5 includes multiple signal lines SL4 and multiple electrodes PD.

[0099] Signal lines SL4 are disposed in the active element region AA, and each signal line SL4 is electrically connected to the drain D of a corresponding active element TFT. In this embodiment, at least a portion of the signal lines SL4 extend from the active element region AA into the display area outside the active element region AA. For example, a portion of the signal lines SL4 extend from the active element region AA into the marker region MA and are connected to the electrode PD in the marker region MA. A portion of the signal lines SL4 overlaps the marker structure MK in the normal direction ND of the surface of the substrate 100.

[0100] Multiple electrodes (PDs) are distributed in the display area. Each electrode (PD) is electrically connected to a corresponding signal line (SL4). In this embodiment, the first portion of the electrode (PD) is located in the marker area (MA); the second portion of the electrode (PD) (not shown) is located in the active element area (AA); and the third portion of the electrode (PD) (not shown) is located in other display areas outside the active element area (AA) and the marker area (MA).

[0101] The fifth dielectric layer 150 is located on the fifth patterned layer P5 and has multiple openings overlapping the multiple electrodes PD. Multiple organic material layers OL are respectively filled into the multiple openings of the fifth dielectric layer 150 and connected to the multiple electrodes PD. A common electrode CE is located on the fifth dielectric layer 150 and connected to the multiple organic material layers OL.

[0102] A common electrode CE, an organic material layer OL, and an electrode PD are overlapped to form a light-emitting element LD2. The light-emitting elements LD2 are distributed throughout the display area. In this embodiment, the first portion of the light-emitting elements LD2 is located in the marking area MA and overlaps with the marking structure MK in the normal direction ND of the surface of the substrate 100; the second portion of the light-emitting elements LD1 is located in the active element area AA; and the third portion of the light-emitting elements LD1 is located in other display areas outside the active element area AA and the marking area MA. In this embodiment, the active element TFT in the active element area AA is electrically connected to the light-emitting elements LD2 through a circuit structure. Through the circuit structure, the active element TFT in the active element area AA can be electrically connected not only to the second portion of the light-emitting elements LD2 in the active element area AA, but also to the first portion of the light-emitting elements LD2 and the third portion of the light-emitting elements LD2 outside the active element area AA.

[0103] Based on the above, since the first part of the light-emitting element LD2 overlaps with the marking structure MK, the display area of ​​the display panel 20 can cover the range of the marking area MA, thereby increasing the area of ​​the display area.

[0104] Figure 11This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. It must be noted that... Figure 11 The embodiments follow Figures 2B to 9B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0105] Figure 11 The display panel 30 and Figure 9B The main difference in the display panel 10 is that the active element TFT in the display panel 30 is a dual-gate thin-film transistor.

[0106] Please refer to Figure 11 In this embodiment, the active element TFT further includes a bottom gate BG. The bottom gate BG belongs to the same film layer (first pattern layer P1) as the through-hole layer HL. In other words, the bottom gate BG and the through-hole layer HL are formed simultaneously. The gate G of the active element TFT is a top gate, and the gate G and the shielding layer CL belong to the same film layer (third pattern layer P3). In other words, the gate G and the shielding layer CL are formed simultaneously.

[0107] Figure 12 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. It must be noted that... Figure 12 The embodiments follow Figures 2B to 9B The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0108] Figure 12 The display panel 40 and Figure 9B The main difference in the display panel 10 is that the shielding layer CL in the display panel 40 overlaps with and contacts the perforated layer HL.

[0109] In this embodiment, the masking layer CL is formed directly on the through-hole layer HL, and the masking layer CL fills the through-hole TH. In this embodiment, the masking layer CL can be a conductive material, a semiconductor material, or an insulating material (e.g., black resin). In other words, the present invention does not limit the masking layer CL to the third patterning layer P3 (see reference). Figure 5B The masking layer CL can also belong to other pattern layers.

[0110] Figure 13 This is a top view of a display panel according to an embodiment of the present invention. It should be noted that... Figure 13 The embodiments follow Figure 1The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0111] Figure 13 The display panel 50 and Figure 1 The main difference in the display panel 10 is that the marker area MA of the display panel 50 overlaps with the active element area AA. In other words, the marker area MA is located within the active element area AA.

[0112] In this embodiment, both the marker area MA and the active element area AA are located within the display area DA of the display panel. In this embodiment, the first portion of the light-emitting element LD1 overlaps with the marker area MA; the second portion of the light-emitting element LD1 overlaps with the display area DA outside the marker area MA. In this embodiment, since the marker area MA overlaps with the display area DA, it is not necessary to place the marker area MA within the bezel area, or even to place a bezel area in the display panel 50. Therefore, the display panel 50 has the advantage of a narrow bezel or even a bezel-less design. In some embodiments, the display panel 50 is suitable for splicing display devices. For example, multiple display panels 50 can be spliced ​​together to form a large-size display device. Since the display panel 50 can have the advantage of a bezel-less design, the problem of splicing seams affecting the display image can be improved.

[0113] Figure 14 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. For example, Figure 14 for Figure 13 A cross-sectional view of the display panel 50 at the location of the marking area MA.

[0114] Please refer to Figure 14 In this embodiment, the active element TFT is superimposed on the marking structure MK in the normal direction ND of the surface of the substrate 100.

[0115] Figure 15 This is a cross-sectional schematic diagram of a display panel according to an embodiment of the present invention. For example, Figure 15 This is a cross-sectional view of the display panel 60 at the location of the marking area MA.

[0116] Please refer to Figure 15 In this embodiment, an information technology process including dry etching, such as laser etching, is performed on the through-hole layer HL. Figure 3A and Figure 3BAfter the described process, the via TH of the through-hole layer HL is raised, so that the through-hole layer HL includes a flat portion HLa and a plurality of raised portions HLb. The raised portions HLb surround the via TH. The circuit structure includes a signal line (e.g., a signal line SL3). The signal line SL3 partially overlaps the raised portion HLb in the normal direction ND of the surface of the substrate 100. In some embodiments, the first dielectric layer 110, the second dielectric layer 120, the masking layer CL, and the third dielectric layer 130 have surface unevenness problems due to the raised portions HLb. In some embodiments, the thickness t2 of the raised portion HLb is reduced as the thickness of the through-hole layer HL before the information processing (which can also be regarded as the thickness t1 of the flat portion HLa) is reduced. In some embodiments, by reducing the thickness of the flat portion HLa or increasing the thickness of the signal line SL3, the signal line SL3 is less likely to break due to the unevenness of the underlying structure. In some embodiments, the thickness t1 of the flat portion HLa of the through-hole layer HL is less than 1 / 7 of the thickness t3 of the signal line SL3. Although in this embodiment the via layer HL includes the raised portion HLb, the invention is not limited thereto. In other embodiments, the information processing includes, for example, wet etching, and the via layer HL does not include the raised portion HLb.

Claims

1.A display panel, comprising: a substrate; a mark structure disposed in a mark region of the display panel, wherein the mark structure comprises a via layer, and the via layer has a plurality of through holes; a plurality of active elements disposed in an active element region of the display panel, wherein the mark region and the active element region are both located in a display region of the display panel; and a plurality of light emitting elements disposed in the display region of the display panel, wherein a first portion of the light emitting elements overlaps the mark structure in a normal direction of a surface of the substrate. 2.The display panel of claim 1, wherein the mark structure further comprises a shielding layer, wherein the shielding layer overlaps and separates from the via layer. 3.The display panel of claim 1, wherein the mark structure further comprises a shielding layer, wherein the shielding layer overlaps and contacts the via layer. 4.The display panel of claim 1, wherein the via layer has a code region and a positioning mark region surrounding the code region, the through holes are located in the code region, and the via layer further comprises a positioning mark located in the positioning mark region, and wherein the mark structure further comprises a shielding layer, and the shielding layer overlaps the through holes and the positioning mark in the normal direction of the surface of the substrate. 5.The display panel of claim 1, further comprising: a wiring structure electrically connected to the first portion of the light emitting elements, and the wiring structure partially overlaps the mark structure in the normal direction of the surface of the substrate. 6.The display panel of claim 5, wherein the via layer comprises a flat portion and a plurality of raised portions, the raised portions surround the through holes, wherein the wiring structure comprises a signal line, and the signal line partially overlaps the raised portions in the normal direction of the surface of the substrate. 7.The display panel of claim 6, wherein a thickness of the flat portion of the via layer is less than 1 / 7 of a thickness of the signal line. 8.The display panel of claim 1, wherein the mark region overlaps the active element region. 9.The display panel of claim 1, wherein the mark region separates from the active element region. 10.The display panel of claim 1, wherein the active elements comprise a dual-gate thin film transistor, wherein a bottom gate of the dual-gate thin film transistor and the via layer belong to a same film layer. 11.The display panel of claim 10, wherein the mark structure further comprises a shielding layer, wherein the shielding layer partially overlaps the via layer in the normal direction of the surface of the substrate, and a top gate of the dual-gate thin film transistor and the shielding layer belong to a same film layer. 12.The display panel of claim 1, further comprising: a common electrode, wherein the common electrode is electrically connected to the light emitting elements, and the common electrode extends from the active element region into the mark region. ​

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