Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes providing a substrate having a first region and a second region, forming a first fin structure in the first region and a second fin structure in the second region, forming a patterned mask in the second region, and performing a processing fabrication process to enlarge the first fin structure, thereby making a top surface of the first fin structure different from a top surface of the second fin structure.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201710655459.9, application date: August 3, 2017, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for expanding the top of a fin-like structure. Background Technology

[0003] In recent years, with the continuous shrinking of field-effect transistor (FET) device dimensions, the development of existing planar FET devices has reached the limits of fabrication technology. To overcome these limitations, replacing planar FET devices with non-planar FET devices, such as fin field-effect transistors (Fin FETs), has become the mainstream development trend. Because the three-dimensional structure of Fin FETs increases the contact area between the gate and the fin structure, it further enhances the gate's control over the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-sized devices and suppressing the short-channel effect (SCE). Furthermore, since Fin FETs have a wider channel width for the same gate length, they can achieve double the drain drive current. Moreover, the threshold voltage of the transistor device can be controlled by adjusting the work function of the gate.

[0004] Generally, after semiconductor fabrication processes entered the 10-nanometer generation, the critical dimension (CD) of the fin structure played a crucial role in the overall device performance. In the current fabrication process for fin field-effect transistors (FETs), the fin structure in the core region and the fin structure in the input / output region ultimately have approximately the same critical dimension. However, since the core region typically requires a larger critical dimension to increase the channel capacity, while the input / output region requires a smaller critical dimension to mitigate the short-channel effect (SCE), current designs clearly cannot simultaneously meet the needs of both regions. Therefore, how to improve this problem within the current FET architecture is an important research topic. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a substrate is provided having a first region and a second region. Then, a first fin structure is formed in the first region and a second fin structure is formed in the second region. A patterned mask is formed in the second region. Subsequently, a processing step is performed to enlarge the first fin structure, thereby making the upper surface of the first fin structure different from the upper surface of the second fin structure.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a substrate having a first region and a second region, a first fin structure disposed in the first region and a second fin structure disposed in the second region, wherein the lower surface of the first fin structure is equal to the lower surface of the second fin structure and the upper surface of the first fin structure is different from the upper surface of the second fin structure. Attached Figure Description

[0007] Figures 1 to 6 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0008] Explanation of main component symbols

[0009] 12 Base 14 First Region

[0010] 16 Second Region 18 First Fin Structure

[0011] 20 Second fin-like structure 22 Shallow groove isolation

[0012] 24 Upper Half 26 Lower Half

[0013] 28 First gate structure 30 Second gate structure

[0014] 32 Dielectric layer 34 Gate material layer

[0015] 36 Spacer wall 38 Source / drain region

[0016] 40 Contact hole etch stop layer 42 Interlayer dielectric layer

[0017] 44 Patterned mask 46 Semiconductor layer

[0018] 48 Dielectric layer 50 High dielectric constant dielectric layer

[0019] 52 Work function metal layer 54 Low impedance metal layer

[0020] 56 First metal gate 58 Second metal gate

[0021] 60 grooves Detailed Implementation

[0022] Please refer to Figures 1 to 3 ,in Figure 1 A top view of a semiconductor device according to an embodiment of the present invention. Figure 2 The left half is Figure 1 A schematic diagram of a cross-section along the tangent AA'. Figure 2 The right half is Figure 1 A schematic cross-sectional view along the tangent BB'. Figure 3 The left half is Figure 1 A schematic cross-sectional view along the tangent CC'. Figure 3 The right half is Figure 1 A schematic cross-sectional view along the tangent DD'. (See diagram below.) Figures 1 to 3 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and a first region 14 and a second region 16 are defined on the substrate, wherein the first region 14 is preferably a core region for subsequent fabrication of active components and the second region 16 is preferably an input / output region for connecting active components and peripheral components.

[0023] Then, multiple fin-like structures are formed on the substrate 12, for example, a first fin-like structure 18 is formed in the first region 14 and a second fin-like structure 20 is formed in the second region 16. A shallow trench isolation (STI) 22 is then formed around the first fin-like structure 18 and the second fin-like structure 20. In this embodiment, the shallow trench isolation 22 is formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer on the substrate 12, completely covering each fin-like structure. Next, a chemical mechanical polishing (CMP) process combined with an etching process is used to remove part of the silicon oxide layer, leaving the remaining silicon oxide layer below the surface of the fin-like structures to form the shallow trench isolation 22.

[0024] It is worth noting that, such as Figure 3 As shown, some of the first fin structures 18 and the second fin structures 20 may be consumed to form silicon dioxide during the formation of the dielectric layer 32, resulting in different widths at the top and bottom. Therefore, after the formation of the dielectric layer 32, each of the first fin structures 18 and the second fin structures 20 preferably defines an upper half 24 and a lower half 26, respectively. The junction of the upper half 24 and the lower half 26 in the first region 14 and the second region 16 (as shown by the dotted line in the figure) is preferably aligned with the upper surface of the shallow trench isolation 26, and the lower surfaces of the upper half 24 of the first region 14 and the second region 16 are both smaller than the upper surfaces of the lower half 26 of the first region 14 and the second region 16, respectively.

[0025] According to a preferred embodiment of the present invention, each fin structure is preferably fabricated using techniques such as sidewall image transfer (SIT). The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0026] In addition, the formation of the fin structure may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure. These embodiments of forming fin structures are all within the scope of this invention.

[0027] Next, at least one gate structure or dummy gate is formed on each fin structure, such as the first gate structure 28 and the second gate structure 30. In this embodiment, the first gate structure 28 and the second gate structure 30 can be fabricated according to the manufacturing process requirements, such as a gate-first fabrication process, a high-k-first fabrication process for the gate-last fabrication process, or a high-k-last fabrication process for the gate-last fabrication process. Taking the high dielectric constant dielectric layer fabrication process of this embodiment as an example, a gate dielectric layer or dielectric layer, a gate material layer composed of polysilicon, and a selective hard mask can be sequentially formed on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the gate material layer and part of the gate dielectric layer are removed. Then, the patterned photoresist is stripped to form a first gate structure 28 and a second gate structure 30 composed of a patterned dielectric layer 32 and a patterned gate material layer 34 on the first fin structure 18 and the second fin structure 20.

[0028] Then, at least one spacer wall 36 is formed on the sidewalls of the first gate structure 28 and the second gate structure 30, respectively. Next, a source / drain region 38 and / or an epitaxial layer (not shown) are formed in the fin-like structures and / or the substrate 12 on both sides of the spacer wall 36, and a metal silicide (not shown) is selectively formed on the surface of the source / drain region 38 and / or the epitaxial layer. In this embodiment, the spacer wall 36 can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain region 38 may contain different dopants depending on the conductivity type of the transistor being disposed, for example, it may contain P-type dopants or N-type dopants.

[0029] Next, a contact hole etch stop layer 40 is formed on the surface of the fin structure and on the first gate structure 28 and the second gate structure 30. Then, an interlayer dielectric layer 42 is formed on the contact hole etch stop layer 40. Then, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 42 and part of the contact hole etch stop layer 40 and expose the gate material layer 34 made of polysilicon, so that the upper surface of each gate material layer 34 is flush with the upper surface of the interlayer dielectric layer 42.

[0030] Subsequently, a metal gate replacement fabrication process is performed to convert the first gate structure 28 and the second gate structure 30 into metal gates. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 34 and even the dielectric layer 32 in the first gate structure 28 and the second gate structure 30, so as to form a groove 60 in the interlayer dielectric layer 42.

[0031] Please refer to the following: Figures 4 to 6 , Figures 4 to 6 This is a continuation of an embodiment of the present invention. Figure 3 A schematic diagram illustrating a method for fabricating semiconductor devices. (Example) Figure 4 As shown, a patterned mask 44 is then formed on the second region 16, including an interlayer dielectric layer 42 covering the second region 16 and a first dielectric layer 32, exposing the first fin structure 18 of the first region 14 and a shallow trench isolation 22. Then, an etching process is performed using the patterned mask 44 as a mask to remove the dielectric layer 32 of the first region 14 and expose the upper half 24 of the first fin structure 18.

[0032] Then as Figure 5 As shown, the patterned mask 44 of the second region 16 is first completely removed. Then, without forming a patterned mask, a processing step is performed to enlarge the top of the first fin structure 18, thereby making the upper surface of the upper half 24 of the first fin structure 18 different from the upper surface of the upper half 24 of the second fin structure 20. More specifically, the processing step performed in this stage preferably includes an epitaxial growth process to form a semiconductor layer 46 on the first fin structure 18. The semiconductor layer 46 and the first fin structure 18 preferably contain the same material, so the formed semiconductor layer 46 is preferably integrated with the original first fin structure 18 to form the new upper half 24 of the first fin structure 18. In this embodiment, both the semiconductor layer 46 and the first fin structure 18 are preferably made of silicon, but are not limited to this. The semiconductor layer 46 and the first fin structure 18 can be made of different materials according to the manufacturing process requirements, and both the semiconductor layer 46 and the first fin structure 18 can be freely selected from the group consisting of, for example, silicon, germanium, silicon germanide, and silicon phosphide.

[0033] It should be noted that, since the upper half 24 of the second fin structure 20 in the second region 16 is covered by the dielectric layer 32 before the processing, the semiconductor layer 46 will only be formed on the upper half 24 of the first fin structure 18 in the first region 14 and not on the upper half 24 of the second fin structure 20 in the second region 16. Compared to the original Figure 3 The upper half 24 of the first fin-like structure 18 and the upper half 24 of the second fin-like structure 20 have the same height and width. Figure 5 The newly formed upper half 24 of the first fin structure 18 preferably has a different height and width than the upper half 24 of the second fin structure 20.

[0034] Looking at the details, for example Figure 6 As shown, the lower surface of the upper half 24 of the new first region 14 is preferably larger than the upper surface of the lower half 26 of the first region 14, the lower surface of the upper half 24 of the second region 16 is preferably smaller than the upper surface of the lower half 26 of the second region 16, both the upper and lower surfaces of the upper half 24 of the first region 14 are preferably larger than the upper and lower surfaces of the upper half 24 of the second region 16, and the upper surface of the lower half 26 of the first region 14 is preferably equal to the upper surface of the lower half 26 of the second region 16. In other words, only the surface area of ​​the channel region traversed by the gate of the first fin structure 18 in the first region 14 increases, thereby increasing the channel width, while the surface area and channel width of the channel region traversed by the gate of the second fin structure 20 in the second region 16 remain unchanged.

[0035] like Figure 6As shown, another dielectric layer 48 is subsequently formed on the first fin structure 18 and the second fin structure 20. Then, a high-dielectric-constant dielectric layer 50, a work function metal layer 52, and a low-impedance metal layer 54 are sequentially formed within the groove 60. A planarization process is then performed, for example, by using CMP to remove a portion of the low-impedance metal layer 54, a portion of the work function metal layer 52, and a portion of the high-dielectric-constant dielectric layer 50 to form the first metal gate 56 and the second metal gate 58. Taking the gate structure fabricated using the high-dielectric-constant dielectric layer fabrication process in this embodiment as an example, the first metal gate 56 preferably includes a dielectric layer 48 or a gate dielectric layer, a U-shaped high-dielectric-constant dielectric layer 50, a U-shaped work function metal layer 52, and a low-impedance metal layer 54. The second metal gate 58 includes a dielectric layer 32, another dielectric layer 48, a U-shaped high-dielectric-constant dielectric layer 50, a U-shaped work function metal layer 52, and a low-impedance metal layer 54.

[0036] In this embodiment, the high dielectric constant dielectric layer 50 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0037] The work function metal layer 52 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low impedance metal layer 54. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The low impedance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof.

[0038] In summary, this invention primarily involves first forming fin-like structures in the core region and input / output regions on a semiconductor substrate, then forming a patterned mask to cover the input / output regions, followed by a fabrication process, such as epitaxial growth, to form a semiconductor layer on the fin-like structures in the core region. This increases the local critical dimension of the same fin-like structure in the core region and increases the channel width. Since the fin-like structures in the input / output regions are masked by the patterned mask during the semiconductor layer formation process, the critical dimension of the fin-like structures in the input / output regions remains unchanged even after the critical dimension of the fin-like structures in the core region increases.

[0039] Generally, since the core area components usually require a larger critical size to increase the capacity of the channel area, while the input / output area requires a smaller critical size to improve the short channel effect (SCE), the present invention, based on this manufacturing method, can expand the critical size of the fin structure in the core area while maintaining the critical size of the fin structure in the input / output area, thereby simultaneously meeting the needs of the above two areas and improving the overall performance of the component.

[0040] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate having a first region and a second region; A first fin-like structure is formed in the first region and a second fin-like structure is formed in the second region; A first gate structure is formed on the first fin structure and a second gate structure is formed on the second fin structure, wherein the first gate structure and the second gate structure each include a first dielectric layer and a gate material layer stacked sequentially. During the formation of the first dielectric layer, a portion of the first fin structure and a portion of the second fin structure are consumed, resulting in different widths at the top and bottom. After removing the gate material layer, a patterned mask is formed in the second region; A processing technique is used to enlarge the first fin structure, thereby making the upper surface of the first fin structure different from the upper surface of the second fin structure; as well as The first gate structure and the second gate structure are converted into a first metal gate and a second metal gate.

2. The method of claim 1, further comprising: The first dielectric layer is formed on the first fin structure and the second fin structure; The patterned mask is formed on the first dielectric layer in the second region; Remove the first dielectric layer in the first region; Remove the patterned mask from the second region; and A second medium layer is formed on the first fin structure and the second fin structure.

3. The method of claim 1, further comprising: A dielectric layer is formed around the first gate structure and the second gate structure; Remove the first gate structure and the second gate structure to form a first recess and a second recess; and After the first groove and the second groove are formed, the patterned mask is formed on the first dielectric layer of the second region.

4. The method of claim 1, wherein each of the first fin-like structures and the second fin-like structure comprises an upper half and a lower half, the method comprising: A shallow groove is formed to isolate the first fin structure and the lower half of the second fin structure.

5. The method of claim 4, wherein the lower surface of the upper half of the first region and the upper surface of the lower half of the second region are flush with the upper surface isolated by the shallow groove.

6. The method of claim 4, wherein the lower surface of the upper half of the first region is greater than the upper surface of the lower half of the first region.

7. The method of claim 4, wherein the lower surface of the upper half of the second region is smaller than the upper surface of the lower half of the second region.

8. The method of claim 1, wherein the lower surface of the first fin structure is equal to the lower surface of the second fin structure.

9. The method of claim 1, wherein the processing fabrication process includes performing an epitaxial growth fabrication process to form a semiconductor layer on the first fin structure.

10. The method of claim 9, wherein the semiconductor layer and the first fin structure comprise the same material.

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