A power supply structure for integrated chip systems

Abstract

This invention relates to the field of semiconductor technology, specifically a power supply structure for integrated chip systems. The structure includes a power management system, an interposer, and an integrated chip system. The interposer includes a substrate layer, an RDL layer, and a vertical connection structure that penetrates the interposer. Interconnects are disposed at the top and bottom ends of the vertical connection structure. The power management system is connected to the upper end of the vertical connection structure via the interconnects, and the integrated chip system is connected to the lower end of the vertical connection structure via the interconnects. This structure, through 2.5D interposer technology, achieves high-density interconnection between the power management system and the integrated chip system, meeting the power supply voltage requirements of the integrated chip system, and achieving small package size and high-quality electrical signal transmission.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a power supply structure for integrated chip systems. Background Technology

[0002] Currently, with the ever-increasing demands for computing speed from artificial intelligence, integrated chips have become an effective solution to improve chip computing power. In chip manufacturing processes, the maximum area (reticlesize) that an advanced lithography machine can support in a single exposure is 3.3cm × 2.6cm. This maximum area exposure will form at least one device design (die). Chips with an area larger than 3.3cm × 2.6cm contain multiple dies; therefore, such chips are called integrated chips. Integrated chips can simultaneously implement the functions of multiple dies and reduce the limitations of inter-die communication bandwidth, thereby achieving bandwidth improvement.

[0003] A chip assembly consisting of multiple logic chips packaged on the same substrate exhibits a similar structure and function to the integrated chips described above. Therefore, this invention refers to these two structures as integrated chip systems, such as... Figure 1 As shown; for ease of explanation, this invention refers to the repetitive unit of an integrated chip system as a Tile. For an integrated chip, one die in the chip is one Tile; for a chip assembly, one chip in the assembly is one Tile.

[0004] References: Designing a 2048-Chiplet, 14336-Core Waferscale Processor. Integrated chip systems mainly employ two power supply schemes: horizontal and vertical. The horizontal power supply scheme uses a DC-DC buck converter as the power management module, placing it horizontally adjacent to the integrated chip system. Electrical signals enter through the power pins around the integrated chip system and are then transmitted to the individual tiles on the chip system via on-chip power traces. The vertical power supply scheme uses a power management module based on an LDO circuit, placing it on the integrated chip system. Electrical signals directly enter the power pins of each tile vertically. The advantages of the vertical power supply method compared to the horizontal power supply method include:

[0005] (1) Avoid using large-area off-chip components such as inductors and capacitors in DC-DC buck converters, thus saving package area;

[0006] (2) The PDN impedance generated by the on-chip power supply traces can cause a significant difference in IR-Drop between the tiles located at the edge of the chip system and the tiles located at the center, which may lead to timing and signal integrity issues in multi-tile systems. Vertical power supply can avoid this. Therefore, using on-chip LDO chips for vertical power supply of integrated chip systems has become the mainstream power supply solution.

[0007] like Figure 2 As shown, using through-silicon via (TSV) technology to power multiple LDO chips to an integrated chip system is one possible solution. However, the fabrication process of TSVs is complex, which will significantly increase the chip packaging cost. Interposer technology in 2.5DIC designs can avoid the use of TSVs. For example... Figure 3 As shown, the interposer technology places LDO chips 102, 103, and 104 horizontally side-by-side on top of interposer 109, while integrated chip 105 is located at the bottom of the interposer. Each LDO chip and integrated chip 105 is interconnected via a vertical structure 107 in interposer 109, thereby supplying power to each tile within the integrated chip. The interposer can be made of materials other than silicon, thus avoiding the use of TSVs and significantly reducing costs.

[0008] Currently, the main difficulty in designing PDN using interposer technology for integrated chips lies in the design complexity of LDO chips. For example... Figure 3 As shown, the interposer layer 109 includes a redistribution layer (RDL layer). The RDL layer is used to transmit the voltage provided by the DC power supply and the ground signal from both sides of the interposer layer to each LDO chip, forming a global PDN for the structure. The metal trace lengths of each LDO chip in the global PDN are different, resulting in different trace voltage drops and thus differences in the input voltage of each LDO chip. However, in homogeneous integrated chip scenarios, each tile is required to have the same voltage input. Therefore, each LDO chip needs to output the same voltage even with significant differences in input voltage, which increases the difficulty of LDO design. Based on this, how to design and control the global PDN to reduce the design complexity of LDO chips has become a key aspect of PDN design in integrated chip systems. Summary of the Invention

[0009] The purpose of this invention is to overcome the problems of the prior art and provide a power supply structure for integrated chip systems. This power supply structure can not only effectively reduce the power supply cost in integrated chip system scenarios, but also achieve the same voltage drop for each power management module in the power management system, thereby reducing the design complexity of the power management system.

[0010] The above objectives are achieved through the following technical solutions:

[0011] A power supply structure for an integrated chip system includes a power management system, an interposer layer, and an integrated chip system. The interposer layer includes a substrate layer, an RDL layer, and a vertical connection structure that can penetrate the interposer layer vertically. Interconnects are respectively provided at the upper and lower ends of the vertical connection structure. The power management system is connected to the upper end of the vertical connection structure through the interconnects, and the integrated chip system is connected to the lower end of the vertical connection structure through the interconnects.

[0012] Furthermore, the RDL layer is formed by sequentially laying multiple metal layers and insulating dielectric layers between adjacent metal layers, constituting a typical "metal-dielectric-metal" capacitor structure; metal traces are provided on the metal layers, and conductive vias are provided in the insulating dielectric layers, with the conductive vias connecting the metal traces on adjacent metal layers.

[0013] The substrate layer is disposed below the RDL layer and is used to support the RDL layer and realize the connection between the RDL layer and the integrated chip system.

[0014] Furthermore, the circuit that performs voltage conversion in the power management system is an LDO circuit, which can provide a stable voltage output;

[0015] The power management system is a distributed power management chip composed of multiple LDO circuits, or a chip set composed of multiple distributed power management chips.

[0016] Furthermore, it also includes a global power supply that provides DC power, which inputs DC power along the edge of the interposer layer; the metal traces and conductive vias in the RDL layer connect the voltage supplied by the global power supply and the ground signal to the power management system, forming a global PDN of this structure; the output voltage of the power management system is transmitted to the integrated chip system through the vertical connectors in the interposer layer, forming a local PDN.

[0017] Furthermore, a plurality of conductive pads are provided on the metal layer on top of the RDL layer. The conductive pads are used to support the interconnects disposed below the power management system and to form an electrical connection.

[0018] Furthermore, the interconnect is a microbump, which is one or more of the following: copper pillar, solder ball, and controlled collapse chip connection structure.

[0019] Furthermore, the integrated chip system refers to a logic chip with a size greater than 3.3cm × 2.6cm, or a chip collection consisting of multiple logic chips packaged on the same substrate.

[0020] Furthermore, the substrate layer is a glass substrate, a ceramic substrate, or an insulating composite layer.

[0021] Furthermore, the number of metal layers in the RDL layer is at least two, the number of insulating dielectric layers is at least one, and the top and bottom of the RDL layer must be the metal layers.

[0022] Furthermore, the materials of the insulating medium include, but are not limited to, polyimide and silicon dioxide.

[0023] Beneficial effects

[0024] The power supply structure for integrated chip systems provided by this invention can achieve high-density interconnection between the power management system and the integrated chip system through 2.5D interposer technology, meet the power supply voltage requirements of the integrated chip system, and achieve the effects of small package size and high quality of electrical signal transmission. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a power supply structure for an integrated chip system according to the present invention, wherein (a) is an integrated chip; and (b) is a chip assembly.

[0026] Figure 2 A schematic diagram of a power supply structure for stacked chips provided for related technologies;

[0027] Figure 3 This is a schematic diagram of the first packaging structure of a power supply structure for an integrated chip system according to the present invention;

[0028] Figure 4 This is a schematic diagram of the second packaging structure of the power supply structure for an integrated chip system described in this invention;

[0029] Figure 5 This is a schematic diagram of a third packaging structure for a power supply structure for an integrated chip system as described in this invention;

[0030] Figure 6 This is a schematic diagram of the fourth packaging structure of the power supply structure for an integrated chip system described in this invention;

[0031] Figure 7 This is a top view of the first packaging structure of the power supply structure for an integrated chip system described in this invention.

[0032] Figure 8 This is a schematic diagram of the first structure of the intermediary layer in a power supply structure for an integrated chip system according to the present invention;

[0033] Figure 9This is a schematic diagram of the second structure of the intermediary layer in a power supply structure for an integrated chip system according to the present invention.

[0034] Explanation of Illustrated Markings

[0035] 101-First packaging structure, 102-First power management chip, 103-Second power management chip, 104-Third power management chip, 105 Integrated chip, 106-First microbump, 107-Vertical connection structure, 108-Second microbump, 109-Interposer layer, 110-RDL layer, 111-First wiring structure, 112-Second wiring structure, 113-Third wiring structure, 121-Conductive pad, 123-Conductive via, 124-Substrate layer, 201-Second packaging structure, 202-Distributed power chip, 301-Third packaging structure, 302-Logic chip, 401-Fourth packaging structure. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] like Figures 3-6 As shown, a power supply structure for an integrated chip system includes a power management system, an interposer layer 109, and an integrated chip system. The interposer layer 109 includes a substrate layer 124, an RDL layer 110, and a vertical connection structure 107 that can vertically penetrate the interposer layer 109. Interconnects are respectively provided at the upper and lower ends of the vertical connection structure 107. The power management system is connected to the upper end of the vertical connection structure 107 through the interconnects, and the integrated chip system is connected to the lower end of the vertical connection structure 107 through the interconnects.

[0038] The RDL layer 110 is formed by sequentially laying multiple metal layers and insulating dielectric layers between adjacent metal layers, forming a typical "metal-dielectric-metal" capacitor structure; metal traces are provided on the metal layers, and conductive vias 123 are provided in the insulating dielectric layers, with the conductive vias 123 connecting the metal traces on adjacent metal layers.

[0039] The substrate layer 124 is disposed below the RDL layer 110 and is used to support the RDL layer 110 and to connect the RDL layer 110 to the integrated chip system.

[0040] The interconnect is a microbump, which is one or more of the following: copper pillar, solder ball, and controlled collapse chip connection structure.

[0041] The circuit that performs voltage conversion in the power management system is a low drop-out voltage regulator (LDO), which can provide a stable voltage output.

[0042] The power management chip system refers to a distributed power management chip composed of multiple LDO circuits, or a chip set composed of multiple power management chips; for ease of expression, the repetitive units of the power management system are referred to as modules in this invention. For a distributed power management chip, one LDO circuit in the chip is a module; for a chip set, one chip in the set is a module.

[0043] The global power supply of this power supply structure is input from the edge of the intermediate layer; the metal traces and vias in the RDL layer connect the voltage supplied by the DC power supply and the ground signal to each module in the power management system, forming the global PDN of this structure; the output voltage of each module in the power management system is transmitted to each tile in the integrated chip system through the vertical connectors in the intermediate layer, forming the local PDN of each tile.

[0044] Specifically, such as Figure 3 As shown, this example provides a first packaging structure 101, wherein the integrated chip system is a single integrated chip 105, and the power management system is a chip set consisting of three power management chips, including a first power management chip 102, a second power management chip 103, and a third power management chip 104. The first power management chip 102, the second power management chip 103, and the third power management chip 104 are horizontally disposed on the upper surface of the interposer layer 109, and the integrated chip 105 is disposed on the lower surface of the interposer layer 109 as a power supply load chip. The first power management chip 102, the second power management chip 103, and the third power management chip 104 are respectively connected to the interposer layer 109 via first microbumps 106; the integrated chip 105 is connected to the interposer layer 109 via second microbumps 108. Figure 7 This is a top view of the first type of packaging structure 101.

[0045] In this example, the integrated chip 105 is configured as a homogeneous multi-tile system, meaning that the integrated chip 105 comprises three identical tiles. The first power management chip 102, the second power management chip 103, and the third power management chip 104 are modules of a power management system. Therefore, in this structure, the three modules of the power management system supply the same voltage to the three tiles of the integrated chip.

[0046] The power management chips described in this invention refer to chips capable of converting source voltage into the voltage required by the target chip. The main circuit of the power management chip is a DC-DC conversion circuit, among which LDOs and DC-DC buck converters are the most common DC-DC converters. Compared with DC-DC buck converters, LDOs can avoid excessive area occupation by external components. Therefore, the first power management chip 102, the second power management chip 103, and the third power management chip 104 in the first package structure 101 of this invention are power management chips based on LDO type circuits.

[0047] In a specific embodiment, such as Figure 4 As shown, in the second packaging structure 201, the power management system is not a collection of multiple LDO chips, but a single distributed power chip 202 composed of multiple LDO circuits. Each LDO circuit structure in the distributed power chip 202 is referred to as a module of the power management system. Similar to the first packaging structure 101, each module in the power management system supplies the same voltage to each tile of the integrated chip.

[0048] In a specific embodiment, such as Figure 5 As shown, in the third packaging structure 301, the integrated chip system is not a single integrated chip, but a chip collection composed of multiple logic chips 302 packaged on the same substrate. The logic chip 302 is a tile of the integrated chip system, and the first power management chip 102, the second power management chip 103, and the third power management chip 104 in the power management system supply the same voltage to each tile.

[0049] In a specific embodiment, such as Figure 6 As shown, in the fourth packaging structure 401, the integrated chip is a chip assembly composed of multiple logic chips 302 packaged on the same substrate, and the power management system is a single distributed power chip 202 composed of multiple LDO circuits. The logic chip 302 is a tile of the integrated chip system, and each LDO circuit structure in the power chip 202 is a module of the power management system, with each module supplying the same voltage to each tile.

[0050] It should be understood that the present invention does not limit the number of tiles in the integrated chip system and the number of modules in the power management system. Provided that the process is feasible and physical constraints and basic functions are met, the number of tiles in the integrated chip system and the number of modules in the power management system in the present invention can be any reasonable number greater than one.

[0051] This invention will address Figure 3 The structure 101 shown is described in detail. In the figure, some pins of the first power management chip 102, the second power management chip 103, and the third power management chip 104 are connected to the integrated chip 105 through the vertical connection structure 107 and the first microbump 106 and the second microbump 108 in the interposer layer 109, thereby forming an electrical path for each power management chip to supply voltage to each tile in the integrated chip 105, i.e., the local PDN of this structure.

[0052] The power supply to the first power management chip 102, the second power management chip 103, and the third power management chip 104 is completed through the RDL layer 110 in the intermediary layer 109. Therefore, the conductive structure in the RDL layer 110 is also called the global PDN.

[0053] like Figure 7 As shown, the conductive structures in RDL layer 110 include a first trace structure 111, a second trace structure 112, a third trace structure 113, and associated conductive vias. The first trace structure 111, the second trace structure 112, and the third trace structure 113 are respectively connected to power management chips (first power management chip 102, second power management chip 103, and third power management chip 104). Each of the first trace structure 111, the second trace structure 112, and the third trace structure 113 includes multiple metal traces, which transmit voltage or ground signals from the DC power supply to each of the power chips.

[0054] It should be understood that the number and wiring details in the diagram are for illustrative purposes only, indicating the connection relationships, and do not represent the actual wiring.

[0055] The first packaging structure 101 proposed in the above-described embodiment of the invention provides a PDN for the integrated chip 105 using 2.5D interposer technology and RDL technology as follows: Each of the first power management chip 102, the second power management chip 103, and the third power management chip 104 obtains the source voltage signal from the global power supply through the first routing structure 111, the second routing structure 112, and the third routing structure 113 in the RDL layer 110, respectively, and outputs the same stable voltage. The voltage is then transmitted to each tile in the target integrated chip 105 through the vertical connection structure 107 in the interposer layer 109.

[0056] like Figure 8 The diagram shows a detailed schematic of the interposer layer of the first type of packaging structure 101.

[0057] In this example, the RDL layer 110 includes two metal layers ML1 and ML2, with an insulating dielectric filling the space between them to form an insulating dielectric layer DL. The metal traces etched on the metal layers ML1 and ML2 constitute the first trace structure 111, the second trace structure 112, and the third trace structure 113; therefore, the metal layers ML1 and ML2 can also be referred to as the first wiring layer and the second wiring layer. Vertical connections between the wiring layers are achieved by conductive vias 123 in the insulating dielectric layer DL. Multiple conductive pads 121 are disposed on the top of the second wiring layer ML2. These conductive pads 121 support the first microbumps 106 of each power management chip and provide electrical connection between the first microbumps 106 and the trace structures in the second wiring layer ML2. A substrate layer 124 is disposed at the bottom of the second wiring layer ML2, and second microbumps 108 are disposed between the substrate layer 124 and the integrated chip 105.

[0058] like Figure 3 , 7 As shown in Figure 8, the trace structure 111 transmits the voltage and ground signal provided by the DC power supply to a conductive pad 121. The conductive pad 121 is connected to a first microbump 106, which is connected to a power pin of the power management chip 102, thus forming a PDN that supplies power to the power management chip 102. The power management chip 102 transmits the voltage signal to the integrated chip 105 through the first microbump 106, the vertical connection structure 107 in the interposer, and the second microbump 108, thus realizing a PDN that supplies power to the integrated chip 105. The other power management chips are similar.

[0059] It should be understood that, as long as adjacent metal layers are separated by an insulating dielectric, the present invention does not limit the stacking structure of the RDL layer. For example, in some embodiments, the RDL layer 110 of the present invention can consist of four metal layers and three insulating dielectric layers, such as... Figure 9 As shown.

[0060] In this embodiment, each power management chip is packaged using flip-chip technology, but in some possible embodiments, it can also be packaged using wire bonding or other equivalent technologies. Meanwhile, the interconnect structure between each chip and the interposer is not limited; for example, the first microbump 106 and the second microbump 108 can be replaced with one or more combinations of copper pillars, solder balls, and controlled collapse chip connection structures.

[0061] In terms of the selection of structural materials, the present invention uses a glass substrate, a ceramic substrate or a similar composite layer as the substrate layer; the conductive structure of the RDL layer 110 is composed of materials including but not limited to copper and gold, and the insulating medium is composed of materials including but not limited to polyimide and silicon dioxide.

[0062] This invention utilizes 2.5D interposer technology and RDL technology to achieve high-density interconnection between the power management system and the integrated chip system, meeting the power supply voltage requirements of the integrated chip system, and has the advantages of small package size and high electrical signal transmission quality.

[0063] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A power supply structure for integrated chip systems, characterized in that, The system includes a power management system, an interposer layer, and an integrated chip system. The interposer layer includes a substrate layer, an RDL layer, and a vertical connection structure that can penetrate the interposer layer vertically. Interconnects are respectively provided at the upper and lower ends of the vertical connection structure. The power management system is connected to the upper end of the vertical connection structure through the interconnects, and the integrated chip system is connected to the lower end of the vertical connection structure through the interconnects. The RDL layer is formed by sequentially laying multiple metal layers and insulating dielectric layers between adjacent metal layers, constituting a typical "metal-dielectric-metal" capacitor structure. Metal traces are provided on the metal layers, and conductive vias are provided in the insulating dielectric layers, with the conductive vias connecting the metal traces on adjacent metal layers. The substrate layer is disposed below the RDL layer and is used to support the RDL layer and realize the connection between the RDL layer and the integrated chip system. The circuit that performs voltage conversion in the power management system is an LDO circuit, which can provide a stable voltage output; the power management system is a distributed power management chip composed of multiple LDO circuits, or a chip collection composed of multiple distributed power management chips. It also includes a global power supply that provides DC power, which inputs DC power along the edge of the interposer layer; the metal traces and conductive vias in the RDL layer connect the voltage supplied by the global power supply and the ground signal to the power management system, forming a global PDN of this structure; the output voltage of the power management system is transmitted to the integrated chip system through the vertical connection structure in the interposer layer, forming a local PDN.

2. The power supply structure for integrated chip systems according to claim 1, characterized in that, A plurality of conductive pads are provided on the metal layer at the top of the RDL layer. The conductive pads are used to support the interconnects disposed below the power management system and to form an electrical connection.

3. The power supply structure for integrated chip systems according to claim 1, characterized in that, The interconnect is a microbump, which is one or more of the following: copper pillar, solder ball, and controlled collapse chip connection structure.

4. The power supply structure for integrated chip systems according to claim 1, characterized in that, The integrated chip system refers to a logic chip with a size greater than 3.3cm × 2.6cm, or a chip collection consisting of multiple logic chips packaged on the same substrate.

5. A power supply structure for integrated chip systems according to claim 1, characterized in that, The substrate layer is a glass substrate, a ceramic substrate, or an insulating composite layer.

6. The power supply structure for integrated chip systems according to claim 1, characterized in that, The RDL layer has at least two metal layers and at least one insulating dielectric layer, and the top and bottom of the RDL layer must be the metal layers.

7. A power supply structure for integrated chip systems according to claim 6, characterized in that, The insulating medium is made of polyimide and silicon dioxide.

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