A multi-step multi-channel trench MOSFET device and its preparation method

Abstract

The present invention provides a multi-step multi-channel trench MOSFET device and a preparation method thereof, wherein the design of the n-step trench can increase the channel path of the unit trench cell and improve the channel density on the basis of ensuring gate oxide reliability and reverse breakdown; adjacent P+ injections are not at the same horizontal position, that is, the first doping region, the second doping region and the third doping region are not at the same horizontal position, which effectively reduces the JFET effect of adjacent P+ regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor and improves the current density per unit area; the low JFET effect reduces the on-resistance change under small current and large current; on the other hand, a Schottky diode is connected in anti-parallel near the source electrode, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the integration of the chip, and reduce the production cost of the MOSFET device with integrated Schottky diode.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more particularly to a multi-step multi-channel trench MOSFET device and a preparation method thereof. Background Art

[0002] Silicon carbide (chemical formula SiC) material has advantages in physical properties such as large band gap, high breakdown electric field, fast electron mobility, and high thermal conductivity. These characteristics make silicon carbide very suitable for high temperature, high pressure, high frequency and radiation-resistant environments.

[0003] SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a unipolar voltage-controlled device that is mainly used in power supplies and power processing systems to control power conversion. Compared with traditional Si-based power devices, SiC devices are easier to achieve high voltage, low loss and high power density, and therefore have gradually become the mainstream of the market.

[0004] Currently, an important factor limiting the cost reduction and further improvement of MOSFET devices is how to reduce their on-resistance (on-resistance per unit chip area); in order to reduce the on-resistance, trench MOSFET has become a hot spot in current research and development; compared with the low channel mobility of planar MOSFET cells on the (0001) plane, the channel of the trench MOSFET is on the crystal plane perpendicular to the (0001) plane, generally on the (11-20) plane. The electron mobility near the channel on this crystal plane is significantly higher than that on the (0001) plane, and the size of the channel cell can be made smaller, so the trench MOSFET device has a lower specific on-resistance and a higher current density.

[0005] However, in trench MOSFET structures, electric field concentration is generally prone to form at the bottom of the gate trench. Since the gate oxide material is generally SiO2, whose dielectric constant is 3.9, while the dielectric constant of SiC is 9.7, the electric field in SiO2 at the gate oxide interface is 2.5 times that of SiC, and the critical electric field of SiC is 10 times that of Si. Therefore, when the device is subjected to high voltage, the gate oxide layer at the bottom of the gate trench of the SiC device is prone to reliability issues. Therefore, how to alleviate or avoid the electric field concentration at the bottom of the gate trench is a hot topic of current research.

[0006] In order to alleviate the electric field concentration at the bottom of the gate trench, P-type dopant ions are usually injected into the bottom of the gate trench or into the bottom of the source trench of the gate and source double trench structure (that is, the gate and source of the trench MOSFET are in two separate trenches); the injection of P-type dopant ions into the bottom of the gate trench will increase the JFET effect of the adjacent P+ region. Since the reduction in the spacing of the P+ injections is synchronized with the increase in the channel density, while reducing the channel resistance, it will also greatly increase the JFET resistance near the adjacent P+ region, resulting in blockage of the current path near the bottom of the gate trench; the double trench structure formed by the gate and source will significantly increase the cell size, and the JFET effect between adjacent P+ injections will be obvious, the on-resistance will increase, the current density will decrease, and the bottom of the source trench is far away from the bottom of the gate trench, making it difficult to significantly alleviate the electric field concentration at the bottom of the gate trench.

[0007] In addition, in practical applications, transistors often need to be connected in anti-parallel with a freewheeling diode, which increases both cost and volume. If a Schottky diode is integrated within the device cell, the chip's integration can be improved. However, currently, integrating a diode within the device generally significantly increases the cell size, resulting in an increase in the on-resistance and a decrease in the current density.

[0008] In addition, under current process conditions, the P-type ohmic contact resistance of silicon carbide is significantly higher than the N-type ohmic contact resistance by 1-2 orders of magnitude. In order to reduce the P-type ohmic contact resistance, it is often achieved by increasing the P-type ohmic contact area, but this will increase the cell size. Summary of the Invention

[0009] In view of this, in order to solve the above problems, the present invention provides a multi-step multi-channel trench MOSFET device and a preparation method thereof, and the technical solution is as follows:

[0010] A multi-step multi-channel trench MOSFET device, the trench MOSFET device comprising:

[0011] substrate;

[0012] In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially located on one side of the substrate; the current spreading layer has n-level stepped trenches on a side facing away from the substrate, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate and points from the substrate to the current spreading layer;

[0013] The trench MOSFET device further includes a gate and a source, the gate being located in the first, ..., and m-th stepped trenches, and the source being located in the m+1, m+2, ..., and n-th stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first-level stepped trench and a second gate portion located in the second-level stepped trench, a sidewall of the first-level stepped trench adjacent to the first gate portion having a first doped region, and a sidewall of the second-level stepped trench adjacent to the second gate portion having a second doped region, and the structure of the first gate portion is the same as that of the second gate portion;

[0014] a source electrode located in the other level stepped trenches, and a third doped region located in the bottom region of the n level stepped trench;

[0015] The first doping region, the second doping region and the third doping region have the same doping type.

[0016] Preferably, in the above trench MOSFET device, the sidewall of the first-level stepped trench adjacent to the first gate portion further has a fourth doped region and a fifth doped region;

[0017] The fourth doping region and the fifth doping region are located between the first doping region and the first gate portion, and the fourth doping region and the fifth doping region are arranged sequentially in the first direction;

[0018] The sidewall of the second-level stepped trench adjacent to the second gate portion further has a sixth doped region and a seventh doped region;

[0019] The sixth doping region and the seventh doping region are located between the second doping region and the second gate portion, and the sixth doping region and the seventh doping region are sequentially arranged in the first direction.

[0020] Preferably, in the above trench MOSFET device, the trench MOSFET device further comprises:

[0021] An eighth doped region is located on a sidewall away from the second gate portion.

[0022] Preferably, in the above trench MOSFET device, the third doped region is located at the bottom of the n-level stepped trench and also extends to both sidewalls of other-level stepped trenches;

[0023] The trench MOSFET device further comprises:

[0024] An ohmic contact layer is located at the bottom of the other level stepped trench and extends to the sidewalls of the other level stepped trench and the sidewalls of the eighth doped region.

[0025] Preferably, in the above trench MOSFET device, the third doped region is located at the bottom of the n-level stepped trench and also extends to a sidewall of another level stepped trench adjacent to the second gate portion;

[0026] The trench MOSFET device further includes: an ohmic contact layer and a Schottky contact layer;

[0027] The ohmic contact layer is located at the bottom of the other stepped trench and extends to a side wall of the other stepped trench adjacent to the second gate portion; the Schottky contact layer is located on a side wall of the other stepped trench away from the second gate portion.

[0028] Preferably, in the above trench MOSFET device, a sidewall of the n-level stepped trench away from the second gate portion is a step structure;

[0029] The Schottky contact layer also extends to the surface of the stepped structure.

[0030] Preferably, in the above trench MOSFET device, the trench MOSFET device has a symmetrical structure based on the n-th level stepped trench.

[0031] Preferably, in the above trench MOSFET device, the third doped region is located at the bottom of the n-level stepped trench and also extends to both sidewalls of the other-level stepped trenches; the trench MOSFET device further comprises: an ohmic contact layer, the ohmic contact layer is located at the bottom of the other-level stepped trenches and extends to the sidewalls of the other-level stepped trenches;

[0032] or,

[0033] The third doped region is located on both sidewalls of the other level stepped trenches;

[0034] The trench MOSFET device further includes an ohmic contact layer and a Schottky contact layer, wherein the ohmic contact layer is located on the sidewalls of the other-level stepped trench, and the Schottky contact layer is located at the bottom of the other-level stepped trench.

[0035] Preferably, in the above trench MOSFET device, the trench MOSFET device further comprises:

[0036] a doped region located on a side of the second doped region away from the second gate portion, and a doped region located on a side of the other level stepped trench adjacent to the second gate portion;

[0037] The doping region includes a ninth doping region and a tenth doping region, and the tenth doping region is at least partially arranged to surround the ninth doping region.

[0038] A method for preparing a multi-step multi-channel trench MOSFET device, used to prepare any of the trench MOSFET devices described above, the preparation method comprising:

[0039] providing a substrate;

[0040] In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; a side of the current spreading layer facing away from the substrate has n-level stepped trenches, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate and points from the substrate to the current spreading layer;

[0041] Prepare a subsequent structure, which includes a gate and a source, the gate being located in the first, ..., mth stepped trenches, and the source being located in the m+1th, m+2th, ..., nth stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first stepped trench and a second gate portion located in the second stepped trench, a sidewall of the first stepped trench adjacent to the first gate portion having a first doped region, a sidewall of the second stepped trench adjacent to the second gate portion having a first doped region, and a structure of the first gate portion being the same as a structure of the second gate portion; a source being located in the other stepped trenches, and a third doped region being located in the bottom area of ​​the nth stepped trench; wherein the first doped region, the second doped region, and the third doped region have the same doping type.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The design of the n-level stepped trench in a trench MOSFET device provided by the present invention can increase the channel path of a unit trench cell and improve the channel density while ensuring gate oxide reliability and reverse breakdown. Adjacent P+ injections are not at the same horizontal position, that is, the first doping region, the second doping region, and the third doping region are not at the same horizontal position, which effectively reduces the JFET effect of adjacent P+ regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor, and improves the current density per unit area. The low JFET effect can reduce the change in on-resistance under low and high currents. On the other hand, a Schottky diode is connected in anti-parallel near the source, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the integration of the chip, and reduce the production cost of the MOSFET device with integrated Schottky diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0045] Figure 1 A schematic structural diagram of a multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0046] Figure 2 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0047] Figure 3 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0048] Figure 4 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0049] Figure 5 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0050] Figure 6 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0051] Figure 7 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0052] Figure 8 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0053] Figure 9 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0054] Figure 10 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0055] Figure 11 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0056] Figure 12 A schematic flow chart of a method for manufacturing a multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention;

[0057] Figure 13-Figure 17 for Figure 12 Schematic diagram of part of the structure corresponding to the preparation method shown. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] Based on the content described in the background technology, a novel multi-step multi-channel trench MOSFET device and a preparation method thereof are provided in an embodiment of the present invention. On the one hand, the multi-step multi-channel trench MOSFET device can increase the channel path of the unit trench cell and improve the channel density on the basis of ensuring gate oxide reliability and reverse breakdown, thereby forming a multi-step multi-channel trench MOSFET device. Adjacent P+ injections are not at the same horizontal position, which spatially separates the mutual influence between adjacent P+ injections, effectively reduces the JFET effect of adjacent P+ regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor, and improves the current density per unit area. The low ET effect reduces the change in on-resistance under small and large currents; on the other hand, a Schottky diode is connected in anti-parallel near the source of the cell structure, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the integration of the chip, and reduce the production cost of MOSFET devices with integrated Schottky diodes; in addition, the multi-step trench sidewalls and bottom of the new multi-step multi-channel trench MOSFET device provided by the embodiment of the present invention are both provided with P-type ohmic contacts connected to the source, which increases the source P-type ohmic contact area while keeping the cell size unchanged, effectively improving the P-type contact resistance, and significantly reducing the diode voltage drop under large reverse freewheeling current.

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] refer to Figure 1 , Figure 1 A schematic structural diagram of a multi-step multi-channel trench MOSFET device provided in an embodiment of the present invention, wherein the trench MOSFET device includes: a substrate 1.

[0062] In a first direction, the buffer layer 2, the epitaxial layer 3 and the current spreading layer 4 are sequentially located on one side of the substrate 1; the current spreading layer 4 has n-level stepped trenches on a side facing away from the substrate 1, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate 1 and points from the substrate 1 to the current spreading layer 4.

[0063] The trench MOSFET device also includes a gate and a source, the gate is located in the first, ..., mth stepped trenches, and the source is located in the m+1th, m+2th, ..., nth stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first stepped trench and a second gate portion located in the second stepped trench, the sidewall of the first stepped trench adjacent to the first gate portion has a first doped region 5, and the sidewall of the second stepped trench adjacent to the second gate portion has a second doped region 6, and the structure of the first gate portion is the same as that of the second gate portion.

[0064] A source electrode 7 is located in the other level stepped trenches, and a third doped region 8 is located in the bottom region of the n level stepped trench.

[0065] The first doping region 5 , the second doping region 6 and the third doping region 8 have the same doping type.

[0066] Specifically, in the embodiment of the present invention, the substrate 1 is an N-type doped SiC substrate with a doping concentration of 1E18-5E19 cm -3 , with a thickness of 80-400 μm. It can be understood that the area where the N-type doped substrate is located is a high-doping area of ​​N-type doping type; the buffer layer 2 is an N-type doped SiC buffer layer with a doping concentration of 7E17-3E18 cm -3 The thickness is about 1 μm, which can be understood as the area where the N-type doped buffer layer is located is a high-doped area of ​​N-type doping type; the epitaxial layer 3 is an N-type doped SiC epitaxial layer with a doping concentration of 1E15-8E16 cm -3 , with a thickness of 4-100 μm. It can be understood that the area where the N-type doped epitaxial layer is located is an N-type doped low-doped area; the current spreading layer 4 is an N-type doped current spreading layer with a doping concentration of 1E15-1E18 cm -3 , depth is 0.3um-5um.

[0067] The first doped region 5 is a P-type first doped region with a doping concentration of 1E17-8E20 cm -3 , with a depth of 0.3-2.0um; the second doped region 6 is a P-type second doped region with a doping concentration of 1E17-8E20cm -3, with a depth of 0.3-2.0um; the third doped region 8 is a P-type third doped region with a doping concentration of 1E16-5E20 cm -3 , with a depth of 0.2-1.5um; that is, the first doped region 5, the second doped region 6 and the third doped region 8 are all high-doped regions of the P-type doping type, ie, P+ regions.

[0068] The first gate portion and the second gate portion have the same structure, both including a gate oxide layer 9, a gate 10 and an isolation dielectric layer 11; wherein the gate oxide layer 9 covers the bottom and sidewalls of the stepped trench at the same level, the gate 10 is located on the gate oxide layer 9, and the isolation dielectric layer 11 covers the surface of the gate 10 facing away from the substrate 1, as well as covers one sidewall of the gate 10, thereby playing the role of gate-source isolation.

[0069] By processing the current spreading layer 4 to form an n-level stepped trench, the gate structure and the source are both inside the same trench, which can reduce the cell size, and inject a P-type doping type well into the n-level stepped trench, and then form an ohmic contact layer and a Schottky contact layer in the well, and then continue to form other structures required subsequently.

[0070] The gate oxide layer 9 includes but is not limited to a gate oxide layer made of silicon dioxide material, the gate 10 includes but is not limited to a gate made of metal material or polycrystalline material, and the source electrode 7 includes but is not limited to a source electrode made of metal material.

[0071] It should be noted that the trench MOSFET device further includes a drain electrode 0 located on a side of the substrate 1 away from the buffer layer 2 . The drain electrode 0 includes but is not limited to a drain electrode made of a metal material.

[0072] Optionally, in another embodiment of the present invention, as Figure 1 As shown, the sidewall of the first-level stepped trench adjacent to the first gate portion further has a fourth doping region 12 and a fifth doping region 13 .

[0073] The fourth doping region 12 and the fifth doping region 13 are located between the first doping region 5 and the first gate portion, and the fourth doping region 12 and the fifth doping region 13 are sequentially arranged in the first direction.

[0074] The sidewall of the second-level stepped trench adjacent to the second gate portion further has a sixth doping region 14 and a seventh doping region 15 .

[0075] The sixth doping region 14 and the seventh doping region 15 are located between the second doping region 6 and the second gate portion, and the sixth doping region 14 and the seventh doping region 15 are sequentially arranged in the first direction.

[0076] Specifically, in the embodiment of the present invention, the fourth doping region 12 and the sixth doping region 14 are both low-doping regions of P-type doping type, with a doping concentration of 1E16-1E18 cm -3 , with a depth of 0.2-2.0 μm; the fifth doping region 13 and the seventh doping region 15 are both N-type high-doping regions with a doping concentration of 1E18-5E20 cm -3 , depth is 0.1-0.5um.

[0077] Optionally, in another embodiment of the present invention, as Figure 1 As shown, the trench MOSFET device further includes:

[0078] An eighth doped region 16 is located on a sidewall away from the second gate portion.

[0079] Specifically, in the embodiment of the present invention, the eighth doping region 16 is a high-doping region of P-type doping type, and the doping concentration is 1E17-8E20 cm -3 , depth is 0.3-2.0um.

[0080] Optionally, in another embodiment of the present invention, as Figure 1 As shown, the third doped region 8 is located at the bottom of the n-level stepped trench and also extends to both sidewalls of the other-level stepped trenches.

[0081] The trench MOSFET device further comprises:

[0082] The ohmic contact layer 17 is located at the bottom of the other-level stepped trench and extends to the sidewalls of the other-level stepped trench and the sidewalls of the eighth doped region 16 .

[0083] Specifically, in the embodiment of the present invention, a three-level stepped trench is taken as an example for explanation. The design of the n-level stepped trench in the trench MOSFET device can increase the channel path of the unit trench cell and improve the channel density on the basis of ensuring gate oxide reliability and reverse breakdown. Adjacent P+ injections are not at the same horizontal position, that is, the first doping region 5, the second doping region 6 and the third doping region 8 are not at the same horizontal position, which effectively reduces the JFET effect of adjacent P+ regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor, and improves the current density per unit area. The low JFET effect can reduce the on-resistance change under small current and large current.

[0084] Optionally, in another embodiment of the present invention, referring to Figure 2 , Figure 2A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the third doped region 8 is located at the bottom of the n-level stepped trench and also extends to a sidewall of the other-level stepped trench adjacent to the second gate portion.

[0085] The trench MOSFET device further includes an ohmic contact layer 17 and a Schottky contact layer 18 .

[0086] The ohmic contact layer 17 is located at the bottom of the other stepped trench and extends to a sidewall of the other stepped trench adjacent to the second gate portion; the Schottky contact layer 18 is located on a sidewall of the other stepped trench away from the second gate portion.

[0087] Specifically, in the embodiment of the present invention, a three-level stepped trench is taken as an example to illustrate, a Schottky contact layer 18 is formed on the side wall of the other level stepped trench away from the second gate portion, and the bottom of the other level stepped trench and the other remaining side walls are injected with highly doped ions of the P-type doping type by inclined injection, so that an ohmic contact layer 17 is formed in the contact area between the source and the highly doped ions of the P-type doping type.

[0088] That is to say, Figure 2 The structure of the trench MOSFET device shown is Figure 1 The structure of the trench MOSFET device shown is improved by increasing the Schottky contact area so that the Schottky diode is integrated into the trench MOSFET device cell, effectively improving its reverse freewheeling capability.

[0089] Optionally, in another embodiment of the present invention, referring to Figure 3 , Figure 3 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the sidewall of the n-level stepped trench away from the second gate portion is a step structure.

[0090] The Schottky contact layer 18 also extends to the surface of the stepped structure.

[0091] Specifically, in the embodiment of the present invention, a three-level stepped trench is used as an example to illustrate that a large-area Schottky contact layer 18 is formed on the side wall of the n-level stepped trench away from the second gate portion. Figure 2 The structure of the trench MOSFET device shown greatly increases the Schottky contact area, further improving its reverse freewheeling capability.

[0092] Similarly, the bottom of other level stepped trenches and other remaining sidewalls are implanted with P-type highly doped ions by tilted implantation, so that the source and the P-type highly doped ion contact area form an ohmic contact layer 17.

[0093] Optionally, in another embodiment of the present invention, referring to Figure 4 , Figure 4 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the stepped trench where the source 7 is located is a multi-step trench.

[0094] Specifically, in the embodiment of the present invention, a four-level stepped trench is used as an example for description, that is, the stepped trenches where the source 7 is located are the third-level stepped trench and the fourth-level stepped trench. In other words, Figure 4 The structure of the trench MOSFET device shown is Figure 1 The structure of the trench MOSFET device shown is improved by making the source 7 part into a multi-level stepped trench, so that the stepped trench where the source 7 is located can be deep enough, so that the high-concentration doped ions of the P-type doping type at the bottom of the stepped trench where the source 7 is located can be implanted deeper, thereby better protecting the gate oxide layer 9.

[0095] Optionally, in another embodiment of the present invention, referring to Figure 5 , Figure 5 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the stepped trench where the source 7 is located is a multi-step trench.

[0096] Specifically, in the embodiment of the present invention, a four-level stepped trench is used as an example for description, that is, the stepped trenches where the source 7 is located are the third-level stepped trench and the fourth-level stepped trench. In other words, Figure 5 The structure of the trench MOSFET device shown is Figure 2 The structure of the trench MOSFET device shown is improved by making the source 7 part into a multi-level stepped trench, so that the stepped trench where the source 7 is located can be deep enough, so that the high-concentration doped ions of the P-type doping type at the bottom of the stepped trench where the source 7 is located can be implanted deeper, thereby better protecting the gate oxide layer 9.

[0097] And compared Figure 4 The structure of the trench MOSFET device shown increases the Schottky contact area, so that the trench MOSFET device cell integrates a Schottky diode, effectively improving its reverse freewheeling capability.

[0098] Optionally, in another embodiment of the present invention, referring to Figure 6 , Figure 6A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the trench MOSFET device has a symmetrical structure based on the n-th level stepped trench.

[0099] The third doped region 8 is located at the bottom of the n-level stepped trench and also extends to the sidewalls of the other-level stepped trenches. The trench MOSFET device also includes: an ohmic contact layer 17, which is located at the bottom of the other-level stepped trenches and extends to the sidewalls of the other-level stepped trenches.

[0100] Specifically, in the embodiment of the present invention, a three-level stepped groove is used as an example for description. Figure 6 The structure of the trench MOSFET device shown is Figure 1 The structure of the trench MOSFET device shown is improved so that it has a symmetrical structure based on the n-th level stepped trench, that is, the stepped trenches where the gate parts on the left and right sides are located share a stepped trench where the source 7 is located, which can effectively increase the vertical channel path, improve the current density of the trench MOSFET device, and reduce the specific on-resistance. In addition, the stepped trench where the source is located is deep enough to effectively shield the electric field strength near the gate oxide layer 9, thereby ensuring the gate oxide reliability of the device.

[0101] Likewise, reference Figure 7 , Figure 7 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 7 As shown, the stepped trench where the source 7 is located is a multi-step trench.

[0102] Specifically, in the embodiment of the present invention, a four-level stepped trench is used as an example for description, that is, the stepped trenches where the source 7 is located are the third-level stepped trench and the fourth-level stepped trench. In other words, Figure 7 The structure of the trench MOSFET device shown is Figure 6 The structure of the trench MOSFET device shown is improved by making the source part into a multi-level stepped trench, so that the stepped trench where the source 7 is located can be deep enough, so that the high-concentration doped ions of the P-type doping type at the bottom of the stepped trench where the source 7 is located can be implanted deeper, thereby better protecting the gate oxide layer 9.

[0103] Optionally, in another embodiment of the present invention, referring to Figure 8 , Figure 8 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 8 As shown, the trench MOSFET device has a symmetrical structure based on the n-th level stepped trench.

[0104] The third doped region 8 is located on both sidewalls of the other level stepped trenches.

[0105] The trench MOSFET device further includes an ohmic contact layer 17 and a Schottky contact layer 18 . The ohmic contact layer 17 is located on the sidewalls of the other-level stepped trenches, and the Schottky contact layer 18 is located at the bottom of the other-level stepped trenches.

[0106] Specifically, in the embodiment of the present invention, a three-level stepped groove is used as an example for description. Figure 8 The structure of the trench MOSFET device shown is Figure 6 The structure of the trench MOSFET device shown is improved so that it is symmetrical based on the n-th level stepped trench, that is, the stepped trenches where the gate portions on the left and right sides are located share a stepped trench where the source 7 is located, which can effectively increase the vertical channel path, improve the current density of the trench MOSFET device, and reduce the specific on-resistance. In addition, the stepped trench where the source 7 is located is deep enough to effectively shield the electric field strength near the gate oxide layer 9, ensuring the gate oxide reliability of the device; and the Schottky contact area is increased, so that the trench MOSFET device cell integrates a Schottky diode, effectively improving its reverse freewheeling capability.

[0107] Likewise, reference Figure 9 , Figure 9 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 9 As shown, the stepped trench where the source 7 is located is a multi-step trench.

[0108] Specifically, in the embodiment of the present invention, a four-level stepped trench is used as an example for description, that is, the stepped trenches where the source is located are the third-level stepped trench and the fourth-level stepped trench, that is, Figure 9 The structure of the trench MOSFET device shown is Figure 8 The structure of the trench MOSFET device shown is improved by making the source 7 part into a multi-level stepped trench, so that the stepped trench where the source 7 is located can be deep enough, so that the high-concentration doped ions of the P-type doping type at the bottom of the stepped trench where the source 7 is located can be implanted deeper, thereby better protecting the gate oxide layer 9.

[0109] And compared Figure 7 The structure of the trench MOSFET device shown increases the Schottky contact area, so that the trench MOSFET device cell integrates a Schottky diode, effectively improving its reverse freewheeling capability.

[0110] Optionally, in another embodiment of the present invention, referring to Figure 10 , Figure 10A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention is shown in FIG. Figure 10 As shown, the trench MOSFET device further includes:

[0111] The doped regions are located on a side of the second doped region 6 away from the second gate portion, and on a side of the other stepped trench adjacent to the second gate portion.

[0112] The doping region includes a ninth doping region 19 and a tenth doping region 20 , and the tenth doping region 20 at least partially surrounds the ninth doping region 19 .

[0113] Specifically, in the embodiment of the present invention, the ninth doping region 19 is a high-doping region of N-type doping type, and the doping concentration is 1E18-5E20 cm -3 , with a depth of 0.1-0.5um; the tenth doped region 20 is a low-doped region of P-type doping type, with a doping concentration of 1E16-1E18 cm -3 , depth is 0.2-2.0um.

[0114] That is to say, a ninth doping region 19 of N-type doping type and a tenth doping region 20 of P-type doping type are further implanted on the n-level stepped trench silicon carbide epitaxy, that is, a horizontal plane channel is added on the basis of the vertical channel, such as Figure 10 Indicated by the arrow.

[0115] Comparison Figure 1 The structure of the trench MOSFET device shown in Figure 10 The structure of the trench MOSFET device shown adds a horizontal planar channel. This trench MOSFET device cell integrates multiple levels of vertical and planar channels, which increases the current path, effectively improving the specific on-resistance, reducing the chip area, and reducing costs.

[0116] Optionally, in another embodiment of the present invention, referring to Figure 11 , Figure 11 A schematic structural diagram of another multi-step multi-channel trench MOSFET device provided by an embodiment of the present invention, Figure 10 The structure of the trench MOSFET device shown in FIG is further improved by adding a Schottky contact layer 18 to the sidewall of the source 7 on the first step and the sidewall of the other step trench away from the second gate portion. In other words, the second doped region 6 on the sidewall of the second step trench adjacent to the second gate portion can be split into two parts, and a Schottky contact is introduced in the middle to make the second doped region 6 Figure 11The trench MOSFET device shown further integrates a Schottky diode on the basis of integrating a vertical channel and a horizontal planar channel, which can effectively improve the reverse diode freewheeling capability.

[0117] From the above description, it can be seen that a trench MOSFET device provided by an embodiment of the present invention can increase the channel path of the unit trench cell and improve the channel density on the basis of ensuring gate oxide reliability and reverse breakdown, thereby forming a new type of multi-step multi-channel trench MOSFET device, reducing the specific on-resistance of the MOSFET transistor and improving the current density per unit area; and a trench MOSFET device proposed by the present invention, the gate and the source are both inside the same multi-step trench, the gate is located in the first and second step trenches, the source is located in the third step trench, and the optional source can also be located in other step trenches such as the third and fourth levels, so that the high-doped region of the P-type doping type can be implanted deeper, better protecting and optimizing the electric field distribution at the bottom of the trench gate oxide, the gate and the source are isolated by an isolation dielectric layer, and the high-doped ions of the P-type doping type in contact with the source serve as the source contact P-type ohmic contact on the one hand, and on the other hand, can effectively alleviate the electric field concentration at the bottom of the gate trench and improve the reliability of the gate oxide layer.

[0118] Moreover, the adjacent P-type doping type high-doping regions are not injected at the same horizontal position, which spatially separates the mutual influence between the adjacent P-type doping type high-doping regions, effectively reduces the JFET effect of the adjacent P-type doping type high-doping regions, reduces the JFET resistance, effectively reduces the specific on-resistance of the MOSFET transistor, and improves the current density per unit area. The low JFET effect reduces the on-resistance change under small and large currents.

[0119] Specifically, when the device is forward-conducting, only a very small part of the bottom of the gate trench has highly doped ions of the P-type doping type, and in the multi-step multi-channel MOSFET device structure, the adjacent P-type highly doped regions are not injected at the same horizontal position, which spatially separates the mutual influence between the injections of adjacent P-type highly doped regions, effectively reducing the JFET effect of the adjacent P-type highly doped regions and reducing the JFET resistance. At the same time, under the influence of the current expansion layer, this P-type highly doped region will not affect the current path near the bottom of the trench, and the current path from the vicinity of the channel to the current expansion layer and the epitaxy is unobstructed; a single MOSFET device cell contains a multi-step multi-channel path, which can effectively increase the current density per unit area and reduce the specific on-resistance of the MOSFET transistor; and the low JFET effect reduces the on-resistance change under small and large currents.

[0120] When the device is reverse-conducting, there are highly doped ions of the P-type doping type in contact with the source near the bottom of each gate trench, which can effectively alleviate the electric field concentration at the bottom of the gate trench. Compared with the structure in which the gate and source are in two trenches, the source and gate of the structure of the present invention are in the same stepped trench, the lateral distance between the source and gate is closer, and the gate is located in the first and second stepped trenches, and the source is located in the third stepped trench. The optional source can also be located in other stepped trenches such as the third and fourth levels, so that the highly doped region of the P-type doping type injected at the bottom of the source trench is deeper, which can effectively and significantly alleviate the electric field concentration at the bottom of the gate trench and better protect the gate oxide layer.

[0121] Furthermore, the trench MOSFET device provided by the embodiment of the present invention has a Schottky diode connected in anti-parallel near the source of the cell structure, which can significantly reduce the diode voltage drop of the MOSFET transistor without affecting the cell size, improve the reverse freewheeling capability of the device, improve the integration of the chip, and reduce the production cost of the MOSFET device with integrated Schottky diode.

[0122] In addition, the sidewalls and bottom of the n-level stepped trench of the trench MOSFET device provided by the embodiment of the present invention are provided with a P-type ohmic contact layer connected to the source. When the cell size remains unchanged, the P-type ohmic contact area of ​​the source is increased, the P-type contact resistance is effectively improved, and the diode voltage drop under large reverse freewheeling current will be significantly reduced.

[0123] At the same time, Figure 1 Based on the structure shown, we can get Figure 2-Figure 11 The other main structures shown, while ensuring gate oxide reliability and reverse breakdown, further improve the current density and significantly reduce the specific on-resistance. In addition, the integration of Schottky diodes without affecting the cell size can significantly improve the Schottky contact area and further enhance the reverse freewheeling capability of the Schottky diodes.

[0124] It should be noted that, in the embodiment of the present invention, the gate can be located in the first, ..., mth step trenches, and the source can be located in the m+1th, m+2th, ..., nth step trenches, depending on the actual situation. In the embodiment of the present invention, only m=2 is used as an example for explanation.

[0125] Optionally, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a method for preparing a trench MOSFET device, which is used to prepare the trench MOSFET device described in the above embodiments, referring to Figure 12 , Figure 12 A schematic flow chart of a method for preparing a multi-step multi-channel trench MOSFET device provided in an embodiment of the present invention, the preparation method comprising:

[0126] S101: providing a substrate.

[0127] S102: In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; the current spreading layer has n-level stepped trenches on a side facing away from the substrate, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate and points from the substrate to the current spreading layer.

[0128] S103: Prepare a subsequent structure, which includes a gate and a source, the gate being located in the first, ..., mth stepped trenches, and the source being located in the m+1th, m+2th, ..., nth stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first stepped trench and a second gate portion located in the second stepped trench, a sidewall of the first stepped trench adjacent to the first gate portion having a first doped region, a sidewall of the second stepped trench adjacent to the second gate portion having a first doped region, and a structure of the first gate portion being the same as that of the second gate portion; a source being located in other levels of stepped trenches, and a third doped region being located in the bottom area of ​​the nth stepped trench; wherein the first doped region, the second doped region, and the third doped region have the same doping type.

[0129] Specifically, in the embodiment of the present invention, based on Figure 12 The preparation method shown is Figure 1 The preparation process of the trench MOSFET device shown is explained below:

[0130] like Figure 13 As shown, n-level stepped trenches are formed by etching on the silicon carbide epitaxial layer. In the embodiment of the present invention, n=3 is used as an example for description.

[0131] like Figure 14 As shown, the required doping regions are implanted step by step on the silicon carbide epitaxial layer with n-level stepped trenches and an activation annealing process is performed at 1650° C.-1750° C., followed by a sacrificial oxidation process.

[0132] like Figure 15 As shown, a gate oxide layer and a gate are then formed in the stepped trench where the gate portion is located, an isolation dielectric layer is deposited, and a source contact hole is opened.

[0133] like Figure 1 As shown, other structures such as metal source are deposited.

[0134] Optionally, in an embodiment of the present invention, based on Figure 12 The preparation method shown is Figure 10 The preparation process of the trench MOSFET device shown is explained below:

[0135] like Figure 13 As shown, n-level stepped trenches 21 are formed by etching on the silicon carbide epitaxial layer. In the embodiment of the present invention, n=3 is used as an example for description.

[0136] like Figure 16 As shown, the required doping regions are implanted step by step on the silicon carbide epitaxial layer with n-level stepped trenches and an activation annealing process is performed at 1650° C.-1750° C., followed by a sacrificial oxidation process.

[0137] like Figure 17 As shown, a gate oxide layer and a gate are then formed in the stepped trench where the gate portion is located, an isolation dielectric layer is deposited, and a source contact hole is opened.

[0138] like Figure 10 As shown, other structures such as metal source are deposited.

[0139] It should be noted that the principle of the method for preparing a multi-step multi-channel trench MOSFET device provided in an embodiment of the present invention is the same as the principle of the multi-step multi-channel trench MOSFET device provided in the above embodiment of the present invention, and will not be repeated here.

[0140] The above is a detailed introduction to a multi-step multi-channel trench MOSFET device and a preparation method thereof provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0141] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0142] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0143] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-step multi-channel trench MOSFET device, characterized in that: The trench MOSFET device comprises: substrate; In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially located on one side of the substrate; the current spreading layer has n-level stepped trenches on a side facing away from the substrate, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate and points from the substrate to the current spreading layer; The trench MOSFET device further includes a gate and a source, the gate being located in the first, ..., and m-th stepped trenches, and the source being located in the m+1, m+2, ..., and n-th stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first-level stepped trench and a second gate portion located in the second-level stepped trench, a sidewall of the first-level stepped trench adjacent to the first gate portion having a first doped region, and a sidewall of the second-level stepped trench adjacent to the second gate portion having a second doped region, and the structure of the first gate portion is the same as that of the second gate portion; a source electrode located in the other level stepped trenches, and a third doped region located in the bottom region of the n level stepped trench; The first doping region, the second doping region and the third doping region have the same doping type.

2. The trench MOSFET device according to claim 1, wherein: The sidewall of the first-level stepped trench adjacent to the first gate portion further has a fourth doped region and a fifth doped region; The fourth doping region and the fifth doping region are located between the first doping region and the first gate portion, and the fourth doping region and the fifth doping region are arranged sequentially in the first direction; The sidewall of the second-level stepped trench adjacent to the second gate portion further has a sixth doped region and a seventh doped region; The sixth doping region and the seventh doping region are located between the second doping region and the second gate portion, and the sixth doping region and the seventh doping region are sequentially arranged in the first direction.

3. The trench MOSFET device according to claim 2, wherein: The trench MOSFET device further comprises: An eighth doped region is located on a sidewall away from the second gate portion.

4. The trench MOSFET device according to claim 3, wherein: The third doped region is located at the bottom of the n-level stepped trench and also extends to both sidewalls of the other-level stepped trenches; The trench MOSFET device further comprises: An ohmic contact layer is located at the bottom of the other level stepped trench and extends to the sidewalls of the other level stepped trench and the sidewalls of the eighth doped region.

5. The trench MOSFET device according to claim 3, wherein: The third doped region is located at the bottom of the n-level stepped trench and also extends to a sidewall of the other-level stepped trench adjacent to the second gate portion; The trench MOSFET device further includes: an ohmic contact layer and a Schottky contact layer; The ohmic contact layer is located at the bottom of the other stepped trench and extends to a side wall of the other stepped trench adjacent to the second gate portion; the Schottky contact layer is located on a side wall of the other stepped trench away from the second gate portion.

6. The trench MOSFET device according to claim 5, wherein: A sidewall of the n-level stepped trench away from the second gate portion is a step structure; The Schottky contact layer also extends to the surface of the stepped structure.

7. The trench MOSFET device according to claim 2, wherein: The trench MOSFET device has a symmetrical structure based on the n-th level stepped trench.

8. The trench MOSFET device according to claim 7, wherein: The third doped region is located at the bottom of the n-level stepped trench and also extends to both sidewalls of the other-level stepped trenches; the trench MOSFET device further includes: an ohmic contact layer, the ohmic contact layer is located at the bottom of the other-level stepped trench and extends to the sidewalls of the other-level stepped trenches; or, The third doped region is located on both sidewalls of the other level stepped trenches; The trench MOSFET device further includes an ohmic contact layer and a Schottky contact layer, wherein the ohmic contact layer is located on the sidewalls of the other-level stepped trench, and the Schottky contact layer is located at the bottom of the other-level stepped trench.

9. The trench MOSFET device according to claim 4, wherein: The trench MOSFET device further comprises: a doped region located on a side of the second doped region away from the second gate portion, and a doped region located on a side of the other level stepped trench adjacent to the second gate portion; The doping region includes a ninth doping region and a tenth doping region, and the tenth doping region is at least partially arranged to surround the ninth doping region.

10. A method for preparing a multi-step multi-channel trench MOSFET device, characterized in that: For preparing the trench MOSFET device according to any one of claims 1 to 9, the preparation method comprises: providing a substrate; In a first direction, a buffer layer, an epitaxial layer, and a current spreading layer are sequentially formed on one side of the substrate; a side of the current spreading layer facing away from the substrate has n-level stepped trenches, where n is a positive integer greater than or equal to 3; the first direction is perpendicular to the plane of the substrate and points from the substrate to the current spreading layer; Prepare a subsequent structure, which includes a gate and a source, the gate being located in the first, ..., mth stepped trenches, and the source being located in the m+1th, m+2th, ..., nth stepped trenches, where m is a positive integer greater than or equal to 2, wherein the gate includes a first gate portion located in the first stepped trench and a second gate portion located in the second stepped trench, a sidewall of the first stepped trench adjacent to the first gate portion having a first doped region, a sidewall of the second stepped trench adjacent to the second gate portion having a second doped region, and a structure of the first gate portion being the same as a structure of the second gate portion; a source being located in the other stepped trenches, and a third doped region being located in the bottom area of ​​the nth stepped trench; wherein the first doped region, the second doped region, and the third doped region have the same doping type.

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