Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductor manufacturing. In the semiconductor device, a top surface of a first source region of a first conductive type is flush with a top surface of a substrate and an outer surface is located in the substrate; a first well ring of a second conductive type covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate; a semiconductor column of the second conductive type penetrates the first source region and the first well ring in a direction towards the substrate via the top surface of the substrate; and spaced first gate structures and second gate structures cover top surfaces of the first well ring and the first source region, and the first gate structures, the semiconductor column and the second gate structures are sequentially distributed in a first direction parallel to the top surface of the substrate. At least the MOS channel density can be improved, the impedance and power loss during forward conduction of the MOS device can be reduced, and the surge resistance can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for preparing the same. Background Technology

[0002] Vertical double-diffused MOSFETs (VDMOS) can withstand voltages up to 1000V and above through double diffusion process and low-doped drift region design, making them suitable for high-voltage applications. Furthermore, the vertical conduction path shortens the current path and significantly reduces on-resistance.

[0003] PiN diodes have many advantages such as high sensitivity, fast response, wide bandwidth and low noise, and are widely used in low power consumption, high voltage and high frequency applications.

[0004] However, in semiconductor devices involving VDMOS and PiN diode structures, the VDMOS and PiN diode structures are typically spaced apart, leading to a reduction in MOS channel density. Furthermore, the PiN structure exhibits a high peak voltage during reverse recovery, which may cause output oscillation and may also force the device driver to use a larger gate configuration to reduce switching speed, thus suppressing the device's output capability. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor device and its fabrication method to address the technical problems in the prior art, which can at least improve the MOS channel density, reduce the impedance and power loss of the MOS device during forward conduction, and improve the surge resistance.

[0006] In a first aspect, this disclosure provides a semiconductor device, including a substrate of a first conductivity type, a first source region of a first conductivity type, a first well ring of a second conductivity type, a semiconductor pillar of a second conductivity type, a first gate structure, and a second gate structure. The top surface of the first source region of the first conductivity type is flush with the top surface of the substrate, and its outer surface is located within the substrate. The first well ring of the second conductivity type covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate. The semiconductor pillar of the second conductivity type penetrates the first source region and the first well ring via the top surface of the substrate in a direction toward the substrate. The first gate structure and the second gate structure, spaced apart, cover the top surface of the first well ring and the top surface of the first source region. The first gate structure, the semiconductor pillar, and the second gate structure are sequentially distributed along a first direction parallel to the top surface of the substrate.

[0007] In the semiconductor device described above, the first well ring of the second conductivity type directly below the first gate structure includes a first portion extending in a direction perpendicular to the substrate and a second portion extending in a first direction parallel to the substrate. This relatively increases the channel size without increasing the substrate size, thus contributing to improved channel density. The second conductivity type semiconductor pillar can not only make ohmic contact with the conductive plug directly above it, but also form a PN junction with the first conductivity type first source region and the substrate. Therefore, the semiconductor device in this embodiment combines the advantages of VDMOS, PN diode, and Schottky structures, and can improve MOS channel density, reduce impedance and power loss during forward conduction of the MOS device, and improve surge protection.

[0008] In some embodiments, the first gate structure and the second gate structure are fabricated simultaneously in the same process steps. The first gate structure and the second gate structure can be fabricated by etching the initial gate structure to split it, which reduces the complexity of the fabrication process and reduces the gate-to-drain capacitance (Cgd) of the device, which is beneficial for high-frequency applications of the device.

[0009] In some embodiments, the first gate dielectric layer shared by the first gate structure and the second gate structure covers the top surface of the first well ring and the top surface of the first source region, and includes a first opening exposing the semiconductor pillar. The shared first gate dielectric layer by the first gate structure and the second gate structure can reduce the complexity and cost of the fabrication process. The first gate dielectric layer including the first opening exposing the semiconductor pillar facilitates ohmic connection between the semiconductor pillar and the conductive plug through the first opening, reducing conductivity impedance.

[0010] In some embodiments, the first gate conductive layer of the first gate structure, the first opening, and the second gate conductive layer of the second gate structure are sequentially distributed along a first direction; a first passivation layer shared by the first gate structure and the second gate structure covers the first gate dielectric layer, the first gate conductive layer, and the second gate conductive layer, and includes a via exposing the first opening; wherein, the semiconductor pillar is used for ohmic connection with the first conductive plug within the via. This facilitates the fabrication of the first gate structure and the second gate structure by etching the initial gate structure, reducing the complexity of the fabrication process while also reducing the gate-to-drain capacitance (Cgd) of the device, which is beneficial for high-frequency applications.

[0011] In some embodiments, the semiconductor device further includes: a third gate structure, a fourth gate structure, a fifth gate structure, a sixth gate structure, a second source region of a first conductivity type, a third source region of a first conductivity type, and a second well ring and a third well ring of a second conductivity type sequentially spaced apart within a substrate along a first direction away from the first well ring; the top surface of the second well ring is flush with the top surface of the substrate and is embedded within the substrate; the top surface of the third well ring is flush with the top surface of the substrate and is embedded within the substrate; the top surface of the second source region is flush with the top surface of the substrate and its outer surface is located within the second well ring; the top surface of the third source region is flush with the top surface of the substrate and its outer surface is located within the third well ring; the third gate structure and the fourth gate structure spaced apart along the first direction cover the top surface of the second well ring; the fifth gate structure and the sixth gate structure spaced apart along the first direction cover the top surface of the third well ring; at least a portion of the top surface of the substrate between the fourth gate structure and the first gate structure is used for connection with a second conductive plug Schottky junction. The third gate structure, the fourth gate structure, the fifth gate structure, the sixth gate structure, the second source region of the first conductivity type, the third source region of the first conductivity type, and the second well ring and the third well ring of the second conductivity type, which are sequentially spaced in the substrate along a first direction away from the first well ring, are used to jointly constitute the VDMOS structure.

[0012] In some embodiments, the third gate structure and the sixth gate structure, which are adjacent along the first direction, share a second gate dielectric layer, which covers at least a portion of the top surface of the substrate between the second well ring and the third well ring.

[0013] In some embodiments, the second gate dielectric layer includes a second opening that exposes at least a portion of the top surface of the substrate between the second well ring and the third well ring, so that the exposed portion of the top surface of the substrate between the second well ring and the third well ring can form a Schottky structure with a third conductive plug via the second opening.

[0014] In some embodiments, the third gate dielectric layer shared by the third gate structure and the fourth gate structure includes a third opening that exposes a portion of the top surface of the second source region. This third opening facilitates the ohmic connection of the exposed portion of the top surface of the second source region with a fourth conductive plug, forming a Schottky structure.

[0015] In some embodiments, the fourth gate dielectric layer shared by the fifth gate structure and the sixth gate structure includes a fourth opening that exposes a portion of the top surface of the third source region. This fourth opening facilitates an ohmic connection between the exposed portion of the top surface of the third source region and the fifth conductive plug, forming a Schottky structure.

[0016] In some embodiments, the semiconductor device further includes: a seventh gate structure, a fourth source region of a first conductivity type, and a fourth well ring of a second conductivity type distributed at intervals from the third well ring along a first direction away from the third well ring; the fourth well ring having a top surface flush with the top surface of the substrate and embedded within the substrate; the fourth source region having a top surface flush with the top surface of the substrate and an outer surface located within the fourth well ring; the seventh gate structure covering the top surface of the fourth source region; and at least a portion of the top surface of the substrate between the fifth gate structure and the seventh gate structure being used to form a Schottky structure with a sixth conductive plug.

[0017] In some embodiments, the semiconductor device further includes an eighth gate structure located on the top surface of a fourth source region on the side away from the seventh gate structure along a first direction; wherein a portion of the top surface of the fourth source region between the seventh gate structure and the eighth gate structure is used for ohmic connection with a seventh conductive plug to form a Schottky structure.

[0018] In some embodiments, the first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, the sixth gate structure, the seventh gate structure, and the eighth gate structure are prepared simultaneously in the same process steps to reduce the complexity of the preparation process.

[0019] Secondly, embodiments of this disclosure also provide a method for fabricating a semiconductor device, comprising:

[0020] A first conductivity type substrate is provided, the first conductivity type substrate includes a first source region of the first conductivity type and a first well ring of the second conductivity type, the top surface of the first source region is flush with the top surface of the substrate and the outer surface is located inside the substrate, the first well ring covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate;

[0021] An initial gate structure is formed that covers the top surface of the first well ring and the top surface of the first source region;

[0022] The initial gate structure, the first source region, and the first well ring are etched to form a groove that runs through the initial gate structure, the first source region, and the first well ring, thereby obtaining a first gate structure and a second gate structure separated by the groove;

[0023] A second type of conductive semiconductor pillar is formed in the groove between the first gate structure and the second gate structure.

[0024] Thirdly, this disclosure also provides an electronic device, including the semiconductor device in any of the above embodiments, or a semiconductor device prepared using the semiconductor device preparation method in any of the above embodiments.

[0025] Since the semiconductor devices and electronic devices of the above embodiments are based on the same inventive concept as the semiconductor device fabrication method provided in the embodiments of this disclosure, the semiconductor devices and electronic devices using this fabrication method have all the advantages of the fabrication method provided in the embodiments of this disclosure, and will not be described in detail here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a top view schematic diagram of a semiconductor structure in a comparative embodiment;

[0028] Figure 2 For along Figure 1 Schematic diagram of the longitudinal section structure obtained in the AA' direction;

[0029] Figure 3 For along Figure 1 Schematic diagram of the longitudinal section structure obtained in the BB' direction;

[0030] Figure 4 This is a schematic flowchart of a semiconductor device fabrication method provided in one embodiment;

[0031] Figure 5 This is a schematic cross-sectional view of a semiconductor device provided in one embodiment;

[0032] Figure 6 This is a schematic cross-sectional view of a semiconductor device with a minimum repeatable unit structure in one embodiment.

[0033] Figure 7 This is a cross-sectional schematic diagram of a semiconductor device with a minimum repeatable unit structure in another embodiment;

[0034] Figure 8 This is a cross-sectional schematic diagram of a semiconductor device with a minimum repeatable unit structure in another embodiment.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1000, PN diode structure; 2000, Schottky structure; 100, substrate; 21, P-type well ring; 22, N-type source region; G, gate electrode; 11, P-type well region; 12, N-type doped region; 13, intrinsic semiconductor layer; M, conductive layer; 14, electrode layer; CT1, first conductive plug; CT2, second conductive plug; CT3, third conductive plug; CT4, fourth conductive plug; CT5, fifth conductive plug; CT6, sixth conductive plug; CT7, seventh conductive plug; 31, first well ring; 32, first source region; 33, first passivation layer; 34, semiconductor pillar; G1, first gate structure; G10, the first... G11, First gate conductive layer; G2, Second gate structure; G21, Second gate conductive layer; G3, Third gate structure; G30, Second gate dielectric layer; G4, Fourth gate structure; G40, Third gate dielectric layer; G5, Fifth gate structure; G50, Fourth gate dielectric layer; G6, Sixth gate structure; G7, Seventh gate structure; G70, Fifth gate dielectric layer; G8, Eighth gate structure; 41, Second well ring; 42, Second source region; 51, Third well ring; 52, Third source region; 61, Fourth well ring; 62, Fourth source region; 3000, Unit structure; VDMOS, Vertical double-diffused metal-oxide-semiconductor field-effect transistor. Detailed Implementation

[0037] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0042] In this embodiment, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the stacking direction or the direction away from the top surface of the substrate (the thickness direction of the substrate) is, for example, a second direction. In this embodiment, the first direction can be the ox direction, and the second direction can be the oz direction; in a plane parallel to the top surface of the substrate, the oy direction is perpendicular to the ox direction. In this embodiment, the "cross section" is parallel to the top surface of the substrate, and the "longitudinal section" or "section" is perpendicular to the top surface of the substrate.

[0043] The structure of an MPS diode (Merged PIN Schottky Diode) mainly consists of an alternating arrangement of finger grids and Schottky structures. When the MPS diode is forward biased, the Schottky junction is in a forward conducting state. As the drift region voltage increases, the PN junction is forward biased, and a conductivity modulation effect occurs in the drift region, effectively reducing the forward voltage drop (VF). When the MPS diode is reverse biased, the depletion region formed by the PN junction diffuses into the channel region, shielding the Schottky interface from high fields and avoiding the Schottky barrier reduction effect, greatly improving the device's breakdown voltage. Ultimately, the device's breakdown voltage approaches the avalanche breakdown voltage of the PN structure. Therefore, MPS diodes have the following characteristics:

[0044] 1) Low forward voltage drop: In the forward conduction state, the MPS diode significantly reduces the forward voltage drop through the conductivity modulation effect, thereby reducing power loss.

[0045] 2) Fast recovery characteristics: Due to its unique structural design, the MPS diode exhibits ultra-soft recovery characteristics during reverse recovery, reducing switching losses.

[0046] 3) High surge reliability: MPS diodes exhibit higher surge reliability under high current, and can maintain stable operation under high current pulses, making them less prone to failure.

[0047] Please refer to Figures 1-3 In a comparative embodiment, Figure 1 This is a top view schematic diagram of a semiconductor structure. Figure 2 For along Figure 1 Schematic diagram of the longitudinal section structure obtained in the AA' direction. Figure 3 For along Figure 1 A schematic diagram of the longitudinal section structure obtained in the BB' direction, wherein... Figure 2 This diagram illustrates a cross-section of a metal-oxide-semiconductor field-effect transistor (MOSFET) device structure. Figure 3 This diagram shows a cross-section of a PN diode device structure.

[0048] Please refer to Figure 2 The substrate 100 can be N-type, with P-type well rings 21 spaced apart along the ox direction within the substrate 100, each including an N-type source region 22. The gate electrode G covers the top surface of the substrate 100 between adjacent P-type well rings 21 along the ox direction. The gate electrode G, the adjacent P-type well rings 21 along the ox direction, and the N-type source regions 22 can together constitute a MOSFET device.

[0049] Please refer to Figure 3 The substrate 100 can be N-type, with a P-type well region 11 located within the substrate 100 and an N-type doped region 12 located within the substrate 100. The P-type well region 11 can be located on the outer wall of the P-type doped region 12. An intrinsic semiconductor layer 13 can be included between the P-type well region 11 and the N-type doped region 12. The P-type well region 11, the intrinsic semiconductor layer 13, and the N-type doped region 12 can together constitute a PiN diode device.

[0050] However, please continue to refer to Figures 1-3 The channel of a PiN diode cannot be directly turned on; it needs to be routed to a MOSFET device, which increases the on-resistance and sacrifices channel density. Furthermore, the PiN structure exhibits a high peak voltage during reverse recovery, which may cause output oscillation and may also force the device driver to use a larger gate configuration to reduce switching speed, thus suppressing the device's output capability.

[0051] Therefore, the present disclosure aims to provide a semiconductor device and its fabrication method, which can at least increase the MOS channel density, reduce the impedance and power loss of the MOS device during forward conduction, and improve surge resistance.

[0052] Please see Figure 4 In some embodiments, a method for fabricating a semiconductor device is provided, comprising:

[0053] Step S20: Provide a first conductivity type substrate, which includes a first conductivity type first source region and a second conductivity type first well ring. The top surface of the first source region is flush with the top surface of the substrate and the outer surface is located inside the substrate. The first well ring covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate.

[0054] Step S40: Form an initial gate structure covering the top surface of the first well ring and the top surface of the first source region;

[0055] Step S60: Etch the initial gate structure, the first source region, and the first well ring to form a groove that penetrates the initial gate structure, the first source region, and the first well ring, thereby obtaining a first gate structure and a second gate structure separated by the groove;

[0056] A second type of conductive semiconductor pillar is formed within the groove, located between the first gate structure and the second gate structure;

[0057] Step S80: Form a second type of conductive semiconductor pillar located between the first gate structure and the second gate structure in the groove.

[0058] For example, the first well ring of the second conductivity type directly below the first gate structure may include a first portion extending in a direction perpendicular to the substrate and a second portion extending in a first direction parallel to the substrate. This relatively increases the channel size without increasing the substrate size, thus contributing to improved channel density. Similarly, the first well ring of the second conductivity type directly below the second gate structure may include a first portion extending in a direction perpendicular to the substrate and a second portion extending in a first direction parallel to the substrate. This relatively increases the channel size without increasing the substrate size, thus contributing to improved channel density. The second conductivity type semiconductor pillar can not only make ohmic contact with the conductive plug directly above it, but can also form a PN junction with the first conductivity type first source region and the substrate, thereby forming a PN diode. Therefore, the semiconductor device in this embodiment combines the advantages of VDMOS, PN diode, and Schottky structures, and can improve MOS channel density, reduce impedance and power loss during forward conduction of the MOS device, and improve surge resistance.

[0059] The semiconductor device obtained after steps S20-S60 can be found in [reference]. Figure 5 For ease of understanding this disclosure, Figure 5 This is one example of a semiconductor device prepared using the preparation method provided in this disclosure. Other suitable examples of semiconductor devices prepared using the preparation method provided in this disclosure are also possible, and this disclosure does not limit them.

[0060] The above steps are explained in detail with reference to the attached diagram.

[0061] Please see Figure 5 The extended step S20 further includes providing a first conductivity type substrate 100, which may be constructed of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 100 should not limit the scope of this disclosure.

[0062] Please continue reading. Figure 5In some embodiments, the first conductivity type substrate 100 provided in step S20 includes a first conductivity type first source region 32 and a second conductivity type first well ring 31. The top surface of the first source region 32 is flush with the top surface of the substrate 100 and the outer surface is located inside the substrate 100. The first well ring 31 covers the outer surface of the first source region 32 and is embedded in the substrate 100 via the top surface of the substrate 100.

[0063] Please continue reading. Figure 5 In some embodiments, the doping concentration of the first source region 32 is greater than the doping concentration of the first well ring 31. The first source region 32 of the first conductivity type can be formed after the first well ring 31 of the second conductivity type, or the first source region 32 of the first conductivity type can be formed before the first well ring 31 of the second conductivity type. For example, the first source region 32 can be an N+ source region, and the first well ring 31 can be a P-type well ring.

[0064] Please continue reading. Figure 5 In some embodiments, in step S40, an initial gate structure (not shown) is formed covering the top surface of the first well ring 31 and the top surface of the first source region 32. For example, an initial gate oxide layer (not shown) covering the top surface of the first well ring 31 and the top surface of the first source region 32 can be formed first using an oxidation process or a deposition process. Then, an initial gate conductive layer (not shown) covering the initial gate oxide layer is formed using a deposition process. The initial gate oxide layer and the initial gate conductive layer are used together to constitute the initial gate structure.

[0065] Please continue reading. Figure 5 In some embodiments, step S60 may employ a dry etching process to etch the initial gate structure, the first source region 32, and the first well ring 31, forming a groove (not shown) penetrating the initial gate structure, the first source region 32, and the first well ring 31, resulting in a first gate structure G1 and a second gate structure G2 separated by the groove. The first gate structure G1 includes a stacked first gate dielectric layer G10 and a first gate conductive layer G11. The second gate structure G2 includes a stacked first gate dielectric layer G10 and a second gate conductive layer G21. The first gate structure G1 and the second gate structure G2 are fabricated simultaneously in the same process step. The first gate structure G1 and the second gate structure G2 are fabricated by etching the initial gate structure, which reduces the complexity of the fabrication process and reduces the gate-to-drain capacitance (Cgd) of the device, which is beneficial for high-frequency applications of the device.

[0066] Please continue reading. Figure 5 In some embodiments, step S80 may employ a deposition process to form a second conductivity type semiconductor pillar 34 located between the first gate structure G1 and the second gate structure G2 within the groove. For example, the semiconductor pillar 34 may be a P+ type semiconductor pillar.

[0067] Please continue reading. Figure 5 In some embodiments, the bottom surface of the semiconductor pillar 34 is lower than the bottom surface of the first well ring 31.

[0068] Please continue reading. Figure 5 In some embodiments, after step S80, a first passivation layer 33 covering the first gate conductive layer G11 and the second gate conductive layer G21 can be formed using a deposition process. The material of the first passivation layer 33 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or combinations thereof.

[0069] Please continue reading. Figure 5 In some embodiments, after the first passivation layer 33 is formed, a deposition process can be used to form a conductive layer M. The portion of the conductive layer M located between the adjacent first gate structure G1 and the second gate structure G2 can constitute a first conductive plug CT1. The first conductive plug CT1 penetrates the first gate dielectric layer G10 and is ohmically connected to the semiconductor pillar 34.

[0070] Please continue reading. Figure 5 ,like Figure 5 The semiconductor structure shown includes: a first gate structure G1, a second gate structure G2, a first conductive plug CT1, a semiconductor pillar 34, a first source region of a first conductivity type 32, and a first well ring of a second conductivity type 31. It combines the advantages of VDMOS, PN diode, and Schottky structures, and can increase MOS channel density, reduce impedance and power loss during forward conduction of the MOS device, and improve surge protection.

[0071] Please continue reading. Figure 5 In some embodiments, a semiconductor device is provided, including a first conductivity type substrate 100, a first conductivity type first source region 32, a second conductivity type first well ring 31, a second conductivity type semiconductor pillar 34, a first gate structure G1, and a second gate structure G2. The top surface of the first conductivity type first source region 32 is flush with the top surface of the substrate 100, and its outer surface is located within the substrate 100. The second conductivity type first well ring 31 covers the outer surface of the first source region 32 and is embedded within the substrate 100 via the top surface of the substrate 100. The second conductivity type semiconductor pillar 34 penetrates the first source region 32 and the first well ring 31 via the top surface of the substrate 100 in a direction toward the substrate 100. The spaced first gate structure G1 and the second gate structure G2 cover the top surface of the first well ring 31 and the top surface of the first source region 32. The first gate structure G1, the semiconductor pillar 34, and the second gate structure G2 are distributed sequentially along a first direction parallel to the top surface of the substrate 100.

[0072] Please continue reading. Figure 5The first well ring 31 of the second conductivity type directly below the first gate structure G1 includes a first portion extending in a direction perpendicular to the substrate 100 and a second portion extending in a first direction parallel to the substrate 100. Without increasing the size of the substrate 100, it relatively increases the channel size, thus contributing to improved channel density. The first well ring 31 of the second conductivity type directly below the second gate structure G2 also includes a first portion extending in a direction perpendicular to the substrate 100 and a second portion extending in a first direction parallel to the substrate 100. Without increasing the size of the substrate 100, it relatively increases the channel size, thus contributing to improved channel density. The second conductivity type semiconductor pillar 34 can not only make ohmic contact with the first conductive plug CT1 directly above it, but also form a PN junction with the first conductivity type first source region 32 and the substrate 100, thereby forming a PN structure. Therefore, it combines the advantages of VDMOS, PN diode, and Schottky structures, and can improve MOS channel density, reduce impedance and power loss during forward conduction of the MOS device, and improve surge resistance.

[0073] Please continue reading. Figure 5 In some embodiments, the first gate dielectric layer G10, shared by the first gate structure G1 and the second gate structure G2, covers the top surface of the first well ring 31 and the top surface of the first source region 32, and includes a first opening (not shown) exposing the semiconductor pillar 34. The shared first gate dielectric layer G10 by the first gate structure G1 and the second gate structure G2 can reduce the complexity and cost of the fabrication process. The first gate dielectric layer G10 includes a first opening exposing the semiconductor pillar 34, which facilitates an ohmic connection between the semiconductor pillar 34 and the first conductive plug CT1 via the first opening, reducing conductivity impedance.

[0074] Please continue reading. Figure 5 In some embodiments, the first gate conductive layer G11 of the first gate structure G1, the first opening, and the second gate conductive layer G21 of the second gate structure G2 are sequentially distributed along a first direction; the first passivation layer 33 shared by the first gate structure G1 and the second gate structure G2 covers the first gate dielectric layer G10, the first gate conductive layer G11, and the second gate conductive layer G21, and includes a via (not shown) exposing the first opening; wherein, the semiconductor pillar 34 is used for ohmic connection with the first conductive plug CT1 in the via. This facilitates the fabrication of the first gate structure G1 and the second gate structure G2 by etching the initial gate structure, reducing the complexity of the fabrication process while also reducing the gate-to-drain capacitance (Cgd) of the device, which is beneficial for high-frequency applications.

[0075] Please continue reading. Figure 5In some embodiments, the semiconductor device further includes: a third gate structure G3, a fourth gate structure G4, a fifth gate structure G5, a sixth gate structure G6, a second source region 42 of a first conductivity type, a third source region 52 of a first conductivity type, and a second well ring 41 and a third well ring 51 of a second conductivity type sequentially spaced apart within the substrate 100 along a first direction away from the first well ring 31; the top surface of the second well ring 41 is flush with the top surface of the substrate 100 and is embedded within the substrate 100; the top surface of the third well ring 51 is flush with the top surface of the substrate 100 and is embedded within the substrate 100. Within substrate 100: a second source region 42, with its top surface flush with the top surface of substrate 100 and its outer surface located within the second well ring 41; a third source region 52, with its top surface flush with the top surface of substrate 100 and its outer surface located within the third well ring 51; a third gate structure G3 and a fourth gate structure G4 spaced apart along a first direction, covering the top surface of the second well ring 41; a fifth gate structure G5 and a sixth gate structure G6 spaced apart along a first direction, covering the top surface of the third well ring 51; at least a portion of the top surface of substrate 100 between the fourth gate structure G4 and the first gate structure G1 is used for Schottky connection with the second conductive plug CT2. The third gate structure G3, the fourth gate structure G4, the fifth gate structure G5, the sixth gate structure G6, the first conductivity type second source region 42, the first conductivity type third source region 52, and the second conductivity type second well ring 41 and the second conductivity type third well ring 51 sequentially spaced apart within substrate 100 along a first direction away from the first well ring 31, together constitute a VDMOS structure.

[0076] Please continue reading. Figure 5 In some embodiments, the third gate structure G3 and the sixth gate structure G6, which are adjacent along the first direction, share a second gate dielectric layer G30, which covers at least a portion of the top surface of the substrate 100 between the second well ring 41 and the third well ring 51.

[0077] Please continue reading. Figure 5 In some embodiments, the third gate dielectric layer G40 shared by the third gate structure G3 and the fourth gate structure G4 includes a third opening (not shown), which exposes a portion of the top surface of the second source region 42. This third opening facilitates an ohmic connection between the exposed portion of the top surface of the second source region 42 and the fourth conductive plug CT4, forming a Schottky structure.

[0078] Please continue reading. Figure 5 In some embodiments, the fourth gate dielectric layer G50 shared by the fifth gate structure G5 and the sixth gate structure G6 includes a fourth opening (not shown), which exposes a portion of the top surface of the third source region 52. This fourth opening facilitates an ohmic connection between the exposed portion of the top surface of the third source region 52 and the fifth conductive plug CT5, forming a Schottky structure.

[0079] Please continue reading. Figure 5 In some embodiments, the semiconductor device further includes: a seventh gate structure G7, a fourth source region 62 of a first conductivity type, and a fourth well ring 61 of a second conductivity type distributed at intervals from the third well ring 51 along a first direction away from the third well ring 51; the fourth well ring 61 has its top surface flush with the top surface of the substrate 100 and embedded within the substrate 100; the fourth source region 62 has its top surface flush with the top surface of the substrate 100, and its outer surface is located within the fourth well ring 61; the seventh gate structure G7 covers the top surface of the fourth source region 62; at least a portion of the top surface of the substrate 100 between the fifth gate structure G5 and the seventh gate structure G7 is used to form a Schottky structure with the sixth conductive plug CT6.

[0080] Please continue reading. Figures 5-6 In some embodiments, it can be Figure 5 The example structure constitutes a minimum repeatable unit structure 3000, which includes a Schottky structure 2000, a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS), a PN diode structure 1000, and the Schottky structure 2000 arranged sequentially along the ox direction. Figure 6 The minimum repeatable cell structure in the example is arranged in a repeating array of 3000 repeatable cells to obtain the desired semiconductor structure. Figure 6 The smallest repeatable cell structure 3000 in the example contains 12 MOS channels, 4 Schottky structures, and 1 PN structure, with a high channel density.

[0081] Please see Figure 7 In some embodiments, Figure 7 The smallest repeatable unit structure 3000 in the example is... Figure 6 The differences in the minimum repeatable cell structure 3000 in the example include: the second gate dielectric layer G30 includes a second opening (not shown) that exposes at least a portion of the top surface of the substrate 100 between the second well ring 41 and the third well ring 51, so that the exposed top surface of the substrate 100 between the second well ring 41 and the third well ring 51 can form a Schottky structure with the third conductive plug CT3 through the second opening. Figure 7 The smallest repeatable cell structure 3000 in the example contains 12 MOS channels, 6 Schottky structures, and 1 PN structure.

[0082] Please continue reading. Figure 8 In some embodiments, Figure 8 The smallest repeatable unit structure 3000 in the example is... Figure 7 The differences between the minimum repeatable unit structure 3000 in the example include: Figure 8The smallest repeatable unit structure 3000 also includes an eighth gate structure G8, which is located on the top surface of the fourth source region 62 on the side away from the seventh gate structure G7 along the first direction; wherein, the part of the top surface of the fourth source region 62 between the seventh gate structure G7 and the eighth gate structure G8 is used to ohmically connect with the seventh conductive plug CT7 to form a Schottky structure. Figure 8 The smallest repeatable cell structure 3000 in the example contains 14 MOS channels, 6 Schottky structures, and 1 PN structure.

[0083] Based on the examples above, similar solutions can be adopted, allowing for flexible design according to application requirements. The ratio of MOS channel, Schottky structure, and PN structure (X:Y:1) can be adjusted according to the actual needs of the application. This approach offers high process compatibility and good design reusability.

[0084] Please continue reading. Figure 8 In some embodiments, the first gate structure G1, the second gate structure G2, the third gate structure G3, the fourth gate structure G4, the fifth gate structure G5, the sixth gate structure G6, the seventh gate structure G7, and the eighth gate structure G8 are prepared simultaneously in the same process steps to reduce the complexity of the preparation process.

[0085] In some embodiments, this disclosure also provides an electronic device, including the semiconductor device in any of the above embodiments, or a semiconductor device prepared using the semiconductor device preparation method in any of the above embodiments.

[0086] In the embodiments described above, a Schottky structure is integrated through a split-gate planar MOS structure, further integrating the MOS channel, Schottky structure, and PN structure at the chip level. This approach offers low manufacturing difficulty, ample design flexibility, and compatibility with mainstream process platforms. From a performance perspective, the increased channel density leads to a significant reduction in Ron and Cgd. The Schottky structure improves the reverse recovery characteristics of the diode, and the addition of the PN structure greatly enhances the surge capability of the device. Overall, all these aspects are significantly optimized from a device perspective.

[0087] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0088] The semiconductor device and its fabrication method disclosed herein have the following unexpected technical effects:

[0089] The first well ring of the second conductivity type directly below the first gate structure includes a first portion extending in a direction perpendicular to the substrate and a second portion extending in a first direction parallel to the substrate. This relatively increases the channel size without increasing the substrate size, thus contributing to improved channel density. The second conductivity type semiconductor pillar can not only make ohmic contact with the conductive plug directly above it, but also form a PN junction with the first conductivity type first source region and the substrate, thereby forming a PN structure. Therefore, the semiconductor device in this embodiment combines the advantages of VDMOS, PN diode, and Schottky structures, and can improve MOS channel density, reduce impedance and power loss during forward conduction of the MOS device, and improve surge resistance.

[0090] In addition, the first gate structure and the second gate structure can be fabricated by etching the initial gate structure to split it, which reduces the complexity of the fabrication process and reduces the gate-to-drain capacitance (Cgd) of the device, which is beneficial for high-frequency applications of the device.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized by, include: First conductivity type substrate; The first source region of the first conductivity type has a top surface flush with the top surface of the substrate and an outer surface located within the substrate; The second conductivity type first well ring covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate; A second conductivity type semiconductor pillar extends through the first source region and the first well ring via the top surface of the substrate in a direction toward the substrate; as well as A first gate structure and a second gate structure that cover the top surface of the first well ring and the top surface of the first source region; The first gate structure, the semiconductor pillar, and the second gate structure are distributed sequentially along a first direction parallel to the top surface of the substrate; The VDMOS structure is located on the side of the second gate structure and the first gate structure away from the semiconductor pillar, and is spaced apart along the first direction; the VDMOS structure includes four gate structures, and corresponding well rings and source regions located below the gate structures; Multiple conductive plugs, some of which, together with the substrate directly below, are used to form a Schottky structure; The semiconductor pillars and the underlying substrate form a PN structure; the minimum repeatable unit of the semiconductor device includes one PN structure, at least two VDMOS and at least four Schottky structures; the ratio of the MOS channel, Schottky structure and PN structure of the minimum repeatable unit is X:Y:

1.

2. The semiconductor device according to claim 1, wherein The first gate structure and the second gate structure are fabricated simultaneously in the same process steps; and / or The first gate dielectric layer shared by the first gate structure and the second gate structure covers the top surface of the first well ring and the top surface of the first source region, and includes a first opening that exposes the semiconductor pillar.

3. The semiconductor device according to claim 2, characterized in that, The first gate conductive layer of the first gate structure, the first opening, and the second gate conductive layer of the second gate structure are distributed sequentially along the first direction; The first passivation layer shared by the first gate structure and the second gate structure covers the first gate dielectric layer, the first gate conductive layer, and the second gate conductive layer, and includes a via that exposes the first opening; The semiconductor pillar is used to make an ohmic connection with the first conductive plug inside the through hole.

4. The semiconductor device according to any one of claims 1-3, characterized in that, Also includes: The third gate structure, the fourth gate structure, the fifth gate structure, the sixth gate structure, the second source region of the first conductivity type, the third source region of the first conductivity type, and the second well ring and the third well ring of the second conductivity type are sequentially and spaced apart in the substrate along a first direction away from the first well ring; The second well ring has its top surface flush with the top surface of the substrate and is embedded within the substrate; The third well ring has its top surface flush with the top surface of the substrate and is embedded within the substrate; The second source region has its top surface flush with the top surface of the substrate, and its outer surface located within the second well ring; The third source region has its top surface flush with the top surface of the substrate, and its outer surface located within the third well ring; The third gate structure and the fourth gate structure, spaced apart along the first direction, cover the top surface of the second well ring; The fifth gate structure and the sixth gate structure, spaced apart along the first direction, cover the top surface of the third well ring; At least a portion of the top surface of the substrate between the fourth gate structure and the first gate structure is used for connection with the second conductive plug Schottky.

5. The semiconductor device according to claim 4, characterized in that, The third gate structure and the sixth gate structure, which are adjacent along the first direction, share a second gate dielectric layer, which covers at least a portion of the top surface of the substrate between the second well ring and the third well ring; or The second gate dielectric layer includes a second opening that exposes at least a portion of the top surface of the substrate between the second well ring and the third well ring.

6. The semiconductor device according to claim 4, characterized in that, The third gate dielectric layer shared by the third gate structure and the fourth gate structure includes a third opening that exposes a portion of the top surface of the second source region; and / or The fourth gate dielectric layer shared by the fifth gate structure and the sixth gate structure includes a fourth opening that exposes a portion of the top surface of the third source region for ohmic connection with the fifth conductive plug.

7. The semiconductor device according to claim 5, characterized in that, Also includes: The seventh gate structure, the fourth source region of the first conductivity type, and the fourth well ring of the second conductivity type distributed at intervals from the third well ring along a first direction away from the third well ring; The fourth well ring has its top surface flush with the top surface of the substrate and is embedded within the substrate; The fourth source region has its top surface flush with the top surface of the substrate, and its outer surface located within the fourth well ring. The seventh gate structure covers the top surface of the fourth source region; At least a portion of the top surface of the substrate between the fifth gate structure and the seventh gate structure is used for connection with the sixth conductive plug Schottky.

8. The semiconductor device according to claim 7, characterized in that, Also includes: The eighth gate structure is located on the top surface of the fourth source region on the side away from the seventh gate structure along the first direction; The top surface of the fourth source region between the seventh gate structure and the eighth gate structure is used for ohmic connection with the seventh conductive plug.

9. The semiconductor device according to claim 8, characterized in that, The first gate structure, the second gate structure, the third gate structure, the fourth gate structure, the fifth gate structure, the sixth gate structure, the seventh gate structure, and the eighth gate structure are prepared simultaneously in the same process steps.

10. A method for fabricating a semiconductor device, characterized in that, Used to prepare the semiconductor device as described in any one of claims 1-9; The preparation method includes: A first conductivity type substrate is provided, the first conductivity type substrate includes a first source region of the first conductivity type and a first well ring of the second conductivity type, the top surface of the first source region is flush with the top surface of the substrate and the outer surface is located in the substrate, the first well ring covers the outer surface of the first source region and is embedded in the substrate via the top surface of the substrate; An initial gate structure is formed that covers the top surface of the first well ring and the top surface of the first source region; The initial gate structure, the first source region, and the first well ring are etched to form a groove penetrating the initial gate structure, the first source region, and the first well ring, thereby obtaining a first gate structure and a second gate structure separated by the groove; a VDMOS structure is formed on the side of the second gate structure and the first gate structure away from the semiconductor pillar, the VDMOS structure is arranged at intervals along the first direction, including four gate structures, and well rings and source regions located below the gate structures respectively; A second type of semiconductor pillar is formed within the groove, located between the first gate structure and the second gate structure; the semiconductor pillar and the underlying substrate form a PN structure; Multiple conductive plugs are formed, and some of the conductive plugs and the substrate directly below are used to form a Schottky structure; the minimum repeatable unit of the semiconductor device includes one PN structure, at least two VDMOS and at least four Schottky structures; the ratio of the MOS channel, Schottky structure and PN structure of the minimum repeatable unit is X:Y:1.

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