A static reactive power compensation device based on ZYNQ

Abstract

The application discloses a static reactive power compensation device based on ZYNQ, which comprises a main controller, a voltage source inverter, a reactor, a power module and a ZYNQ module; a microprocessor, a ZYNQ chip and a first FPGA chip are arranged in the ZYNQ module; a driving board and a first turn-off semiconductor device are arranged in the power module; the driving board is connected with the main controller; the driving board is internally provided with a second FPGA chip; the first turn-off semiconductor device is internally provided with a switch tube S1, a switch tube S2, a switch tube S3 and a switch tube S4; the driving board is used for sending PWM waves; the switch tube S1, the switch tube S2, the switch tube S3 and the switch tube S4 are used for receiving the PWM waves; the first FPGA chip is connected with the second FPGA chip; the first FPGA chip is used for processing analog quantity zero drift; the second FPGA chip is connected with a fiber board through backboard LVDS wiring; and the fiber board is connected with a unit driving board through a transceiving optical fiber. The device can realize efficient real-time dynamic reactive power compensation, guarantee the stability of data transmission and realize high integration of the chip.

Description

Technical Field

[0001] This invention relates to the field of static var compensators (SVCs), and particularly to a static var compensator based on ZYNQ. Background Technology

[0002] Static Var Compensators (SVGs) are widely used in modern power systems for load compensation and transmission line compensation (voltage and reactive power compensation), especially in high-power grids. SVGs are used for voltage control or to achieve other benefits, such as improving system damping and stability. Instead of using large-capacity capacitors and inductors to generate the required reactive power, they achieve reactive power compensation through high-frequency switching of power electronic devices. Their main functions include: 1) rapidly, continuously, and dynamically outputting inductive and capacitive reactive power to the power system; 2) maintaining line and receiving-end voltage stability, suppressing voltage fluctuations and flicker; 3) compensating for system reactive power, improving power factor, reducing penalties, and reducing line losses; 4) eliminating negative sequence current and suppressing three-phase imbalance; 5) dynamic harmonic compensation, improving power quality, etc. The core technology of SVG devices lies in the control and communication systems. This involves calculating the relevant electrical quantities collected and precisely controlling the capacitor voltage of each module through the switching control of multiple full-bridge modules, enabling the device to generate or absorb reactive current and control the reactive power on the grid side. The control principle of the static var compensator is to use instantaneous reactive power detection, with power factor, system voltage, system reactive power and device reactive power as control targets, to dynamically track changes in grid power-related indicators, and adjust reactive power output in real time according to changes in the grid, so as to achieve high-energy-quality operation of the grid.

[0003] Currently, there are various hardware design schemes for the communication system of SVG devices. The mainstream scheme uses a microcontroller or DSP chip to perform complex electrical quantity calculations, combined with an FPGA chip for related control logic, analog signal acquisition, and communication interface functions, thereby achieving hardware-software co-design of the device. Most SVG devices are currently based on this multi-board, multi-CPU architecture. The number of chips is directly related to the design complexity of the hardware control board, resulting in high overall device complexity, large size, and high power consumption. Communication between chips uses an external fieldbus, which limits data transmission rates, hinders hardware-software integration, and prevents the full realization of the advantages of embedded systems.

[0004] Communication between the DSP and FPGA processors typically uses an off-chip asynchronous fieldbus, usually with an EMIFA parallel bus interface. However, this off-chip communication method is severely limited by EMC (Electronic Controlled Compatibility) conditions, significantly restricting transmission speed and data volume, and is increasingly unable to meet the higher real-time requirements of SVG (Static Var Generator) devices. This multi-chip off-chip communication architecture has relatively limited performance, poor stability, and weak anti-interference capabilities. The communication speed of ordinary fieldbuses has reached its bottleneck and is gradually failing to meet the fieldbus requirements of industrial control communication systems. Multi-chip hardware and software co-design requires developers to be familiar with different development environments, making development difficult. Different chip versions may require different software development platforms, and chip updates can affect board hardware and chip software design, severely impacting device development iterations and maintenance, and leading to excessively long development cycles.

[0005] Therefore, based on the existing static var compensator, how to improve the fieldbus reactive power compensation rate and meet the real-time requirements of field reactive power compensation has become an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the above problems, the present invention proposes a ZYNQ-based static var compensator that at least solves some of the above technical problems, which can realize efficient real-time dynamic var compensator and ensure the stability of data transmission.

[0007] This invention provides a static var compensator based on ZYNQ, comprising: a main controller; and a voltage source inverter, a reactor, a power module, and a ZYNQ module connected to the main controller; the ZYNQ module is configured with a microprocessor, a ZYNQ chip, and a first FPGA chip;

[0008] The voltage source inverter includes: a DC capacitor and an inverter;

[0009] The power module is equipped with a driver board and a first turn-off semiconductor device; the driver board is connected to the main controller; the driver board has a second FPGA chip inside; the first turn-off semiconductor device is equipped with switching transistors S1, S2, S3 and S4.

[0010] The driver board is used to generate PWM waves; the switching transistors S1, S2, S3 and S4 are used to receive the PWM waves.

[0011] The first FPGA chip is connected to the second FPGA chip; the first FPGA chip is used for zero drift processing of analog signals.

[0012] The second FPGA chip is connected to the fiber optic board via LVDS traces on the backplane;

[0013] The fiber optic board is connected to the unit driver board via transceiver fibers.

[0014] Furthermore, the inverter is internally equipped with a second turn-off semiconductor device.

[0015] Furthermore, the ZYNQ chip and the second FPGA chip are integrated on a single CPU hardware board.

[0016] Furthermore, an AXI bus connects the ZYNQ chip and the second FPGA chip.

[0017] Furthermore, the AXI bus includes: four AXI_HP high-performance interfaces, an AXI_ACP bus, and four AXI_GP general-purpose interfaces.

[0018] Furthermore, the AXI_ACP bus is a 64-bit slave interface on the Consistent Storage Control Unit (SCU).

[0019] Furthermore, the microprocessor consists of two ARM processors; one ARM processor is used to parse the instructions sent by the host computer and the data sent by the second FPGA chip; the other ARM processor is used to generate the modulation wave that produces the PWM wave.

[0020] Furthermore, the first FPGA chip is used to receive encoded analog data through the optical fiber board and decode the analog data.

[0021] Furthermore, it also includes an M-GBE2 gigabit port, which connects to another SVG controller for switching between the primary and backup controllers when the primary controller malfunctions.

[0022] Furthermore, the second FPGA chip has four gigabit ports and four FT3 interfaces.

[0023] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following:

[0024] This invention provides a ZYNQ-based static var compensator, comprising: a main controller, a voltage source inverter, a reactor, a power module, and a ZYNQ module; the ZYNQ module is equipped with a microprocessor, a ZYNQ chip, and a first FPGA chip; the power module is equipped with a driver board and a first turn-off semiconductor device; the driver board is connected to the main controller; the driver board contains a second FPGA chip; the first turn-off semiconductor device contains switching transistors S1, S2, S3, and S4; the driver board is used to generate PWM waves; switching transistors S1, S2, S3, and S4 are used to receive PWM waves; the first FPGA chip is connected to the second FPGA chip; the first FPGA chip is used for zero-drift processing of analog signals; the second FPGA chip is connected to an optical fiber board via LVDS traces on a backplane; the optical fiber board is connected to the unit driver board via transceiver optical fibers. This device can achieve efficient real-time dynamic reactive power compensation, ensure data transmission stability, and achieve high chip integration.

[0025] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0026] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0028] Figure 1 This is a schematic diagram of the main circuit topology of the star-connected SVG device provided in an embodiment of the present invention;

[0029] Figure 2 A topology diagram of a chain-type SVG power module provided in an embodiment of the present invention;

[0030] Figure 3 This is a block diagram of the overall architecture of the chain-type SVG device provided in an embodiment of the present invention. Detailed Implementation

[0031] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0032] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] This invention provides a static var compensator based on ZYNQ, comprising: a main controller; and a voltage source inverter, a reactor, a power module, and a ZYNQ module connected to the main controller; the ZYNQ module is configured with a microprocessor, a ZYNQ chip, and a first FPGA chip;

[0035] A voltage source inverter consists of: a DC capacitor and an inverter;

[0036] The power module is equipped with a driver board and a first turn-off semiconductor device; the driver board is connected to the main controller; the driver board has a second FPGA chip inside; the first turn-off semiconductor device is equipped with switching transistors S1, S2, S3 and S4.

[0037] The driver board is used to generate PWM waves; switching transistors S1, S2, S3, and S4 are used to receive PWM waves.

[0038] The first FPGA chip is connected to the second FPGA chip; the first FPGA chip is used for zero drift processing of analog signals.

[0039] The second FPGA chip is connected to the fiber optic board via LVDS traces on the backplane.

[0040] The fiber optic board is connected to the unit driver board via transmit and receive optical fibers.

[0041] The ZYNQ-based static var compensator provided in this embodiment integrates functions that previously required multiple chips into a single chip, resulting in a simpler and more flexible embedded system structure, facilitating system maintenance and upgrades. Furthermore, data is no longer transmitted via an external bus but is processed directly within the chip. Consequently, the chip boasts high hardware integration and a small size, significantly improving the efficiency of simultaneously developing data processing and control functions in an integrated environment, and comprehensively optimizing system stability and real-time performance.

[0042] Reference Figure 1 The diagram shows the main circuit topology of a star-connected chain SVG device. The basic principle of a Static Var Compensator (SVG) is to connect a voltage source inverter in parallel with the power grid via a reactor. The voltage source inverter consists of a DC capacitor and an inverter, which is composed of IGBTs (Inverter Gate Bipolar Transistors). During operation, the amplitude and phase of the SVG's output voltage can be controlled by adjusting the switching of the IGBTs in the inverter. The entire SVG can be considered equivalent to a phase-shifting power supply; by detecting the reactive power required in the system, it can quickly generate reactive power of equal magnitude but opposite nature, achieving dynamic reactive power compensation. The chain topology greatly improves the reliability, flexibility, and maintainability of the SVG.

[0043] Reference Figure 2 The diagram shows the topology of a chain-type SVG power module. The power module adopts a full-bridge H-type topology. Each power module is equipped with a driver board with an attached FPGA chip. This driver board communicates with the controller, receiving control commands, modulation waves, carrier waves, and other communication data from the controller. The driver board then generates PWM waves to control the on / off switching of the S1, S2, S3, and S4 switches of the IGBT devices in the power module, thereby achieving dynamic reactive power compensation. Here, FPGA refers to a Field-Programmable Gate Array. The driver board samples the DC voltage and temperature of the power module locally and sends them, along with simple logic judgments regarding power module faults, to the controller for protection and control logic judgments. The modular hardware and software design allows for flexible configuration of protection functions to meet the needs of different users.

[0044] The SVG controller communication system architecture is mainly implemented using a host computer + ZYNQ + extended FPGA approach, referring to... Figure 3 The diagram shows the overall architecture of the chain-type SVG device, which mainly includes communication within the ZYNQ chip, communication between ZYNQ and the on-board high-capacity FPGA2, communication between FPGA2 and six fiber optic boards, and communication between the fiber optic boards and the power module driver board. ZYNQ refers to a SoC (System-on-a-Chip) that integrates an FPGA and an ARM (microprocessor).

[0045] The Master plugin primarily handles communication between the host computer and the ZYNQ system, as well as interface functions for debugging tools. Through the human-machine interface module, it communicates with the touchscreen and the backend monitoring system, issuing control commands and displaying test results. It acts as the external interface for the controller device, supporting standard Ethernet, IEC61850 / 103 / MODUS, and RS485 protocols, along with optical port B-code time synchronization. Data transmission between the host computer and the ARM (microprocessor) is achieved via RS485 serial asynchronous communication using the Modbus protocol. The host computer synchronously displays test results to the monitoring backend via gigabit Ethernet. If the Master plugin malfunctions, communication between the SVG control device and the HMI is interrupted, preventing the HMI from issuing new commands to the SVG control device. The input / output plugins mainly include 24 channels of 24V input, 24 channels of 220V / 110V input, and 32 channels of non-holding output, which are hard nodes controlled by the CPU board via the internal CAN network.

[0046] The ZYNQ chip and the extended high-capacity FPGA2 (second FPGA chip) are designed on a single CPU hardware board. The Zynq-7015 system-on-a-chip effectively integrates an ARM processing system (PS) and FPGA programmable logic (PL), with a maximum frequency of 766MHz and support for 6.25G high-speed SerDes. The PS and PL communicate via an AXI (Advanced eXtensible Interface) bus, which includes four AXI_HP (AXI HighPerformance Port) high-performance interfaces, an AXI_ACP (AXI Accelerator Coherency Port) bus, and four AXI_GP (AXI General Purpose Port) general-purpose interfaces. The ACP used is a 64-bit slave interface on the Snoop Control Unit (SCU), implementing an asynchronous cache coherency access point from the PL to the PS. The ACP provides a low-latency link between the accelerator implemented in the PL and the PS, thereby improving overall system performance, reducing power consumption, and simplifying software. ARM0 primarily handles data communication management and information interaction through two interrupts (100µs interrupt and 1ms interrupt), parsing commands issued by the host computer and data sent by FPGA2. ARM1 is designed as the internal algorithm processing core, where all SVG control functions are processed. It uses a 50µs interrupt to complete the calculation of the SVG-related control loop, mainly through the algorithm module to generate the modulation wave used to generate the PWM wave.

[0047] FPGA1 (the first FPGA chip) is responsible for ADC sampling control, remote sampling control, analog quantity zero drift processing, basic configuration of ARM0 and ARM1, interrupt generation, and data transmission with FPGA2. Up to 48 local AD samples are used to collect electrical quantities at relevant measurement points on the main circuit. Remote current sampling encodes the analog data collected by the local sampling board into 8b and 10b values ​​and sends it to FPGA1 for decoding via optical fiber.

[0048] The M-GBE2 gigabit port is developed as a coordination redundancy interface, connecting to another SVG controller. This allows for failover when the main controller fails, enabling the SVG device to continue operating without downtime. The M-GBE3 communicates with the waveform recording module via its gigabit port, uploading waveform data to the waveform recording board for storage. This data primarily includes analog signal acquisition data (including data generated by RTSIM), data calculated by RAM1, and DC voltage and fault status words from FPGA2. RAM0 reserves some analog signal and 10-channel digital signal data for visualization analysis during function development and fault analysis. RTSIM refers to the real-time simulation system.

[0049] ZYNQ communicates with FPGA2 via two internal Gigabit ports, GBE0 and GBE1, which are routed on the board. The packet data structure in the Gigabit port communication protocol is as follows: destination MAC address, source MAC address, packet type, packet length, data type, data length, data, packet counter, and CRC checksum. GBE0 relays communication between FPGA2 and ARM0 via FPGA1. The communication content mainly includes configuration information sent by RAM0 and master waveform recording data sent by FPGA2. GBE1 is responsible for establishing communication between FPGA2 and FPGA1, and forwarding it to ARM1. The content includes the modulation wave generated by the control loop algorithm sent by ARM1, and receiving status feedback words, FT3 analog acquisition values, RTSIM acquisition values, etc. sent by FPGA2.

[0050] The FPGA1 chip in the ZYNQ chip has a small capacity and cannot support the development of all control functions. It also supports a limited number of interfaces. FPGA2 is a 300K capacity CycloneV series expansion chip, including algorithm, logic judgment, data storage, data acquisition, and communication modules, responsible for implementing most of the functions of the test system. It undertakes the development of some control algorithm functions, most of the fast protection fault judgment logic, and communication forwarding functions. Specific functions include phase voltage equalization calculation based on the direct voltage of each power unit, generating the carrier wave of each power module through a carrier phase shifting algorithm, generating the modulation wave of each power module through a voltage equalization loop algorithm, and implementing the fault unit bypass function. Due to various limitations, the single control chassis can only support a maximum of 48 power modules per phase. When the number of chains per phase of the SVG is greater than 48 chains but less than 96 chains, an expansion chassis is required. The two gigabit ports, GBE2 and GBE4, are used to connect to the expansion device to forward the control parameters and modulation waves sent by ZYNQ. At the same time, they receive fault information and unit direct voltage from the expansion chassis, which are then summarized in FPGA2 of the main chassis and sent to ZYNQ. The GBE3 gigabit port communicates with the hardware-in-the-loop (HIL) real-time simulation system, interacting with simulation data for functional development and fault analysis. The HIL real-time simulation system uses the Simulink real-time kernel in MATLAB to simulate the main circuit model. An FPGA is used to simulate data from all power modules in parallel using algorithms. The GBE3 interface connects the SVG controller to the main circuit, enabling real-time simulation of the controller's operation within the main circuit. Four FT3 interfaces are used to connect external devices conforming to the FT3 industry standard protocol, primarily for coordinating master-slave control functions.

[0051] FPGA2 communicates with six fiber boards via 36 pairs of LVDS backplane traces. Two fiber boards are used for each of the three phases (A, B, and C). LVDS communication uses 8b10b encoding / decoding, with a data rate of 48M / s. The main function of the fiber boards is data aggregation and relay, and they include simple communication fault diagnosis logic. Upward, the fiber boards receive configuration data, carrier waves, and modulation waves from FPGA2 via LVDS and transmit local floor data information to the units. Downward, each fiber board uses 24 pairs of transceiver fibers (24*fiber) to communicate point-to-point with 24 unit driver boards (24*cell), receiving unit fault information and unit direct voltage, and transmitting control information, carrier waves, and modulation waves. The fiber boards and local driver boards use 8b10b encoding / decoding, with a data rate of 3M / s.

[0052] Traditional SVG device communication system architecture includes four CPU boards (one main controller and three phase controllers) to perform the same function. Each CPU board contains one DSP and one FPGA, resulting in a complex communication architecture that wastes significant chip resources. The ZYNQ-based static var compensator provided in this embodiment adopts a ZYNQ-based communication system architecture, which fully combines the advantages of both ARM and FPGA in data computation and processing. This makes the embedded system structure more flexible and simple, and chip resource utilization more efficient. Data is processed directly within the chip, which is more stable and faster than external data transmission, effectively improving system reliability and performance. Gigabit Ethernet communication replaces part of the original 48M / s 8b10b codec communication, fully utilizing the advantages of Gigabit Ethernet technology to greatly improve data communication speed and real-time data processing, effectively improving device compatibility and overall performance. The SVG controller functions are integrated into a single ZYNQ chip. The FPGA accelerates and parallelizes the data processing, while the ARM optimizes the control algorithm to reduce the system's computational complexity. The control system is then developed synchronously through a hardware and software fusion approach, striving for comprehensive optimization in terms of device cost, system performance, development efficiency, and real-time performance.

[0053] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A static var compensator based on ZYNQ, characterized in that, include: Main controller; And a voltage source inverter, reactor, power module and ZYNQ module connected to the main controller; The ZYNQ module is equipped with a microprocessor, a ZYNQ chip, and a first FPGA chip. The voltage source inverter includes: a DC capacitor and an inverter; The power module is equipped with a driver board and a first turn-off semiconductor device; the driver board is connected to the main controller; the driver board has a second FPGA chip inside; the first turn-off semiconductor device is equipped with switching transistors S1, S2, S3 and S4. The driver board is used to generate PWM waves; the switching transistors S1, S2, S3 and S4 are used to receive the PWM waves. The first FPGA chip is connected to the second FPGA chip; the first FPGA chip is used for zero drift processing of analog signals. The second FPGA chip is connected to the fiber optic board via LVDS traces on the backplane; The fiber optic board is connected to the unit driver board via transceiver fibers. The ZYNQ chip and the second FPGA chip are integrated on a single CPU hardware board. The ZYNQ chip and the second FPGA chip are connected by an AXI bus.

2. The static var compensator based on ZYNQ as described in claim 1, characterized in that, The inverter is equipped with a second turn-off semiconductor device.

3. The static var compensator based on ZYNQ as described in claim 1, characterized in that, The AXI bus includes: four AXI_HP high-performance interfaces, an AXI_ACP bus, and four AXI_GP general-purpose interfaces.

4. A static var compensator based on ZYNQ as described in claim 3, characterized in that, The AXI_ACP bus is a 64-bit slave interface on the Consistent Storage Control Unit (SCU).

5. A static var compensator based on ZYNQ as described in claim 1, characterized in that, The microprocessor consists of two ARM processors; one ARM processor is used to parse the instructions sent by the host computer and the data sent by the second FPGA chip; the other ARM processor is used to generate the modulation wave that produces the PWM wave.

6. A static var compensator based on ZYNQ as described in claim 1, characterized in that, The first FPGA chip is used to receive encoded analog data through the optical fiber board and decode the analog data.

7. A static var compensator based on ZYNQ as described in claim 1, characterized in that, Also includes: The M-GBE2 gigabit port connects to another SVG controller, enabling a switchover between the primary and backup controllers when the primary controller malfunctions.

8. A static var compensator based on ZYNQ as described in claim 1, characterized in that, The second FPGA chip has four gigabit ports and four FT3 interfaces.

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