Dynamic random access memory structure

Abstract

A dynamic random access memory structure includes at least one memory cell. The memory cell includes a substrate, a gate structure, a first capacitor, a first bit line structure, a second capacitor, and a second bit line structure. The substrate has opposing first and second faces. The gate structure extends through the substrate. The first capacitor is on the first face of the substrate. The first bit line structure is on the second face of the substrate. The second capacitor is on the second face of the substrate. The second bit line structure is on the first face of the substrate.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure, and more particularly to a dynamic random access memory (DRAM) structure. BACKGROUND

[0002] A dynamic random access memory including a transistor and a capacitor has been developed. In such a dynamic random access memory, the capacitor is used as a storage node. However, how to further improve the bit density, electrical performance and operation speed of the memory element is a continuous effort. SUMMARY

[0003] The present invention provides a dynamic random access memory structure which can effectively improve the bit density, electrical performance and operation speed of the memory element.

[0004] The present invention provides a dynamic random access memory structure including at least one memory cell. The memory cell includes a substrate, a gate structure, a first capacitor, a first bit line structure, a second capacitor and a second bit line structure. The substrate has opposite first and second surfaces. The gate structure extends through the substrate. The first capacitor is located on the first surface of the substrate. The first bit line structure is located on the second surface of the substrate. The second capacitor is located on the second surface of the substrate. The second bit line structure is located on the first surface of the substrate.

[0005] According to an embodiment of the present invention, in the above dynamic random access memory structure, the substrate can include a first channel region and a second channel region. The first channel region is located between the first capacitor and the first bit line structure. The second channel region is located between the second capacitor and the second bit line structure.

[0006] According to an embodiment of the present invention, in the above dynamic random access memory structure, the memory cell can further include an isolation structure. The isolation structure is located in the substrate. The first channel region can be located at one side of the gate structure and between the gate structure and the isolation structure. The second channel region can be located at the other side of the gate structure and between the gate structure and the isolation structure.

[0007] According to an embodiment of the present invention, in the above dynamic random access memory structure, the gate structure can include a gate and a dielectric layer. The gate is located in the substrate. The dielectric layer is located between the gate and the substrate.

[0008] According to an embodiment of the present invention, in the above dynamic random access memory structure, the gate can have a top view shape of a strip or with branches.

[0009] According to an embodiment of the present application, in the dynamic random access memory structure, the dielectric layer can surround the gate.

[0010] According to an embodiment of the present application, in the dynamic random access memory structure, the first capacitor and the first bit line structure can be located at one side of the gate structure, and the second capacitor and the second bit line structure can be located at the other side of the gate structure.

[0011] According to an embodiment of the present application, in the dynamic random access memory structure, the first bit line structure can include a first bit line and a first contact window. The first bit line is located on the second surface of the substrate. The first contact window is located between the first bit line and the substrate. The second bit line structure can include a second bit line and a second contact window. The second bit line is located on the first surface of the substrate. The second contact window is located between the second bit line and the substrate.

[0012] According to an embodiment of the present application, in the dynamic random access memory structure, the first bit line and the second bit line can have a straight shape or a zigzag shape.

[0013] According to an embodiment of the present application, in the dynamic random access memory structure, the memory cell can further include a first contact window and a second contact window. The first contact window is located between the first capacitor and the substrate. The second contact window is located between the second capacitor and the substrate.

[0014] Based on the above, in the dynamic random access memory structure according to the present application, the gate structure penetrates the substrate, the first capacitor is located on the first surface of the substrate, the first bit line structure is located on the second surface of the substrate, the second capacitor is located on the second surface of the substrate, and the second bit line structure is located on the first surface of the substrate. Therefore, a single memory cell can have two bits, thereby improving the bit density of the memory element. In addition, since the first capacitor and the second capacitor are located on different surfaces of the substrate, the area of the first capacitor and the area of the second capacitor can be improved. Thus, the capacitance of the first capacitor and the capacitance of the second capacitor can be improved, thereby improving the electrical performance of the memory element. Furthermore, since the two bits in the memory cell share the gate structure (i.e., a single gate structure can control two bits), the two bits in the memory cell can be operated (e.g., read operation) at the same time, thereby improving the operation speed of the memory element.

[0015] In order to make the above features and advantages of the present application more apparent, the following embodiments are described in detail below, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A perspective view of a dynamic random access memory structure according to some embodiments of the present application;

[0017] Figure 2 Cross-sectional schematic view of a dynamic random access memory structure for some embodiments of the invention;

[0018] Figure 3 Top view schematic of a dynamic random access memory structure for some embodiments of the invention;

[0019] Figure 4 Top view schematic of a dynamic random access memory structure for some embodiments of the invention.

[0020] Symbol explanation

[0021] 100: dynamic random access memory structure

[0022] 102: substrate

[0023] 104: gate structure

[0024] 106, 110: capacitor

[0025] 108, 112: bit line structure

[0026] 114: isolation structure

[0027] 116: gate

[0028] 118, 126, 146, 148, 150, 152: dielectric layer

[0029] 120: barrier layer

[0030] 122, 124, 124a, 124b, 134, 136, 136a, 136b: electrode

[0031] 126, 138: insulating layer

[0032] 128, 132, 140, 144: contact

[0033] 130, 142: bit line

[0034] B1, B2: bit

[0035] C1, C2: channel region

[0036] D1, D2: direction

[0037] MC: memory cell

[0038] ML: length

[0039] MW: width

[0040] S1: first surface

[0041] S2: second surface Detailed Implementation

[0042] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, features in the perspective view, top view, and sectional view are not drawn to the same scale. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0043] Figure 1 This is a three-dimensional schematic diagram of a dynamic random access memory structure according to some embodiments of the present invention. Figure 2 This is a cross-sectional schematic diagram of a dynamic random access memory structure according to some embodiments of the present invention. Figure 3 This is a top view schematic diagram of a dynamic random access memory structure according to some embodiments of the present invention. Furthermore, Figure 2 For along Figure 3 A cross-sectional view of the I-I' section line in the diagram. Figure 4 This is a top view schematic diagram of a dynamic random access memory structure according to other embodiments of the present invention. Furthermore, in Figure 1 , Figure 3 and Figure 4 in, omit Figure 2 Some components are clearly explained. Figure 1 , Figure 3 and Figure 4 The positional relationship between the various components.

[0044] Please refer to Figures 1 to 4 The dynamic random access memory (DRAM) architecture 100 includes at least one memory cell MC. In this embodiment, the DRAM architecture 100 is based on a plurality of memory cells MC ( Figure 3 and Figure 4 Let's take a memory cell MC as an example. The memory cell MC includes a substrate 102, a gate structure 104, a capacitor 106, a bit line structure 108, a capacitor 110, and a bit line structure 112. The substrate 102 has opposing first surfaces S1 and second surfaces S2. The substrate 102 can be a semiconductor substrate, such as a silicon substrate.

[0045] Furthermore, substrate 102 may include channel region C1 and channel region C2. Channel region C1 is located between capacitor 106 and bit line structure 108. Channel region C2 is located between capacitor 110 and bit line structure 112. Additionally, the memory cell MC may also include an isolation structure 114. Isolation structure 114 is located within substrate 102. Isolation structure 114 may define an active region AA within substrate 102. Figure 3 andFigure 4 In some embodiments, the active region AA may be a parallelogram (…). Figure 3 ) or rectangle ( Figure 4 However, the present invention is not limited thereto. Channel region C1 may be located on one side of gate structure 104 and may be located between gate structure 104 and isolation structure 114. Channel region C2 may be located on the other side of gate structure 104 and may be located between gate structure 104 and isolation structure 114. Isolation structure 114 is, for example, a shallow trench isolation (STI) structure. The material of isolation structure 114 may be, for example, silicon oxide, silicon nitride, or a combination thereof.

[0046] Please refer to Figure 1 and Figure 2 A gate structure 104 extends through a substrate 102. The gate structure 104 may include a gate 116 and a dielectric layer 118. The gate 116 is located within the substrate 102. The gate 116 may be a vertical gate. For example, in channel region C1, current may flow in a direction D1 perpendicular to the surface of the substrate 102 (e.g., the first surface S1). Furthermore, in channel region C2, current may flow in a direction D2 perpendicular to the surface of the substrate 102 (e.g., the first surface S1). The material of the gate 116 is, for example, a conductive material such as a metal (e.g., tungsten). The dielectric layer 118 is located between the gate 116 and the substrate 102. The dielectric layer 118 may serve as a gate dielectric layer. In some embodiments, the dielectric layer 118 may surround the gate 116. The dielectric layer 118 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 118 is, for example, silicon oxide, silicon nitride, or a combination thereof. Additionally, the gate structure 104 may also include a barrier layer 120. A barrier layer 120 is located between the gate 116 and the dielectric layer 118. In some embodiments, the barrier layer 120 may surround the gate 116, but the invention is not limited thereto. The material of the barrier layer 120 is, for example, titanium, titanium nitride, or a combination thereof.

[0047] Please refer to Figure 3 and Figure 4 The top view shape of gate 116 can be strip-shaped. Figure 3 ) or has branches ( Figure 4 The top view of gate 116 has branches (). Figure 4 In the case of a gate 116 branch, the branch can surround part of the channel region C1 and part of the channel region C2, thereby increasing the channel width.

[0048] Please refer to Figures 1 to 4Capacitor 106 is located on the first surface S1 of substrate 102. Capacitor 106 can serve as a storage node of storage cell MC. Capacitor 106 can be various capacitors suitable for dynamic random access memory (e.g., cylinder capacitor). In some embodiments, capacitor 106 may include electrode 122, electrode 124, and insulating layer 126. Figure 2 Electrode 122 is located on the first surface S1 of substrate 102. The material of electrode 122 is, for example, titanium, titanium nitride, or a combination thereof. Electrode 124 is located on electrode 122. Electrode 124 can be a single-layer structure or a multi-layer structure. In this embodiment, electrode 124 can be a multi-layer structure including electrode 124a and electrode 124b, but the invention is not limited thereto. Electrode 124a is located on electrode 122. The material of electrode 124a is, for example, titanium, titanium nitride, or a combination thereof. Electrode 124b is located on electrode 124a. The material of electrode 124b is, for example, a doped semiconductor material, such as boron-doped silicon germanium (SiGe) or doped polycrystalline silicon. Insulating layer 126 is located between electrode 122 and electrode 124. The material of insulating layer 126 can be a dielectric material, such as a high-k material.

[0049] Please refer to Figures 1 to 4 The memory cell MC may also include a contact window 128. The contact window 128 can be used as a contact window for the memory node. The contact window 128 is located between the capacitor 106 and the substrate 102. The material of the contact window 128 is, for example, a conductive material such as doped polysilicon.

[0050] Please refer to Figure 1 and Figure 2 The bitline structure 108 is located on the second surface S2 of the substrate 102. The bitline structure 108 may include a bitline 130 and a contact window 132. The bitline 130 and the contact window 132 may be integrally formed or separate components. The bitline 130 is located on the second surface S2 of the substrate 102. The material of the bitline 130 is, for example, a conductive material such as a metal (e.g., tungsten). The contact window 132 is located between the bitline 130 and the substrate 102. The material of the contact window 132 is, for example, doped polycrystalline silicon or a conductive material such as a metal (e.g., tungsten).

[0051] Please refer to Figure 1 and Figure 2 The capacitor 110 is located on the second surface S2 of the substrate 102. The capacitor 110 can serve as a storage node of the storage cell MC. The capacitor 110 can be a capacitor suitable for dynamic random access memory (e.g., a cylindrical capacitor). In some embodiments, the capacitor 110 may include electrodes 134 and 136 and an insulating layer 138. Figure 2Electrode 134 is located on the second surface S2 of substrate 102. The material of electrode 134 is, for example, titanium, titanium nitride, or a combination thereof. Electrode 136 is located on electrode 134. Electrode 136 can be a single-layer or multi-layer structure. In this embodiment, electrode 136 can be a multi-layer structure including electrode 136a and electrode 136b, but the invention is not limited thereto. Electrode 136a is located on electrode 134. The material of electrode 136a is, for example, titanium, titanium nitride, or a combination thereof. Electrode 136b is located on electrode 136a. The material of electrode 136b is, for example, a doped semiconductor material, such as boron-doped silicon-germanium or doped polycrystalline silicon. Insulating layer 138 is located between electrode 134 and electrode 136. The material of insulating layer 138 can be a dielectric material, such as a high dielectric constant material.

[0052] Please refer to Figure 1 and Figure 2 The memory cell MC may also include a contact window 140. The contact window 140 can be used as a contact window for the memory node. The contact window 140 is located between the capacitor 110 and the substrate 102. The material of the contact window 140 is, for example, a conductive material such as doped polysilicon.

[0053] Please refer to Figures 1 to 4 The bitline structure 112 is located on the first surface S1 of the substrate 102. The bitline structure 112 may include a bitline 142 and a contact window 144. The bitline 142 and the contact window 144 may be integrally formed or separate components. The bitline 142 is located on the first surface S1 of the substrate 102. The material of the bitline 142 is, for example, a conductive material such as a metal (e.g., tungsten). The contact window 144 is located between the bitline 142 and the substrate 102. The material of the contact window 144 is, for example, doped polycrystalline silicon or a conductive material such as a metal (e.g., tungsten).

[0054] like Figure 2 As shown, capacitor 106 and bit line structure 108 can be located on one side of gate structure 104, and capacitor 110 and bit line structure 112 can be located on the other side of gate structure 104. Furthermore, contact window 128 and contact window 132 can be located on the same side of gate structure 104, and contact window 140 and contact window 144 can be located on the same side of gate structure 104. Alternatively, contact window 128 and contact window 140 can be located on different sides of gate structure 104, and contact window 132 and contact window 144 can be located on different sides of gate structure 104.

[0055] Please refer to Figure 3 and Figure 4 The top view shape of position line 142 can be a straight line. Figure 3 ) or zigzag ( Figure 4 In addition, in Figure 3 and Figure 4 Although bit line 130 is not shown in the diagram, its top view shape can be referenced.Figure 3 and Figure 4 The top view shape of bit line 142. That is, the top view shape of bit line 130 can be straight or zigzag.

[0056] Please refer to Figure 2 The memory cell MC may further include at least one of dielectric layer 146, dielectric layer 148, dielectric layer 150, and dielectric layer 152. Dielectric layer 146 is located between contact window 128 and bit line 142. Dielectric layer 148 is located between capacitor 106 and bit line 142, and between capacitor 106 and dielectric layer 146. Dielectric layer 150 is located between contact window 140 and bit line 130. Dielectric layer 152 is located between capacitor 110 and bit line 130, and between capacitor 110 and dielectric layer 150. The material of dielectric layer 146, dielectric layer 148, dielectric layer 150, and dielectric layer 152 is, for example, silicon nitride.

[0057] In addition, the dynamic random access memory structure 100 may also include other required dielectric layers (for isolation) and / or other required interconnect structures (for electrical connection), the description of which is omitted here.

[0058] In this embodiment, please refer to Figure 3 If half of the minimum spacing between components is set as F, then the length ML of the storage cell MC is approximately 4F, the width MW of the storage cell MC is approximately 2F, and the area of ​​the storage cell MC is approximately 8F. 2 (=4F×2F). However, since the memory cell MC can have two bits (bit B1 and bit B2) Figure 1 and Figure 2 Therefore, the average bit size of the memory cell MC is approximately 4F. 2 (=8F 2 / 2). In this way, the memory cell MC can have a smaller bit size, thereby increasing the bit density of the memory element. Furthermore, since the area of ​​the memory cell MC is approximately 8F... 2 Therefore, the usable area of ​​capacitors 106 and 110 located on different surfaces of substrate 102 is approximately 8F. 2 That is, capacitors 106 and 110 can have a large area. This can increase the capacitance of capacitor 106 and the capacitance of capacitor 110.

[0059] As can be seen from the above embodiments, in the dynamic random access memory structure 100, the gate structure 104 penetrates the substrate 102, the capacitor 106 is located on the first surface S1 of the substrate 102, the bit line structure 108 is located on the second surface S2 of the substrate 102, the capacitor 110 is located on the second surface S2 of the substrate 102, and the bit line structure 112 is located on the first surface S1 of the substrate 102. Therefore, a single memory cell MC can have two bits, thereby increasing the bit density of the memory element. Furthermore, since the capacitor 106 and the capacitor 110 are located on different surfaces of the substrate 102, it is beneficial to increase the area of ​​the capacitor 106 and the area of ​​the capacitor 110. As a result, the capacitance of the capacitor 106 and the capacitance of the capacitor 110 can be increased, thereby improving the electrical performance of the memory element. In addition, since the two bits (bit B1 and bit B2) in the memory cell MC share the gate structure 104 (that is, a single gate structure 104 can control two bits), the two bits in the memory cell MC can be operated on simultaneously (e.g., read operation), thereby improving the operating speed of the memory element.

[0060] In summary, in the dynamic random access memory structure of the above embodiments, since the two bits in the memory cell share a common gate structure and the two capacitors in the memory cell are located on different surfaces of the substrate, the bit density, electrical performance and operating speed of the memory element can be effectively improved.

[0061] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A dynamic random access memory (DRAM) structure, comprising at least one memory cell, wherein the memory cell comprises: The base has a first surface and a second surface that are opposite to each other; A gate structure extends through the substrate; A first capacitor is located on the first surface of the substrate; The first line structure is located on the second surface of the substrate; A second capacitor is located on the second surface of the substrate; as well as The second bit line structure is located on the first surface of the substrate.

2. The dynamic random access memory structure as described in claim 1, wherein the substrate comprises: The first channel region is located between the first capacitor and the first bit line structure; as well as The second channel region is located between the second capacitor and the second bit line structure.

3. The dynamic random access memory structure as described in claim 2, wherein the memory unit further comprises: An isolation structure is located in the substrate, wherein The first channel region is located on one side of the gate structure and between the gate structure and the isolation structure. The second channel region is located on the other side of the gate structure and between the gate structure and the isolation structure.

4. The dynamic random access memory structure as described in claim 1, wherein the gate structure comprises: The gate is located in the substrate; as well as A dielectric layer is located between the gate and the substrate.

5. The dynamic random access memory structure of claim 4, wherein the top view shape of the gate includes a strip or has branches.

6. The dynamic random access memory structure of claim 4, wherein the dielectric layer surrounds the gate.

7. The dynamic random access memory structure as described in claim 1, wherein... The first capacitor and the first bit line structure are located on one side of the gate structure, and The second capacitor and the second bit line structure are located on the other side of the gate structure.

8. The dynamic random access memory structure as described in claim 1, wherein... The first bit line structure includes: The first line is located on the second surface of the substrate; as well as The first contact window is located between the first bit line and the substrate, and The second bit line structure includes: The second bit line is located on the first surface of the substrate; as well as The second contact window is located between the second bit line and the substrate.

9. The dynamic random access memory structure as described in claim 8, wherein the top view shape of the first bit line and the top view shape of the second bit line include a straight line or a zigzag shape.

10. The dynamic random access memory structure as described in claim 1, wherein the memory unit further comprises: A first contact window is located between the first capacitor and the substrate; as well as The second contact window is located between the second capacitor and the substrate.

Images