Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a first semiconductor layer, the first semiconductor layer comprising a first part and a second part located on opposite sides of the first part, the first part being bent away from the second part to form an opening; a first gate electrode located in the opening; and a dielectric layer located on at least one side surface of the second part; wherein the first part is used to form a first channel region of a first transistor, and the second part on opposite sides of the first channel region is used to form a first source contact region or a first drain contact region. The semiconductor structure and the manufacturing method thereof provided by the embodiment of the present disclosure can improve the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a well-known semiconductor memory device, which is widely used in various electronic devices. Dynamic random access memory (DRAM) is composed of many repeated memory cells, each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell is electrically connected to each other through a word line (WL) and a bit line (BL).

[0003] However, with the development of semiconductor technology, miniaturization of semiconductor devices is still a goal, and the size of semiconductor devices is further reduced, and the requirements for their performance are also higher and higher. Therefore, at present, while reducing the size of semiconductor devices, it is still necessary to improve the performance of semiconductor structures. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which at least have advantages of improving the performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a semiconductor structure, comprising: a first semiconductor layer, the first semiconductor layer comprising a first part and a second part located on opposite sides of the first part, the first part being bent away from the second part to form an opening; a first gate electrode located in the opening; and a dielectric layer located on at least one side surface of the second part; wherein the first part is used to form a first channel region of a first transistor, and the second parts on opposite sides of the first channel region are used to form a first source contact region or a first drain contact region.

[0006] In some embodiments, the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer is located on the surface of the second part, and the second dielectric layer is located on the surface of the first dielectric layer away from the second part, the density of the first dielectric layer is greater than the density of the second dielectric layer.

[0007] In some embodiments, the material of the first dielectric layer comprises silicon nitride, and the material of the second dielectric layer comprises silicon oxide.

[0008] In some embodiments, the first gate includes a first gate dielectric layer and a first gate conductive layer, the first gate dielectric layer covers the surface of the opening, and the first gate conductive layer covers the surface of the first gate dielectric layer and fills the opening, the dielectric constant of the first gate dielectric layer is greater than the dielectric constant of the second dielectric layer.

[0009] In some embodiments, the material of the first gate dielectric layer includes at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide, or titanium oxide.

[0010] In some embodiments, the material of the first semiconductor layer includes indium gallium zinc oxide.

[0011] In some embodiments, the plurality of first semiconductor layers are arranged along a first direction, and each first semiconductor layer includes at least two first portions along the first direction, each first portion having a first gate in the opening thereof.

[0012] In some embodiments, the plurality of first semiconductor layers are arranged along a second direction, and the plurality of first gates are connected to each other along the second direction.

[0013] In some embodiments, the plurality of first semiconductor layers are arranged along a first direction and a second direction, and adjacent first semiconductor layers are spaced apart from each other, each first semiconductor layer having a first gate in the opening thereof; wherein the first gate of at least one first transistor is electrically connected to the first source contact region or the first drain contact region of another first transistor.

[0014] In some embodiments, the semiconductor structure further includes: a second gate electrically connected to the first source contact region or the first drain contact region at one end and extending away from the first semiconductor layer at the other end; and a second semiconductor layer located on the surface of the second gate away from the first semiconductor layer, the second semiconductor layer including a third portion and fourth portions located on opposite sides of the third portion, the third portion covering the surface of the second gate; wherein the third portion is used to form a second channel region of a second transistor, and the fourth portions are used to form a second source contact region or a second drain contact region of the second transistor.

[0015] In some embodiments, the material of the second semiconductor layer is the same as the material of the first semiconductor layer.

[0016] In some embodiments, the first transistor and the second transistor jointly form a memory cell, and the memory cells are arranged along the first direction and the second direction.

[0017] In some embodiments, the second gate includes a second gate dielectric layer and a second gate conductive layer, one end of the second gate conductive layer is electrically connected with the first source contact region or the first drain contact region, the other end of the second gate conductive layer extends in a direction away from the first source contact region or the first drain contact region, and the second gate dielectric layer covers a side surface of the second gate conductive layer away from the first source contact region or the first drain contact region, wherein the second gate dielectric layers in different second transistors are in the same layer and the edges thereof extend to each other.

[0018] In some embodiments, the first gate includes a first gate dielectric layer and a first gate conductive layer, the first gate dielectric layer covers a surface of the opening, and the first gate conductive layer covers a surface of the first gate dielectric layer and fills the opening; wherein the material of the second gate dielectric layer is the same as the material of the first gate dielectric layer.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a first semiconductor layer on the substrate, the first semiconductor layer including a first part and second parts located on opposite sides of the first part, the first part being bent in a direction away from the second parts to form an opening; forming a first gate in the opening; and forming a dielectric layer on at least one side surface of the second parts; wherein the first part is used to form a first channel region of a first transistor, and the second parts on opposite sides of the first part are used to form a first source contact region or a first drain contact region.

[0020] In some embodiments, the forming of the first semiconductor layer on the substrate includes: forming a plurality of first semiconductor layers arranged in a first direction and a second direction, each of the first semiconductor layers including at least two first parts in the first direction; and the forming of the first gate includes: forming a first gate in the opening of each of the first parts, and in the second direction, the plurality of first gates are connected to each other.

[0021] In some embodiments, after the forming of the first gate, the method further includes: forming a second gate having one end electrically connected with the first source contact region or the first drain contact region and the other end extending in a direction away from the substrate surface; and forming a second semiconductor layer on a side surface of the second gate away from the first semiconductor layer, the second semiconductor layer including a third part and fourth parts located on opposite sides of the third part, and the third part covering a surface of the second gate; wherein the third part is used to form a second channel region of a second transistor, and the fourth parts are used to form a second source contact region or a second drain contact region of the second transistor.

[0022] The technical scheme provided by the embodiment of the present disclosure has at least the following advantages: the first semiconductor layer in the semiconductor structure provided by the embodiment includes a first part and a second part, the first part is bent in a direction away from the second part to form an opening, the first gate is in the opening, the first gate and the first semiconductor layer are used to form a first transistor, the first part is used to form a first channel region of the first transistor, the bent opening can increase the contact area of the first channel region and the first gate, improve the gate control capability of the first transistor, and using the first semiconductor layer as the semiconductor channel of the first transistor can be beneficial to improve the moving speed of the carriers and reduce the channel resistance.

[0023] In addition, the second part is used to form a first source contact region or a first drain contact region, that is, the surface of the second part is used to form a contact structure to connect a bit line or a capacitor, and the dielectric layer is located on at least one side surface of the second part, for example, the dielectric layer can be located on the side surface opposite to the contact structure of the second part, or on the two side surfaces opposite to the second part, so that the contact structure is arranged in the dielectric layer, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part, and improving the stability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0024] One or more embodiments are illustrated by way of example in the drawings that are for illustrative purposes only, and not for the purposes of limitation of the embodiments, unless otherwise explicitly stated in the specification. The drawings in the accompanying drawings are not necessarily to scale, as is clear to a person of ordinary skill in the art. In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings needed in the embodiments will be briefly described in the following. Obviously, the drawings in the following description should not be confined to the drawings in the present disclosure, and other drawings can be obtained by those skilled in the art without creative work.

[0025] Figures 1 to 16 The various semiconductor structure schematic diagrams provided by an embodiment of the present disclosure are provided.

[0026] Figures 17 to 20 The structure schematic diagrams corresponding to various steps of the manufacturing method of the semiconductor structure provided by another embodiment of the present disclosure are provided. DETAILED DESCRIPTION

[0027] As known from the background, the performance of the semiconductor structure needs to be improved.

[0028] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, which is at least beneficial to improve the performance of the semiconductor structure.

[0029] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are presented in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0030] Figures 1 to 16 The semiconductor structure provided by an embodiment of the present disclosure is described in detail below with reference to the drawings. Specifically, the semiconductor structure provided by the embodiment is described as follows:

[0031] Reference Figures 1 to 4 The semiconductor structure comprises: a first semiconductor layer 101, the first semiconductor layer 101 comprises a first part I and a second part II located on opposite sides of the first part I, and the first part I is bent away from the second part II to form an opening 112; a first gate 102, the first gate 102 is located in the opening 112; and a dielectric layer 103, the dielectric layer 103 is located on at least one side surface of the second part II; wherein the first part I is used to form a first channel region of a first transistor, and the second part II on opposite sides of the first channel region is used to form a first source contact region or a first drain contact region.

[0032] In the semiconductor structure provided by the embodiment, the first semiconductor layer 101 comprises the first part I and the second part II, the first part I is bent away from the second part II to form the opening 112, the first gate 102 is located in the opening 112, the first gate 102 and the first semiconductor layer 101 are used to form the first transistor, the first part I is used to form the first channel region of the first transistor, the bent opening 112 can increase the contact area of the first channel region and the first gate 102, improve the gate control capability of the first transistor, and using the first semiconductor layer 101 as the semiconductor channel of the first transistor can be beneficial to improve the moving speed of the carriers.

[0033] In some embodiments, reference Figures 1 to 4 , Figures 1 to 4 The semiconductor structure provided by an embodiment of the present disclosure is described in detail below with reference to the drawings. Specifically, the semiconductor structure provided by the embodiment is described as follows: Figure 1 The dielectric layer 103 can be located on the second part II surface of the first semiconductor layer 101 on one side of the opening 112; in some embodiments, reference Figure 2 The dielectric layer 103 can be located on the second part II surface of the first semiconductor layer 101 on the opposite side of the opening 112; in some embodiments, reference Figure 3 The dielectric layer 103 can be located on the second part II surface of the first semiconductor layer 101 on opposite sides; in some embodiments, reference Figure 4The medium layer 103 can also wrap the second part II of the first semiconductor layer 101, that is, the medium layer 103 covers the opposite two surfaces of the second part II and the side surface exposed from the side away from the first part I.

[0034] It can be understood that, referring to Figure 5 , Figure 5 The schematic diagram of the contact structure provided by an embodiment of the present disclosure is shown in FIG. 6, and the second part II is used to form the first source contact region or the first drain contact region, that is, the surface of the second part II is used to form the contact structure 104 to connect the bit line or the capacitor. In some embodiments, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure. Figure 5 Figure 5 It should be noted that, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure.

[0035] It should be noted that, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure. Figure 5 It should be noted that, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure.

[0036] It should be noted that, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure.

[0037] Figure 6 It should be noted that, referring to (a) in FIG. 6, taking the surface of the second part II of the first semiconductor layer 101 with the medium layer 103 located on the opposite side as an example, the medium layer 103 can be located on the surface of the side opposite to the contact structure 104; in some embodiments, referring to (b) in FIG. 6, the medium layer 103 is located on the opposite two surfaces of the second part II, so that the contact structure 104 is arranged in the medium layer 103, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part II, so as to improve the stability of the semiconductor structure. Figure 6 Figure 6 ​​​In (a) of FIG. 1, the second part II of the first semiconductor layer 101 is parallel to the surface of the substrate 100, and the first part I is bent in a direction pointing to the substrate 100, and the opening 112 is directed to a direction away from the surface of the substrate 100; or, referring to Figure 6 In (b) of FIG. 1, the second part II of the first semiconductor layer 101 is parallel to the surface of the substrate 100, and the first part I is bent in a direction away from the surface of the substrate 100, and the opening 112 is directed to a direction pointing to the surface of the substrate 100.

[0038] That is, the first semiconductor layer 101 and the substrate 100 can have different positional relationships, and the first transistor with the corresponding structure is formed, so as to increase the diversity of the semiconductor structure, thereby facilitating the selection of a relatively simple semiconductor structure manufacturing process to form the corresponding semiconductor structure, and improving the manufacturing efficiency of the semiconductor structure.

[0039] It should be noted that the positional relationship between the first semiconductor layer 101 and the substrate 100 in the drawings provided by the embodiment is only an example and does not constitute a limitation on the positional relationship between the first semiconductor layer 101 and the substrate 100; in other embodiments, the first semiconductor layer and the substrate can also have other positional relationships.

[0040] In addition, in the drawings of the positional relationship between the first semiconductor layer and the substrate provided by the embodiment, the medium layer 103 is located on the surface of the second part II of the first semiconductor layer 101 on the side of the substrate 100, which is only an example and does not constitute a limitation on the position of the medium layer 103 on the surface of the second part II; in some embodiments, the medium layer can be located on the surface of the second part away from the substrate or wrap the surface of the second part.

[0041] For the substrate, in some embodiments, the substrate includes a substrate and an insulating layer located on the surface of the substrate, and the first semiconductor layer, the medium layer and the first gate are located in the insulating layer above the substrate, so that the substrate and the first semiconductor layer and the first gate can be isolated by the insulating layer, thereby avoiding the phenomenon of electric leakage, so as to improve the stability of the semiconductor structure.

[0042] For the substrate, the material of the substrate can be an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material can be germanium, silicon, selenium, boron, tellurium or antimony; the compound semiconductor material can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide or gallium arsenide silicon, etc.

[0043] For the insulating layer, the material of the insulating layer includes silicon oxide, silicon nitride or silicon oxynitride, etc.

[0044] For the first semiconductor layer 101, in some embodiments, the material of the first semiconductor layer 101 includes Indium Gallium Zinc Oxide (IGZO). When the material of the first semiconductor layer 101 is IGZO, the carrier mobility of IGZO is 20-50 times of the carrier mobility of polysilicon, which can be beneficial to improve the carrier mobility in the semiconductor channel, thereby reducing the leakage current when the semiconductor structure is working, and reducing the power consumption of the semiconductor structure.

[0045] For the dielectric layer 103, in some embodiments, referring to Figure 7 , the dielectric layer 103 includes a first dielectric layer 113 and a second dielectric layer 123, the first dielectric layer 113 is located on the surface of the second part II, and the second dielectric layer 123 is located on the surface of the first dielectric layer 113 away from the second part II, and the density of the first dielectric layer 113 is greater than the density of the second dielectric layer 123. The first dielectric layer 113 is located on the surface of the second part II, and the density of the first dielectric layer 113 is greater than the density of the second dielectric layer 123, which can be more beneficial to the insulation of the second part II and other device structures, and the density of the second dielectric layer 123 is smaller, which can be covered on the opposite side surface of the first semiconductor layer 101 having the opening 112, thereby protecting the first channel region formed by the first part I, and avoiding the leakage between the side surface of the first channel region away from the first gate 102 and other device structures.

[0046] In some embodiments, the material of the first dielectric layer 113 includes silicon nitride, and the material of the second dielectric layer 123 includes silicon oxide. It can be understood that the density of silicon oxide is smaller than that of silicon nitride, and accordingly the stress of the second dielectric layer is smaller, which can avoid excessive stress on the first channel region when covering the side surface of the first channel region away from the first gate, and reduce the stress of the second dielectric layer on the first channel region; the first dielectric layer is silicon nitride, which can isolate the influence of oxygen in the second dielectric layer on the source or drain formed by the second part.

[0047] For the first gate 102, in some embodiments, referring to Figure 8 , the first gate 102 includes a first gate dielectric layer 122 and a first gate conductive layer 132, the first gate dielectric layer 122 covers the surface of the opening 112, and the first gate conductive layer 132 covers the surface of the first gate dielectric layer 122 and fills the opening 112, and the dielectric constant of the first gate dielectric layer 122 is greater than the dielectric constant of the second dielectric layer 123. The dielectric constant of the first gate dielectric layer 122 is greater than that of the second dielectric layer 123, which can reduce the direct tunneling current in the first gate 102, thereby reducing the leakage and improving the reliability of the first gate dielectric layer 122.

[0048] For the first gate conductive layer 132, in some embodiments, the material of the first gate conductive layer 132 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, lanthanum, titanium, or tungsten.

[0049] For the first gate dielectric layer 122, in some embodiments, the material of the first gate dielectric layer 122 includes at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide, or titanium oxide.

[0050] That is, the first gate dielectric layer 122 is made of a high dielectric constant material, so that the equivalent oxide thickness (EOT) of the first gate dielectric layer 122 can be kept unchanged while reducing the physical thickness of the first gate dielectric layer 122, so as to reduce the direct tunneling effect and reduce the tunneling current.

[0051] In some embodiments, referring to Figure 9 , the semiconductor structure can further include an isolation layer 105 located on the side surface of the first gate 102 away from the first semiconductor layer 101. The isolation layer 105 can separate the first gate 102 from other semiconductor structures to avoid leakage between the first gate 102 and other device structures.

[0052] In some embodiments, referring to Figure 10 , Figure 10 A schematic diagram of a structure of a first semiconductor layer arranged along a first direction is provided for an embodiment of the present disclosure. A plurality of first semiconductor layers 101 are arranged along a first direction X, and each first semiconductor layer 101 includes at least two first parts I along the first direction X, and each first part I has a first gate 102 in the opening 112 thereof.

[0053] By arranging the first semiconductor layers 101 along the first direction X, and each first semiconductor layer 101 including at least two first parts I, and each first part I having a first gate 102 in the opening 112 thereof, one first semiconductor layer 101 can form a plurality of first transistors along the first direction X, and the first transistors formed by the same first semiconductor layer 101 along the first direction X can share the same second part II to form a first source contact region or a first drain contact region, thereby facilitating reduction of the total area occupied by the plurality of first transistors arranged along the first direction X.

[0054] In some embodiments, referring to Figure 11 , Figure 11In another structure provided by an embodiment of the present disclosure, the dielectric layer 103 on the second part II surface of the adjacent first semiconductor layer 101 can be in the same layer and the edges can extend to connect to each other. Then, the first transistors formed by different first semiconductor layers 101 can share the same dielectric layer 103 to isolate from other device structures, thereby improving the stability of the semiconductor structure. In addition, the dielectric layer 103 on the second part II surface of the different first semiconductor layers 101 can be formed in the same process step, thereby reducing the manufacturing process of the semiconductor structure and reducing the difficulty of the manufacturing process of the semiconductor structure.

[0055] It can be understood that the drawings provided by the embodiments are schematic diagrams of part of the semiconductor structure, Figure 10 and Figure 11 both of which show the structure of two first semiconductor layers 101 arranged in the first direction X, and do not constitute a limitation on the number of first semiconductor layers 101 arranged in the first direction X.

[0056] In some embodiments, referring to Figure 12 , Figure 12 a top view of a semiconductor structure provided by an embodiment of the present disclosure, a plurality of first semiconductor layers 101 can also be arranged at intervals in the second direction Y, and in the second direction Y, a plurality of first gates 102 are connected to each other. To form a plurality of first transistors arranged in the first direction X and the second direction Y, and in the second direction Y, the first gates 102 of the plurality of first transistors are connected to each other, which can reduce the gate control end of the first transistor and improve the control ability of the word line in the array-arranged first transistor.

[0057] In some embodiments, referring to Figure 13 , a plurality of first semiconductor layers 101 are arranged in the first direction X and the second direction Y, and the adjacent first semiconductor layers 101 are spaced apart from each other, and each first semiconductor layer 101 has a first gate 102 in the opening 112; wherein the first gate 102 of at least one first transistor is electrically connected to the first source contact region or the first drain contact region of another first transistor. For example Figure 13 as shown in , the first gate 102 of one first transistor can be electrically connected to the first source contact region or the first drain contact region of another first transistor through a transmission line 106.

[0058] That is, a plurality of first transistors are arranged in the first direction X and the second direction Y, and the plurality of first transistors are spaced apart from each other, wherein the first source contact region or the first drain contact region of one first transistor is connected to the first gate of another first transistor, and the corresponding two first transistors can form a 2T0C structure, thereby reducing the capacitor manufacturing process in the semiconductor structure.

[0059] In some embodiments, referring to Figure 14 , the semiconductor structure further comprises: a second gate 202, one end of which is electrically connected with the first source contact region or the first drain contact region, and the other end of which extends away from the first semiconductor layer 101; and a second semiconductor layer 201, which is located on the side surface of the second gate 202 away from the first semiconductor layer 101, and the second semiconductor layer 201 comprises a third part III and a fourth part IV located on the opposite sides of the third part III, and the third part III covers the surface of the second gate 202; wherein the third part III is used to form a second channel region of a second transistor, and the fourth part IV is used to form a second source contact region or a second drain contact region of the second transistor. By electrically connecting the first source contact region or the first drain contact region of the first transistor with the second gate, the first transistor and the second transistor can jointly form a 2T0C structure, thereby reducing the capacitance manufacturing process in the semiconductor structure.

[0060] It should be noted that, in some embodiments, one end of the second gate can be in contact with the first source contact region or the first drain contact region; in some embodiments, the second gate can be electrically connected with the first source contact region or the first drain contact region by using a transmission line formed by a conductive material, one end of the transmission line being in electrical contact with the first gate, and the other end of the transmission line being in electrical contact with the first source contact region or the first drain contact region, so as to electrically connect the second gate with the first source contact region or the first drain.

[0061] As for the second semiconductor layer 201, in some embodiments, the material of the second semiconductor layer 201 comprises Indium Gallium Zinc Oxide (IGZO). When the material of the second semiconductor layer 201 is IGZO, the carrier mobility of IGZO is 20-50 times that of polysilicon, which can be beneficial to improve the carrier mobility in the semiconductor channel, thereby being beneficial to reduce the leakage current when the semiconductor structure is working, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure.

[0062] In some embodiments, the material of the second semiconductor layer 201 is the same as that of the first semiconductor layer 101. When the materials of the second semiconductor layer and the first semiconductor layer are the same, the semiconductor channels of the first transistor and the second transistor are the same, and the structures of the two transistors in the 2T0C structure formed thereby are similar.

[0063] In other embodiments, the material of the second semiconductor layer can be different from that of the first semiconductor layer.

[0064] As for the second gate 202, in some embodiments, referring to Figure 15For example, the second gate 202 is in electrical connection with the first source contact or the first drain contact, the second gate 202 includes a second gate dielectric layer 222 and a second gate conductive layer 232, one end of the second gate conductive layer 232 is in electrical connection with the first source contact or the first drain contact, and the other end extends away from the first source contact or the first drain contact; the second gate dielectric layer 222 is located on a side surface of the second gate conductive layer 232 away from the first source contact or the first drain contact, and the second semiconductor layer 201 is located on a side surface of the second gate dielectric layer 222 away from the second gate conductive layer 232; in the extending direction of the second gate conductive layer 232, the third part III of the second semiconductor layer 201 is opposite to the surface of the second gate conductive layer 232 in contact with the second gate dielectric layer 222.

[0065] For the second gate conductive layer 232, in some embodiments, the material of the second gate conductive layer 232 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, lanthanum, titanium or tungsten.

[0066] For the second gate dielectric layer 222, in some embodiments, the material of the second gate dielectric layer 222 includes at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide or titanium oxide.

[0067] That is, the second gate dielectric layer 222 is made of a high dielectric constant material, so that the equivalent oxide thickness (EOT) of the second gate dielectric layer 222 can be kept unchanged while reducing the physical thickness of the second gate dielectric layer 222, so as to reduce the direct tunneling effect and reduce the tunneling current.

[0068] In some embodiments, the material of the second gate conductive layer 232 is the same as the material of the first gate conductive layer 132, and the material of the second gate dielectric layer 222 is the same as the material of the first gate dielectric layer 122, so as to form the first transistor and the second transistor with similar material properties, and the two transistors in the corresponding 2T0C have similar material properties, thereby improving the stability of the semiconductor structure.

[0069] In other embodiments, the material of the second gate conductive layer can be different from the material of the first gate conductive layer, and the material of the second gate dielectric layer can be different from the material of the first gate dielectric layer.

[0070] In some embodiments, the first transistor and the second transistor jointly form a storage unit, and the storage units are arranged in an array along the first direction and the second direction. By arranging the storage units formed by the first transistor and the second transistor in an array along the first direction and the second direction, the transistor structure of the arrayed 2T0C can be formed, so as to improve the integration density of the semiconductor structure.

[0071] In some embodiments, the second gate dielectric layer in different second transistors are in the same layer and the edges thereof extend to contact each other. That is, the second gate 202 in the second transistors can share the same second gate dielectric layer 222, and thus the second gate dielectric layer 222 of different second transistors can be formed in the same process step during the manufacturing process of the semiconductor structure. Figure 16 It should be noted that the semiconductor structure provided by the embodiments of the present disclosure

[0072] The semiconductor structure provided by the embodiments of the present disclosure is only a schematic diagram of part of the semiconductor structure, Figure 16 The semiconductor structure provided by the embodiments of the present disclosure is only a schematic diagram of part of the semiconductor structure, Figure 16 The semiconductor structure provided by the embodiments of the present disclosure is only a schematic diagram of part of the semiconductor structure,

[0073] The first semiconductor layer of the semiconductor structure provided by the embodiments of the present disclosure includes a first part and a second part, the first part is bent away from the second part to form an opening, and the first gate is in the opening. The first gate and the first semiconductor layer are used to form the first transistor, the first part is used to form the first channel region of the first transistor, the bent opening can increase the contact area of the first channel region and the first gate, improve the gate control ability of the first transistor, and using the first semiconductor layer as the semiconductor channel of the first transistor can be beneficial to improve the moving speed of the carriers.

[0074] In addition, the second part is used to form the first source contact region or the first drain contact region, that is, the surface of the second part is used to form a contact structure to connect the bit line or the capacitor. The dielectric layer is located on at least one side surface of the second part, for example, the dielectric layer can be located on the side surface opposite to the contact structure of the second part, or on the two side surfaces opposite to each other of the second part, so as to arrange the contact structure in the dielectric layer, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part.

[0075] According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which can be used to form the above semiconductor structure to improve the performance of the formed semiconductor structure. It should be noted that the same or corresponding parts as the above embodiments can refer to the corresponding description of the foregoing embodiments, which will not be described in detail below.

[0076] Figures 17 to 20 The manufacturing method of the semiconductor structure provided by another embodiment of the present disclosure is schematically shown in the corresponding structure diagram of each step, and the manufacturing method of the semiconductor structure provided by the present embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the manufacturing method provided by the present embodiment is taken as an example of forming a single first transistor and the dielectric layer is located on the surface of the second part of the first semiconductor layer facing the base, and the manufacturing method of the semiconductor structure is as follows:

[0077] Referring to Figure 17 , a substrate 300 is provided, and a dielectric layer 301 is formed on the substrate 300, the dielectric layer 301 includes a first dielectric layer 311 and a second dielectric layer 321, the second dielectric layer 321 covers a surface of the substrate 300, and the first dielectric layer 311 covers a surface of the second dielectric layer 321; a recess 302 is formed in the dielectric layer 301; referring to Figure 18 , a first semiconductor layer 303 is formed, the first semiconductor layer 303 covers a top and a sidewall of the recess 302, and further covers a surface of the dielectric layer 301, the first semiconductor layer 303 includes a first portion I and a second portion II located on opposite sides of the first portion I, the first portion I is bent away from the second portion II to form a bent opening 313, and the dielectric layer 301 is located on at least one side surface of the second portion II; referring to Figure 19 , a first gate 304 is formed, the first gate 304 is located in the opening 313, and the first gate 304 includes a first gate dielectric layer 324 and a first gate conductive layer 314, the first gate dielectric layer 324 covers a surface of the opening 313, and the first gate conductive layer 314 fills the opening 313, wherein the first portion I is used to form a first channel region of a first transistor, and the second portion II on opposite sides of the first channel region is used to form a first source contact region or a first drain contact region.

[0078] For the substrate 300, the material forming the substrate 300 includes an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material can be germanium, silicon, selenium, boron, tellurium, or antimony; and the compound semiconductor material can be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon, etc.

[0079] For the first dielectric layer 311, the material forming the first dielectric layer 311 includes silicon nitride.

[0080] For the second dielectric layer 321, the material forming the second dielectric layer 321 includes silicon oxide.

[0081] For the first semiconductor layer 303, the material forming the first semiconductor layer 303 includes indium gallium zinc oxide (IGZO).

[0082] For the first gate conductive layer 314, the material forming the first gate conductive layer 314 includes at least one of polysilicon, titanium nitride, titanium aluminum, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, lanthanum, titanium, or tungsten.

[0083] For the first gate dielectric layer 324, the material forming the first gate dielectric layer 324 includes at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide, or titanium oxide.

[0084] It can be understood that, based on the manufacturing method of the semiconductor structure forming the single first transistor provided in the above embodiments, a person skilled in the art can derive a manufacturing method of the semiconductor structure forming the array-arranged first transistors.

[0085] For example, in some embodiments, the forming the first semiconductor layer on the substrate comprises: forming a plurality of first semiconductor layers arranged in a first direction and a second direction, each of the first semiconductor layers comprises at least two first parts in the first direction; and the forming the first gate electrode comprises: forming a first gate electrode in each of the first parts, and in the second direction, the plurality of first gate electrodes are connected to each other. Thus, the array-arranged first transistors are formed, wherein each of the first semiconductor layers comprises at least two first parts in the first direction, and two first transistors corresponding to one first semiconductor layer are formed, and the two first transistors share the same second part to form the first source contact region or the first drain contact region, so as to reduce the total area occupied by the first transistors and improve the integration density of the semiconductor structure. In addition, in the second direction, the plurality of first gate electrodes are connected to each other, so that the plurality of first transistors in the second direction share the same control end of the first gate electrode, thereby facilitating the reduction of the number of gate control ends of the array-arranged first transistors.

[0086] In some embodiments, with reference to Figure 20 , the forming the first gate electrode 304 further comprises: forming a second gate electrode 305, one end of which is electrically connected to the first source contact region or the first drain contact region, and the other end extends away from the surface of the substrate 300; the second gate electrode 305 comprises a second gate dielectric layer 315 and a second gate conductive layer 325, one end of the second gate conductive layer 325 is electrically connected to the first source contact region or the first drain contact region, and the other end extends away from the first source contact region or the first drain contact region; the second gate dielectric layer 315 is located on the side surface of the second gate conductive layer 325 away from the first source contact region or the first drain contact region; and the forming the second semiconductor layer 306 comprises: forming a third part III and a fourth part IV located on the opposite sides of the third part III, the third part III covers the surface of the second gate electrode 306, and in the extending direction of the second gate conductive layer 325, the third part III of the second semiconductor layer 306 is opposite to the surface of the second gate conductive layer 325 and the second gate dielectric layer 315; wherein the third part III is used to form a second channel region of a second transistor, and the fourth part IV is used to form a second source contact region or a second drain contact region of the second transistor.

[0087] By electrically connecting the first source contact region or the first drain contact region of the first transistor with the second gate, the first transistor and the second transistor can jointly form a 2T0C structure, thereby reducing the capacitance manufacturing process in the semiconductor structure.

[0088] For the second gate conductive layer 325, the material of the second gate conductive layer 325 includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, lanthanum, titanium or tungsten.

[0089] For the second gate dielectric layer 315, the material of the second gate dielectric layer 315 includes at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide or titanium oxide.

[0090] For the second semiconductor layer 306, the material of the second semiconductor layer 306 includes indium gallium zinc oxide (IGZO).

[0091] The semiconductor structure manufacturing method provided by the embodiments of the present disclosure forms the first semiconductor layer including a first part and a second part, the first part is bent away from the second part to form an opening, and the first gate is in the opening, the first gate and the first semiconductor layer are used to form the first transistor, the first part is used to form the first channel region of the first transistor, the bent opening can increase the contact area of the first channel region and the first gate, improve the gate control capability of the first transistor, and using the first semiconductor layer as the semiconductor channel of the first transistor can be beneficial to improve the moving speed of the carriers.

[0092] In addition, the second part is used to form the first source contact region or the first drain contact region, that is, the surface of the second part is used to form a contact structure to connect the bit line or the capacitor, and the dielectric layer is located on at least one side surface of the second part, for example, the dielectric layer can be located on the side surface opposite to the contact structure of the second part, or on the two side surfaces opposite to the second part, so as to arrange the contact structure in the dielectric layer, thereby avoiding the influence of other structures in the semiconductor structure on the source or the drain formed by the second part.

[0093] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising: a first semiconductor layer comprising a first portion and a second portion on opposite sides of the first portion, the first portion being bent away from the second portion to form an opening; a first gate in the opening; a dielectric layer on at least one side surface of the second portion; wherein the first portion is configured to form a first channel region of a first transistor, and the second portions on opposite sides of the first channel region are configured to form a first source contact region or a first drain contact region; wherein a plurality of the first semiconductor layers are arranged along a first direction, and each of the first semiconductor layers comprises at least two first portions along the first direction, and each of the first portions has a first gate in the opening. 2.The semiconductor structure of claim 1, wherein: the dielectric layer comprises a first dielectric layer on a surface of the second portion and a second dielectric layer on a surface of the first dielectric layer away from the second portion, and a density of the first dielectric layer is greater than a density of the second dielectric layer. 3.The semiconductor structure of claim 2, wherein: a material of the first dielectric layer comprises silicon nitride, and a material of the second dielectric layer comprises silicon oxide. 4.The semiconductor structure of claim 2, wherein: the first gate comprises a first gate dielectric layer covering a surface of the opening and a first gate conductive layer covering a surface of the first gate dielectric layer and filling the opening, and a dielectric constant of the first gate dielectric layer is greater than a dielectric constant of the second dielectric layer. 5.The semiconductor structure of claim 4, wherein: a material of the first gate dielectric layer comprises at least one of hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, zirconium oxide, or titanium oxide. 6.The semiconductor structure of claim 1, wherein: a material of the first semiconductor layer comprises indium gallium zinc oxide. 7.The semiconductor structure of claim 1, wherein: a plurality of the first semiconductor layers are arranged along a second direction with a spacing, and a plurality of the first gates are connected to each other along the second direction. 8.The semiconductor structure of claim 1, wherein: a plurality of the first semiconductor layers are arranged along the first direction and the second direction with a spacing between adjacent first semiconductor layers, and each of the first semiconductor layers has a first gate in the opening; wherein the first gate of at least one of the first transistors is electrically connected to a first source contact region or a first drain contact region of another of the first transistors. 9.The semiconductor structure of claim 1, further comprising: a second gate electrically connected to the first source contact region or the first drain contact region at one end and extending away from the first semiconductor layer at another end. ​ ​ A second semiconductor layer is located on a side surface of the second gate away from the first semiconductor layer, and the second semiconductor layer comprises a third part and fourth parts located on opposite sides of the third part, and the third part covers a surface of the second gate; wherein the third part is used to form a second channel region of a second transistor, and the fourth parts are used to form a second source contact region or a second drain contact region of the second transistor.

10. The semiconductor structure of claim 9, wherein, a material of the second semiconductor layer is the same as a material of the first semiconductor layer.

11. The semiconductor structure of claim 9, wherein, the first transistor and the second transistor jointly form a memory cell, and the memory cell is arranged in an array along a first direction and a second direction.

12. The semiconductor structure of claim 9, wherein, the second gate comprises a second gate dielectric layer and a second gate conductive layer, one end of the second gate conductive layer is electrically connected with the first source contact region or the first drain contact region, the other end of the second gate conductive layer extends away from the first source contact region or the first drain contact region, and the second gate dielectric layer covers a side surface of the second gate conductive layer away from the first source contact region or the first drain contact region, wherein the second gate dielectric layers in different second transistors are in the same layer and their edges extend to each other.

13. The semiconductor structure of claim 12, wherein, the first gate comprises a first gate dielectric layer and a first gate conductive layer, the first gate dielectric layer covers a surface of the opening, and the first gate conductive layer covers a surface of the first gate dielectric layer and fills the opening; wherein a material of the second gate dielectric layer is the same as a material of the first gate dielectric layer.

14. A manufacturing method of a semiconductor structure, comprising: providing a substrate; forming a first semiconductor layer on the substrate, the first semiconductor layer comprises a first part and second parts located on opposite sides of the first part, and the first part is bent away from the second parts to form an opening; forming a first gate in the opening; forming a dielectric layer on at least one side surface of the second parts; wherein the first part is used to form a first channel region of a first transistor, and the second parts on opposite sides of the first channel region are used to form a first source contact region or a first drain contact region; wherein forming the first semiconductor layer on the substrate comprises: forming a plurality of first semiconductor layers arranged in an array along a first direction and a second direction, and each of the first semiconductor layers comprises at least two first parts along the first direction; forming the first gate comprises: forming a first gate in the opening of each of the first parts, and along the second direction, a plurality of the first gates are connected to each other.

15. The manufacturing method of the semiconductor structure of claim 14, wherein after forming the first gate, the method further comprises: ​ ​ forming a second gate, one end of which is electrically connected with the first source contact region or the first drain contact region, and the other end of which extends away from the surface of the substrate; forming a second semiconductor layer, which is located on the side surface of the second gate away from the first semiconductor layer, and which comprises a third part and fourth parts located on opposite sides of the third part, the third part covering the surface of the second gate; wherein the third part is used to form a second channel region of a second transistor, and the fourth parts are used to form second source contact regions or second drain contact regions of the second transistor.

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