Clock stop monitoring circuit, monitoring method, chip system and storage medium

Abstract

The present invention relates to a clock stop monitoring circuit, a monitoring method, a chip system and a storage medium, comprising a crystal oscillator monitoring circuit, a clock switching circuit, a crystal oscillator recovery circuit and an exception handling circuit. The crystal oscillator monitoring circuit repeatedly monitors the crystal oscillator clock signal for stop, and outputs a crystal oscillator stop flag; the crystal oscillator recovery circuit outputs a crystal oscillator restart signal to an external crystal oscillator, and outputs a crystal oscillator recovery flag to the clock switching circuit after the external crystal oscillator is successfully restarted; when the clock switching circuit receives the crystal oscillator stop flag, it switches the operating clock to a high-frequency RC clock, and when the clock switching circuit receives the crystal oscillator recovery flag, it switches the operating clock to the external crystal oscillator. The present invention attempts to recover the crystal oscillator by restarting, which can effectively solve the stop problem caused by factors such as poor contact, and once the clock switching circuit detects that the crystal oscillator has recovered, it will automatically switch to a relatively accurate crystal oscillator clock, effectively enhancing the reliability and accuracy of the chip system.

Description

Technical Field

[0001] The present invention relates to the technical field of clock detection, and in particular to a clock stop monitoring circuit, a monitoring method, a chip system and a storage medium. Background Art

[0002] With the development of chip technology, the requirements for chip reliability and security are becoming increasingly higher. Among them, the chip's operating clock plays an important role in the normal operation of the entire chip, and the stability of the clock operation affects the stability of the entire system.

[0003] Chip clocks are broadly categorized into three types. The first is the ring oscillator clock generated by the chip's internal RC oscillator. This type of clock has poor temperature characteristics, resulting in inaccurate clock frequency, short stability time, and is not prone to stalling. The second type is the internal phase-locked loop clock, which has a higher frequency and a longer stabilization time, making it unsuitable as a power-up clock. The third type is the external crystal oscillator clock, which requires a start-up circuit to generate the clock. While accurate in frequency, it is significantly affected by the external environment and prone to stalling. External crystal oscillators often experience stalling due to environmental influences, causing internal clock disruptions.

[0004] To address clock irregularities caused by oscillation stall, existing solutions typically detect the crystal oscillator's clock edges to determine whether the clock frequency is within the required range. This single comparison determines whether the crystal oscillator has failed. However, due to the long startup time of crystal oscillators, especially low-frequency crystals, the clock is unstable during the initial startup period. Therefore, judging failure based on a single result increases the probability of misjudgment. Furthermore, if the crystal oscillator fails to start due to problems such as poor solder connections on the circuit board, there is no recovery measure. Consequently, the chip's operating clock directly switches to the internal high-frequency RC clock, and the crystal oscillator clock does not recover, which can easily lead to inaccurate chip operating clocks. Summary of the Invention

[0005] The embodiments of the present invention provide a clock stop monitoring circuit, a monitoring method, a chip system and a storage medium, so as to at least solve the problem in the related art that the crystal oscillator clock cannot automatically restart and resume operation after stopping oscillation.

[0006] In a first aspect, an embodiment of the present invention provides a clock oscillation stop monitoring circuit, which is applied in a chip system. The clock oscillation stop monitoring circuit includes a crystal oscillator monitoring circuit, a clock switching circuit, a crystal oscillator recovery circuit, and an exception handling circuit; wherein,

[0007] The input end of the crystal oscillator monitoring circuit obtains a crystal oscillator clock signal from an external crystal oscillator, and the output end is connected to the input ends of the clock switching circuit, the crystal oscillator recovery circuit, and the abnormality handling circuit respectively; the crystal oscillator monitoring circuit repeatedly performs oscillation stop monitoring on the crystal oscillator clock signal according to a preset clock cycle, and when the crystal oscillator monitoring circuit detects that the crystal oscillator clock signal is abnormal, it outputs a crystal oscillator stop flag to the clock switching circuit, the crystal oscillator recovery circuit, and the abnormality handling circuit;

[0008] The output end of the crystal oscillator recovery circuit is connected to the clock switching circuit and the external crystal oscillator respectively; when the crystal oscillator recovery circuit receives the crystal oscillator stop flag, it outputs a crystal oscillator restart signal to the external crystal oscillator, and outputs a crystal oscillator recovery flag to the clock switching circuit after the external crystal oscillator is successfully restarted;

[0009] The output end of the clock switching circuit is connected to the external crystal oscillator and the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator stop flag, the operating clock is switched to the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator recovery flag, the operating clock is switched to the external crystal oscillator;

[0010] The abnormality processing circuit is used to obtain a preset protection measure to protect the chip system after receiving the crystal oscillator stop flag.

[0011] In some embodiments, the clock stop monitoring circuit also includes a crystal oscillator starting circuit; wherein, the input end of the crystal oscillator starting circuit is connected to the crystal oscillator recovery circuit, and the output end is connected to the crystal oscillator monitoring circuit, and the crystal oscillator starting circuit is used to convert the analog signal of the external crystal oscillator into a digital signal of the crystal oscillator clock signal and send it to the crystal oscillator monitoring circuit; receive the crystal oscillator restart signal output by the crystal oscillator recovery circuit and restore the external crystal oscillator.

[0012] In some embodiments, the crystal oscillator monitoring circuit and the crystal oscillator recovery circuit use a normally-on low-frequency RC clock as their operating clock, and the low-frequency RC clock outputs an operating clock signal.

[0013] In some embodiments, the crystal oscillator monitoring circuit includes a frequency division module, a first counting module, a second counting module, a first comparison module, and a second comparison module; wherein;

[0014] The frequency division module is used to obtain the crystal oscillator clock signal and divide it according to a preset frequency division value, generate a divided clock signal and send it to the first counting module;

[0015] The first counting module is used to obtain a frequency-divided clock signal and a working clock signal, operate according to the working clock signal, and count the frequency-divided clock signal;

[0016] The second counting module is used to obtain the working clock signal and count the working clock signal to obtain a second count value;

[0017] The first comparison module is used to obtain a first preset threshold value, and compare the first count value obtained by the first counting module within the preset clock cycle with the first preset threshold value, and determine whether to output a crystal oscillator stop signal according to the comparison result;

[0018] The second comparison module is configured to obtain the second count value, and output a reset signal to the first counting module when determining that the second count value is equal to the preset clock period.

[0019] In some embodiments, the crystal oscillator recovery circuit includes a third counting module, a third comparing module, a signal triggering module and a first AND gate; wherein,

[0020] The third counting module is used to obtain a working clock signal and count the working clock signal to obtain a third count value;

[0021] The third comparison module obtains a preset time value and a third count value and compares them, and resets the third count module when the third count value is equal to the preset time value;

[0022] The signal trigger module obtains the third count value and outputs a corresponding level signal according to the size of the third count value;

[0023] The first AND gate obtains the level signal and the crystal oscillator stop flag, and outputs a crystal oscillator recovery signal when the crystal oscillator stop flag is received and the level signal is a preset level.

[0024] In a second aspect, an embodiment of the present invention provides a clock oscillation stop monitoring method, which is applied to the clock oscillation stop monitoring circuit described in any of the above embodiments. The method includes:

[0025] Acquire a crystal oscillator clock signal, and monitor the crystal oscillator clock signal for oscillation stop according to a preset clock cycle, and output a crystal oscillator stop flag when the crystal oscillator clock signal is detected to be abnormal;

[0026] After receiving the crystal oscillator stop flag, the operating clock of the chip system is switched to a high-frequency RC clock, and a preset protection measure is obtained to protect the chip system, and at the same time, a crystal oscillator restart signal is output to stimulate the external crystal oscillator to restart, until the external crystal oscillator resumes operation;

[0027] When it is determined that the external crystal oscillator has resumed operation, a crystal oscillator resumption flag is output, and the operating clock of the chip system is switched to the external crystal oscillator clock according to the crystal oscillator stop flag.

[0028] In some embodiments, the monitoring of the crystal oscillator clock signal for oscillation stop according to a preset clock cycle and outputting a crystal oscillator stop flag when an abnormality is detected in the crystal oscillator clock signal include:

[0029] Obtaining a first preset value, and dividing the frequency of the crystal oscillator clock signal according to the first preset value to obtain a divided clock signal, and counting the divided clock signal, recording the total number of divided clock signal cycles within one preset clock cycle as a first count value;

[0030] Obtaining a first preset threshold, and comparing the first count value with the first preset threshold; if the first count value is greater than or equal to the first preset threshold, outputting a crystal oscillator stop flag;

[0031] A working clock signal is acquired, and the working clock signal is counted to obtain a second count value; when the second count value is equal to the preset clock period, the first count value is cleared and counted again.

[0032] In some embodiments, the outputting of a crystal oscillator restart signal for stimulating the external crystal oscillator to restart includes:

[0033] Obtaining a working clock signal, counting the working clock signal to obtain a third count value, and outputting the third count value in real time;

[0034] Obtaining a second preset threshold, comparing the third count value with the second preset threshold, and outputting a corresponding level signal according to the comparison result;

[0035] When the crystal oscillator stop flag is received and the level signal is at a preset level, a crystal oscillator restart signal is output;

[0036] A preset time value is obtained, and when the third count value is equal to the preset time value, the third count value is cleared and counted again until the external crystal oscillator resumes operation.

[0037] In a third aspect, an embodiment of the present invention provides a chip system, including a memory and a processor, characterized in that it also includes the clock stop monitoring circuit described in any of the above embodiments.

[0038] In a fourth aspect, an embodiment of the present invention provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to execute the clock stop monitoring method described in any of the above embodiments when running.

[0039] Compared with the related art, the clock stop monitoring circuit, monitoring method, chip system and storage medium provided by the embodiment of the present invention can not only monitor whether the crystal oscillator clock is working normally through the crystal oscillator monitoring circuit, but also complete clock switching and exception handling measures such as the clock switching circuit and the exception handling circuit to avoid abnormal chip operation when the crystal oscillator clock is abnormal. At the same time, the crystal oscillator recovery circuit is used to restart the stopped crystal oscillator multiple times. By trying to restore the crystal oscillator by restarting, the stop problem caused by factors such as poor contact can be effectively solved. Once the clock switching circuit detects that the crystal oscillator has recovered, it will automatically switch to a relatively accurate crystal oscillator clock. Therefore, the present invention not only realizes the automatic restoration of the normal working state after the crystal oscillator stops, but also effectively enhances the reliability and accuracy of the chip system. In addition, the present invention detects the number of crystal oscillator clocks within a period of time (preset clock cycle) by window detection and compares it with the expected number of clocks, thereby judging whether the crystal oscillator has failed, which can greatly reduce the probability of misjudgment of stop. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0041] Figure 1 1 is a schematic structural diagram of a clock stop monitoring circuit according to an embodiment of the present invention;

[0042] Figure 2 is a circuit schematic diagram of a crystal oscillator monitoring circuit according to an embodiment of the present invention;

[0043] Figure 3 is a circuit schematic diagram of a crystal oscillator recovery circuit according to an embodiment of the present invention;

[0044] Figure 4 FIG. 4 is a timing diagram of crystal oscillator recovery according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described and illustrated in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Based on the embodiments provided by the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for those of ordinary skill in the art related to the contents disclosed by the present invention, some changes such as design, manufacturing or production based on the technical contents disclosed by the present invention are only conventional technical means and should not be understood as the contents disclosed by the present invention being insufficient.

[0046] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments, unless there is a conflict.

[0047] Unless otherwise defined, technical or scientific terms used in the present invention shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the invention pertains. The terms "a," "an," "a kind," "the," and similar expressions used in the present invention do not limit the number and may refer to the singular or plural. The terms "comprise," "include," "have," and any variations thereof used in the present invention are intended to cover non-exclusive inclusions; for example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or units but may also include steps or units not listed, or may include other steps or units inherent to the process, method, product, or device. The terms "connect," "connected," "coupled," and similar expressions used in the present invention are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. The term "plurality" used in the present invention means greater than or equal to two. "And / or" describes an association relationship between associated objects, indicating that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist simultaneously, or B exists alone. The terms "first", "second", "third", etc. involved in the present invention are merely used to distinguish similar objects and do not represent a specific ordering of the objects.

[0048] External crystal oscillators in chip systems often experience environmental factors that cause them to stop oscillating, disrupting the chip's internal clock. This invention addresses this issue by using a detection circuit to promptly detect whether the crystal oscillator is operating normally. Once a stoppage is detected, the system takes appropriate action and attempts to stimulate the crystal oscillator for recovery. If the crystal oscillator recovers, the chip's internal clock will continue to be used.

[0049] In response to the above solution, an embodiment of the present invention provides a clock oscillation stop monitoring circuit, which is applicable to both high-frequency crystal oscillators and low-frequency crystal oscillators. The clock oscillation stop monitoring circuit includes a crystal oscillator monitoring circuit, a clock switching circuit, a crystal oscillator recovery circuit, and an exception handling circuit.

[0050] Specific reference Figure 1 The input end of the crystal oscillator monitoring circuit obtains the crystal oscillator clock signal, and the output end is connected to the input ends of the clock switching circuit, the crystal oscillator recovery circuit and the abnormality handling circuit respectively; the crystal oscillator monitoring circuit repeatedly performs oscillation stop monitoring on the crystal oscillator clock signal according to a preset clock cycle, and when the crystal oscillator monitoring circuit detects that the crystal oscillator clock signal is abnormal, it outputs a crystal oscillator stop flag to the clock switching circuit, the crystal oscillator recovery circuit and the abnormality handling circuit;

[0051] The output end of the crystal oscillator recovery circuit is connected to the clock switching circuit and the external crystal oscillator respectively; when the crystal oscillator recovery circuit receives the crystal oscillator stop flag, it outputs a crystal oscillator restart signal to the external crystal oscillator, and outputs a crystal oscillator recovery flag to the clock switching circuit after the external crystal oscillator is successfully restarted;

[0052] The output end of the clock switching circuit is connected to the external crystal oscillator and the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator stop flag, the operating clock is switched to the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator recovery flag, the operating clock is switched to the external crystal oscillator;

[0053] The abnormality processing circuit is used to obtain a preset protection measure to protect the chip system after receiving the crystal oscillator stop flag.

[0054] The clock stop monitoring circuit provided in the embodiment of the present invention also includes a crystal oscillator starting circuit; wherein, the crystal oscillator starting circuit is connected between the crystal oscillator clock and the clock stop monitoring circuit, and the input end of the crystal oscillator starting circuit is connected to the crystal oscillator recovery circuit, and the output end is connected to the crystal oscillator monitoring circuit. The external crystal oscillator of the chip system generally requires the cooperation of the crystal oscillator starting circuit to output the crystal oscillator clock. The crystal oscillator starting circuit of this embodiment is an analog circuit, which can be integrated inside the IO PAD (chip pin processing module) or separately set outside the IO PAD. The crystal oscillator starting circuit is used to convert the analog signal of the external crystal oscillator into a crystal oscillator clock signal of a digital signal and send it to the crystal oscillator monitoring circuit; receive the crystal oscillator restart signal output by the crystal oscillator recovery circuit and restore the external crystal oscillator so that the external crystal oscillator can start working again.

[0055] In the embodiment of the present invention, the external crystal oscillator cooperates with the crystal oscillator starting circuit to output the crystal oscillator clock (i.e., the crystal oscillator clock signal). The crystal oscillator monitoring circuit monitors in real time whether the received crystal oscillator clock is normal. Once it detects that it has stopped oscillating, it outputs a crystal oscillator stop flag. When the abnormality handling circuit of the SOC system (chip system) detects the crystal oscillator stop flag, it is regarded as an abnormality of the chip's external crystal oscillator, and the advanced timer brake will be triggered to prevent damage to the device; after the clock switching circuit receives the crystal oscillator stop flag, it will switch the chip system clock to a high-frequency RC clock; after the crystal oscillator recovery circuit receives the crystal oscillator stop flag, it will output a restart signal every second to try to restore the external crystal oscillator until the external crystal oscillator works again. After the recovery is successful, the previous clock abnormality signal will automatically become invalid, that is, the output of the crystal oscillator stop flag will stop. The crystal oscillator recovery circuit will notify the clock switching circuit to switch the running clock back to the external crystal oscillator clock and stop stimulating the recovery crystal oscillator.

[0056] In a preferred embodiment of the present invention, the crystal oscillator monitoring circuit and the crystal oscillator recovery circuit use a normally-on low-frequency RC clock as their operating clock. Furthermore, the crystal oscillator monitoring circuit includes a frequency division module, a first counting module, a second counting module, a first comparison module, and a second comparison module.

[0057] Specific reference Figure 2, the frequency division module is used to obtain the crystal oscillator clock signal and divide it according to the preset frequency division value, generate a frequency-divided clock signal and send it to the first counting module; the first counting module is used to obtain the frequency-divided clock signal and the working clock signal, work according to the working clock signal, and count the frequency-divided clock signal; the second counting module is used to obtain the working clock signal and count the working clock signal to obtain a second count value; the first comparison module is used to obtain a first preset threshold value, and compare the first count value obtained by the first counting module within the preset clock period with the first preset threshold value, and determine whether to output a crystal oscillator stop signal based on the comparison result; the second comparison module is used to obtain the second count value, and when it is determined that the second count value is equal to the preset clock period, output a clear signal to the first counting module.

[0058] This embodiment combines Figure 4 right Figure 2 To further explain this, a low-frequency internal RC clock is used as the normally-on clock for the crystal oscillator monitoring circuit and the crystal oscillator recovery circuit to reduce chip power consumption. The output signal is designated as RCL. In this embodiment, the low-frequency RC clock frequency is set to 32 kHz. This embodiment first divides the real-time monitored crystal oscillator clock signal XTAL_CLK by 2048 using the frequency divider DIV / 2048. This generates the divided clock signal XTAL_2048 and sends it to the first counting module CNT0.

[0059] The present invention repeatedly monitors the crystal oscillator clock signal according to a preset clock cycle. Each preset clock cycle is equivalent to a monitoring window. Specifically, the present invention collects crystal oscillator clock signals over a period of time (preset clock cycles) to determine whether oscillation has stopped. Specifically, this embodiment uses a second counting module CNT1 to record the size of the monitoring window, with every 256 RCL clock cycles serving as a monitoring window. When CNT1 reaches 256, it sends a clear signal to the first counting module CNT0, clearing CNT0 to 0, indicating the end of signal monitoring. Therefore, this embodiment monitors the normal operation of the external crystal oscillator every 256 RCL clock cycles. The monitoring method is to sample the divided clock signal and record it with the first counting module CNT0. The CNT0 count is incremented by one after each sampling. Then, a first comparison module compares the first count value recorded by CNT0 within 256 RCL clock cycles with a first preset threshold (this threshold can be set by the user according to their needs). The first preset threshold in this embodiment is the user's desired number of clock cycles, N, divided by 2. In this embodiment, N / 2 is selected as the comparison value for the first comparison module to reduce the probability of circuit misjudgment. In this embodiment, as long as the actual count value (first count value) of the first counting module is greater than or equal to the expected comparison value (N / 2), it can be determined that the crystal oscillator clock signal continues to exist, the external crystal oscillator is operating normally, and the crystal oscillator monitoring circuit output level signal switch_xtal is 0 (low level); otherwise, it indicates that the external crystal oscillator has stopped oscillating, and a clock abnormal interrupt will be triggered at the same time, and the crystal oscillator monitoring circuit output level signal switch_xtal is 1 (high level), which serves as a crystal oscillator stop flag.

[0060] The crystal oscillator monitoring circuit will send the judgment result, that is, the level signal switch_xtal, to the clock switching circuit. The clock switching circuit mainly determines whether the clock needs to be switched by the state (high or low) of the level signal switch_xtal. The embodiment of the present invention adopts a glitch-free clock switching circuit, which can achieve glitch-free and smooth switching of the clock, effectively avoiding the situation where the program runs away due to clock glitches. In this embodiment, when the clock switching circuit detects that switch_xtal is 1, it means that the external crystal oscillator has stopped oscillating, and the chip operating clock is smoothly switched to the internal high-frequency RC clock RCH. The internal high-frequency RCH clock frequency is close to the crystal oscillator clock frequency, which can achieve senseless switching; when it is detected that switch_xtal changes from 1 to 0, it means that the external crystal oscillator has resumed working, and this circuit will automatically switch the operating clock back to the crystal oscillator clock.

[0061] In the embodiments of the present invention, specific reference is made to Figure 2The crystal oscillator monitoring circuit also includes a first selector MUX, a first flip-flop DFF1, a first inverter INV, a second flip-flop DFF2, and a third flip-flop DFF3. The first selector MUX receives the comparison values ​​output by the first and second comparison modules, selects the two comparison values, and outputs a result that meets the requirements to the first flip-flop DFF1. This result is triggered and inverted by the first flip-flop DFF1, the first inverter INV, the second flip-flop DFF2, and the third flip-flop DFF3 before outputting a level signal switch_xtal. The first, second, and third flip-flops DFF1, DFF2, and DFF3 also use a low-frequency internal RC clock as their operating clock.

[0062] At the same time, after the external crystal oscillator stops oscillating, the CPU core (exception handling circuit) will detect the abnormal clock interruption, and the corresponding module can take corresponding chip protection measures as needed. For example, it can stop the generation of PWM waveforms, or if the system is in sleep mode, the crystal oscillator clock failure event will trigger wake-up.

[0063] After the crystal oscillator recovery circuit detects the relevant signal of the crystal oscillator stopping, the crystal oscillator recovery circuit starts the crystal oscillator restart work. Figure 3 The crystal oscillator recovery circuit includes a third counting module, a third comparison module, a signal trigger module, and a first AND gate. The third counting module, such as a second counter S_CNT, is configured to obtain the RC clock signal and count the RC clock signal to obtain a third count value. The third comparison module obtains and compares a preset time value and the third count value, and clears the third counting module when the third count value equals the preset time value. The signal trigger module obtains the third count value and outputs a corresponding level signal based on the magnitude of the third count value. The first AND gate obtains the level signal and a crystal oscillator stop flag, and outputs a crystal oscillator recovery signal when the stop signal is received and the level signal is at a preset level.

[0064] This embodiment Figure 3 To explain in detail, the second counter S_CNT inside the crystal oscillator recovery circuit uses the same internal low-frequency RC clock RCL as its operating clock. S_CNT can count to more than 1 second, meaning the maximum count value of S_CNT must be greater than 1 second. This requires the count time to be greater than the crystal oscillator's start-up stabilization time. If the count time is less than the crystal oscillator's start-up stabilization time, a false restart will occur. If the crystal oscillator start-up circuit fails to successfully start oscillation and then initiates a restart, the crystal oscillator clock will never reach a stable state. When the third count value recorded by the second counter S_CNT reaches the preset time value EXP_VALUE (preset time value), the second counter S_CNT is cleared and counted again until the external crystal oscillator successfully restarts.

[0065] The crystal oscillator recovery circuit generates a restart signal of a corresponding level based on the count value of the seconds counter S_CNT. During the first 1ms of each S_CNT recount, the restart signal output by the signal trigger module is low. After 1ms, until S_CNT is cleared, the restart signal output by the signal trigger module remains high. The first AND gate performs an AND logic operation on the restart signal with the switch_xtal flag signal output by the crystal oscillator monitoring circuit. When the restart signal is high, it generates the restart_xtal signal, the crystal oscillator restart flag. This signal is used to restart the external crystal oscillator or, if a crystal oscillator start-up circuit is installed, the crystal oscillator start-up circuit.

[0066] In an embodiment of the present invention, the crystal oscillator recovery circuit may further include a fourth flip-flop DFF4, which also uses the low-frequency internal RC clock as its operating clock. The fourth flip-flop DFF4 obtains the count value output by the seconds counter S_CNT, processes the count value, and outputs a restart signal to the first AND gate.

[0067] The present invention provides an oscillation stop monitoring circuit, which can not only monitor whether the crystal oscillator clock is working normally, but also take measures such as clock switching and exception handling to avoid abnormal chip operation. It also has a crystal oscillator recovery circuit, which increases the possibility of restoring the normal operation of the crystal oscillator by restarting the crystal oscillator multiple times, thereby effectively enhancing the reliability and accuracy of the chip system.

[0068] In addition, the present invention uses a lower-frequency internal RC clock as the working clock. Only when the crystal oscillator stops oscillating is the high-frequency RC clock turned on and switched. This can also reduce the operating power consumption of the chip and the sleep power consumption in low-power mode. Finally, when the crystal oscillator clock is abnormal, the operating clock is switched to a high-frequency RC clock with a similar frequency instead of a low-frequency RC clock, thereby realizing seamless clock switching and ensuring stable operation of the system.

[0069] Another embodiment of the present invention provides a clock oscillation stop monitoring method, which is applied to the clock oscillation stop monitoring circuit provided by the present invention. The specific implementation process of the method includes the following steps.

[0070] First, obtain a crystal oscillator clock signal, and monitor the crystal oscillator clock signal for oscillation stop according to a preset clock cycle, and output a crystal oscillator stop flag when the crystal oscillator clock signal is detected to be abnormal; and monitor the crystal oscillator clock signal for oscillation stop according to a preset clock cycle, and output a crystal oscillator stop flag when the crystal oscillator clock signal is detected to be abnormal.

[0071] Regarding the output of the crystal oscillator stop flag, an embodiment of the present invention can first obtain a first preset value, and divide the crystal oscillator clock signal according to the first preset value to obtain a divided clock signal, and count the divided clock signal, and record the total number of divided clock signal cycles within one preset clock cycle as a first count value; obtain a first preset threshold, and compare the first count value with the first preset threshold; if the first count value is greater than or equal to the first preset threshold, output the crystal oscillator stop flag; obtain a working clock signal, and count the working clock signal to obtain a second count value; when the second count value is equal to the preset clock cycle, clear the first count value and count again.

[0072] After receiving the crystal oscillator stop flag, the operating clock of the chip system is switched to a high-frequency RC clock, and preset protection measures are obtained to protect the chip system. At the same time, a crystal oscillator restart signal is output to stimulate the external crystal oscillator to restart until the external crystal oscillator resumes work.

[0073] Regarding the output of the crystal oscillator stop flag, an embodiment of the present invention first obtains a working clock signal, counts the working clock signal to obtain a third count value, and outputs it in real time; obtains a second preset threshold, compares the third count value with the second preset threshold, and outputs a corresponding level signal based on the comparison result; outputs a crystal oscillator restart signal when the crystal oscillator stop signal is received and the level signal is a preset level; obtains a preset time value, and when the third count value is equal to the preset time value, clears the third count value and recounts until the external crystal oscillator resumes operation. When it is determined that the external crystal oscillator has resumed operation, a crystal oscillator recovery flag is output, and the operating clock of the chip system is switched to the external crystal oscillator clock based on the crystal oscillator stop flag.

[0074] In a specific embodiment of the present invention, the crystal oscillator clock signal (XTAL_CLK) to be monitored is first divided by 2048 to generate a divided clock signal XTAL_2048. A counter CNT1 is then used to record the size of the monitoring window. In this embodiment, every 256 RCL clock cycles (preset clock cycles) is used as the monitoring window. When CNT1 reaches 256, the counter CNT0 is cleared, indicating the end of a monitoring cycle. In this embodiment, the crystal oscillator is monitored for proper operation every 256 RCL clock cycles. This monitoring method involves sampling the divided clock signal and recording it with the counter CNT0. Each time a sample is taken, the CNT0 count is incremented by one. The CNT0 count value recorded within 256 RCL clock cycles is compared with a desired comparison value. To minimize the probability of misjudgment, in this embodiment, the desired number of crystal oscillator clock cycles, N, is divided by 2 to form the desired comparison value (N / 2). As long as the actual CNT0 count value is greater than or equal to the desired comparison value, the crystal oscillator is considered to be operating normally. The monitoring circuit outputs the switch_xtal signal to indicate whether the crystal oscillator has stopped oscillating. If switch_xtal is 0, it indicates that the crystal oscillator clock is working normally. Otherwise, if switch_xtal is 1, it indicates that the crystal oscillator clock has stopped oscillating and a clock abnormal interrupt will be triggered.

[0075] When switch_xtal is 1, the seconds counter value is obtained and a restart signal is generated based on the value of the seconds counter S_CNT. Specifically, the restart signal is low during the first 1ms of each S_CNT restart. From 1ms onward until S_CNT is cleared, the restart signal remains high. The restart signal is ANDed with the switch_xtal flag signal to generate the restart_xtal signal, which is used to restart the crystal oscillator. Furthermore, the seconds counter S_CNT is cleared to 0 after the count reaches the preset time value EXP_VALUE.

[0076] The clock stall monitoring method of the present invention uses a window detection method to detect the number of crystal oscillator clocks within a period of time (preset clock cycle) and compare it with the expected number of clocks to determine whether the crystal oscillator has failed, which greatly reduces the probability of misjudgment. In addition, after detecting that the crystal oscillator has stalled, the present invention attempts to restore the crystal oscillator by restarting it, which can effectively solve the problem of stalling caused by factors such as poor contact. Once the crystal oscillator is detected to have recovered, the hardware circuit automatically switches to a relatively accurate crystal oscillator clock.

[0077] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be repeated here.

[0078] In addition, in conjunction with the clock stop monitoring method in the above embodiment, the present invention can provide a storage medium for implementation. The storage medium stores a computer program; when the computer program is executed by a processor, any one of the stop monitoring methods in the above embodiment is implemented.

[0079] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be repeated here.

[0080] An embodiment of the present invention further provides a chip system, including a memory and a processor, and the system further includes any one of the clock stop monitoring circuits in the above embodiments.

[0081] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be repeated here.

[0082] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiment methods can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-described methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0083] Those skilled in the art should understand that the various technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A clock stop monitoring circuit, used in a chip system, characterized in that: The clock stop monitoring circuit includes a crystal oscillator monitoring circuit, a clock switching circuit, a crystal oscillator recovery circuit and an abnormality processing circuit; wherein, The input end of the crystal oscillator monitoring circuit obtains a crystal oscillator clock signal from an external crystal oscillator, and the output end is connected to the input ends of the clock switching circuit, the crystal oscillator recovery circuit, and the abnormality handling circuit respectively; the crystal oscillator monitoring circuit repeatedly performs oscillation stop monitoring on the crystal oscillator clock signal according to a preset clock cycle, and when the crystal oscillator monitoring circuit detects that the crystal oscillator clock signal is abnormal, it outputs a crystal oscillator stop flag to the clock switching circuit, the crystal oscillator recovery circuit, and the abnormality handling circuit; The output end of the crystal oscillator recovery circuit is connected to the clock switching circuit and the external crystal oscillator respectively; when the crystal oscillator recovery circuit receives the crystal oscillator stop flag, it outputs a crystal oscillator restart signal to the external crystal oscillator, and outputs a crystal oscillator recovery flag to the clock switching circuit after the external crystal oscillator is successfully restarted; The output end of the clock switching circuit is connected to the external crystal oscillator and the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator stop flag, the operating clock is switched to the high-frequency RC clock; when the clock switching circuit receives the crystal oscillator recovery flag, the operating clock is switched to the external crystal oscillator; The abnormality processing circuit is used to obtain a preset protection measure to protect the chip system after receiving the crystal oscillator stop flag; The crystal oscillator recovery circuit includes a third counting module, a third comparing module, a signal triggering module and a first AND gate; wherein, The third counting module is used to obtain a working clock signal and count the working clock signal to obtain a third count value; The third comparison module obtains a preset time value and a third count value and compares them, and resets the third count module when the third count value is equal to the preset time value; The signal trigger module obtains the third count value and outputs a corresponding level signal according to the size of the third count value; The first AND gate obtains the level signal and the crystal oscillator stop flag, and outputs a crystal oscillator recovery signal when the crystal oscillator stop flag is received and the level signal is a preset level.

2. The clock oscillation stop monitoring circuit according to claim 1, wherein: The clock stop monitoring circuit also includes a crystal oscillator starting circuit; wherein, the input end of the crystal oscillator starting circuit is connected to the crystal oscillator recovery circuit, and the output end is connected to the crystal oscillator monitoring circuit, and the crystal oscillator starting circuit is used to convert the analog signal of the external crystal oscillator into a digital signal of the crystal oscillator clock signal and send it to the crystal oscillator monitoring circuit; receive the crystal oscillator restart signal output by the crystal oscillator recovery circuit and restore the external crystal oscillator.

3. The clock oscillation stop monitoring circuit according to claim 1, wherein: The crystal oscillator monitoring circuit and the crystal oscillator recovery circuit use a normally-on low-frequency RC clock as their working clock, and the low-frequency RC clock outputs a working clock signal.

4. The clock oscillation stop monitoring circuit according to claim 3, wherein: The crystal oscillator monitoring circuit includes a frequency division module, a first counting module, a second counting module, a first comparing module, and a second comparing module; in; The frequency division module is used to obtain the crystal oscillator clock signal and divide it according to a preset frequency division value, generate a divided clock signal and send it to the first counting module; The first counting module is used to obtain a frequency-divided clock signal and a working clock signal, operate according to the working clock signal, and count the frequency-divided clock signal; The second counting module is used to obtain the working clock signal and count the working clock signal to obtain a second count value; The first comparison module is used to obtain a first preset threshold value, and compare the first count value obtained by the first counting module within the preset clock cycle with the first preset threshold value, and determine whether to output a crystal oscillator stop signal according to the comparison result; The second comparison module is configured to obtain the second count value, and output a reset signal to the first counting module when determining that the second count value is equal to the preset clock period.

5. A clock stop monitoring method, characterized in that: Applied in the clock stop monitoring circuit according to any one of claims 1 to 4, the method comprises: Acquire a crystal oscillator clock signal, and monitor the crystal oscillator clock signal for oscillation stop according to a preset clock cycle, and output a crystal oscillator stop flag when the crystal oscillator clock signal is detected to be abnormal; After receiving the crystal oscillator stop flag, the operating clock of the chip system is switched to a high-frequency RC clock, and a preset protection measure is obtained to protect the chip system, and at the same time, a crystal oscillator restart signal is output to stimulate the external crystal oscillator to restart, until the external crystal oscillator resumes operation; When it is determined that the external crystal oscillator has resumed operation, a crystal oscillator resumption flag is output, and the operating clock of the chip system is switched to the external crystal oscillator clock according to the crystal oscillator stop flag.

6. The clock oscillation stop monitoring method according to claim 5, characterized in that: The method of monitoring the crystal oscillator clock signal for oscillation stop according to a preset clock cycle and outputting a crystal oscillator oscillation stop flag when the crystal oscillator clock signal is detected to be abnormal comprises: Obtaining a first preset value, and dividing the frequency of the crystal oscillator clock signal according to the first preset value to obtain a divided clock signal, and counting the divided clock signal, recording the total number of divided clock signal cycles within one preset clock cycle as a first count value; Obtaining a first preset threshold, and comparing the first count value with the first preset threshold; if the first count value is greater than or equal to the first preset threshold, outputting a crystal oscillator stop flag; A working clock signal is acquired, and the working clock signal is counted to obtain a second count value; when the second count value is equal to the preset clock period, the first count value is cleared and counted again.

7. The clock oscillation stop monitoring method according to claim 5, characterized in that: The output of the crystal oscillator restart signal for stimulating the external crystal oscillator to restart the operation includes: Obtaining a working clock signal, counting the working clock signal to obtain a third count value, and outputting the third count value in real time; Obtaining a second preset threshold, comparing the third count value with the second preset threshold, and outputting a corresponding level signal according to the comparison result; When the crystal oscillator stop flag is received and the level signal is at a preset level, a crystal oscillator restart signal is output; A preset time value is obtained, and when the third count value is equal to the preset time value, the third count value is cleared and counted again until the external crystal oscillator resumes operation.

8. A chip system comprising a memory and a processor, characterized in that: It also includes the clock stop monitoring circuit according to any one of claims 1 to 4.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the clock oscillation stop monitoring method according to any one of claims 5 to 7 when running.

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